GB2466233A

GB2466233A - Frequency synthesizer

Info

Publication number: GB2466233A
Application number: GB9008089A
Authority: GB
Inventors: Alain Poezevara; Didier Quievy; Jean Anastassiades; Francis Desjouis
Original assignee: Thomson CSF SA
Current assignee: Thales SA
Priority date: 1989-04-11
Filing date: 1990-04-10
Publication date: 2010-06-23
Anticipated expiration: 2010-04-10
Also published as: IT9067230A0; GB9008089D0; GB2466233B; DE4011572C2; IT1246699B; IT9067230A1; DE4011572A1; FR2706099B1; FR2706099A1

Abstract

The synthesizer comprises a phase-locked loop including successively: a variable frequency oscillator 1; a mixer 2 receiving at its first input the signal generated by said oscillator 1 and at its second input a basic reference frequency; a frequency reducing chain; a phase detector 6 receiving the signal delivered by said chain and a predetermined frequency FR1 defining the step size of the output frequency; and a low pass network 8 delivering as output the control voltage for the variable frequency oscillator 1. The frequency reducing chain includes, in cascade between said variable frequency oscillator 1 and said phase detector 6, a plurality of frequency converter stages 20, 20',20", each comprising an heterodyne mixer receiving the signal from the preceding frequency converter stage and a programmable reference frequency, and delivering as output, through a low pass filter network 30, 30', 30", the signal applied to the next frequency converter stage. The determination of the output frequency of said variable frequency oscillator results essentially from a combination of the commands of said programmable reference frequencies.

Description

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Frequency synthesizer The present invention relates to a frequency synthesizer, i.e., to a circuit allowing to generate a signal of predeter-mined frequency chosen within a certain range of variation among a plurality of discrete frequencies spaced from each other by a given pitch.

The performance of the devices into which the frequency synthesizers are built are closely related to the qualities of the latter, which are in particular -the stability of the generated frequency, both short-term stability (referred to as phase stability) and long-term sta-bility (small fluctuationsF/F); in frequency synthesizers, the causes of instability are essentially the internal noise of the various stages of the synthesizer and the generation, at parasitic levels, of frequencies distinct from the desired frequency due to the fact that, when a frequency is generated through synthesis, it is never possible to fully eliminate the basic frequencies (and their harmonics) which have been combined to generate the end frequency; -rapid switching between the various frequency values it is desired to obtain the shortest possible delay between the time when tThe control signal (in general, a digital control word) corresponding to a desired new frequency is applied to the frequency synthesizer and the time when the latter effec-tively delivers the desired frequency; -a range of frequencies as wide as possible; -a high number of discrete values of frequency capable of being generated. This quality generally goes against the pre-ceding une as a matter of fact, the frequency synthesizers witi very small pitch currently implemented generally operate only in a narrow band; -the spectral purity of the generated signal, corresponding to a low level of parasitic lines (non-harmonic lines) with respect to the line of the generated signal.

The known frequency synthesizer circuits use essentially two basically different techniques: direct synthesis and in-direct synthesis.

Direct synthesis consists in generating frequencies spaced by a constant interval, either through switching of seperate sources (non-coherent direct synthesis) or from a single stan- dard source whose frequency, equal to the pitch to be obtai-ned, is applied to the input of a frequency multiplying chain with variable order (coherent direct frequency); the frequency multiplying chain is generally formed by a comb generator that produces an energy distributed over harmonics of the basic frequency and at whose output the desired frequencies are se-lected through switching of harmonic filters.

The number of frequencies that can be generated by such a basic circuit being limited, if it is desired to obtain a great number of frequencies, use is made of successive mixings of signals delivered by intermediate direct synthesis chains, for example three chains, one generating 1 low-pitch frequen-cies, the second m medium-pitch Frequencies, and the third n coarse-pitch frequencies at the output of the mixer,.there will thus he l;<mxn fine-pitch frequencies available.

This technique allows to achieve an excellent performance as to the phase stability and the rapidity of switching bet-ween frequencies (the latter depending only on the rapidity of switching harmonic filters, which can be high in the case of digitally controlled filters).

On the other hand, it is relatively difficult to achieve a low level of parasitic lines, for this requires a careful isolation of the various circuits switching the sources (in the case of non-coherent synthesis) or rejecting the undesi- red lines by harmonic filters (in the case of coherent syn-thesis); these parasitic lines are due to the interniodulation products created by the successive mixings.

In practice, it is possible to obtain a satisfying spec- tral purity only in relatively narrow ranges of variation (a-bout 10 to 12 % at cnost about the center frequency), which excludes the use of this technique in many applications where these values are insufficient.

In addition, the requirement of using high-quality varia-ble switchable filters leads to a significant cost increase forthe synthesizer.

The second frequency synthesis technique is the indirect synthesis, which uses a phase-locked loop and also allows t3 generate frequencies spaced by a constant interval from a sin-gle standard source.

The conventional embodiment of such a type of circuit - to which type the present invention belongs -is the hetero-dyne loop with frequency conversion and programmable frequency division, illustrated in a schematic manner by figure 1 of the accompanying drawings.

This circuit comprises essentially a variable-frequency oscillator 1, generally a voltage-controlled oscillator (VCO) delivering an output frequency FS which is a function of a control signal (analog voltage) which is applied to it as an input This output frequency FS is applied to a first input of a mixer 2 which receives at its second input a reference fre- quency FR. The output of the mixer 2 is applied to a program-

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mable frequency divider (i.e., a divider whose division order N is chosen by a logic-type command, for example a digital The output signal from the frequency divider 5 is applied to one of the inputs of a phase detect3r circuit 6 which re-ceives at its second input a signal with a frequency equal t:) the pitch p of variation of the frequencies. The output voltage of the phase detector 6 is applied to a low-pass fil- ter 8 whose output signal is the control voltage for the vol-tage-controlled oscillator 1.

Thereference frequency FR and the pitch p are produced from a standard source 3 (crystal fixed-frequency oscillator) that delivers a frequency FQ. This frequency FQ is, for one, increased by a frequency multiplier 4 with a fixed order M delivering the reference frequency FR which is thus equal to MxFQ and, for another, decreased by a frequency divider 7, also with a fixed order P, so as to generate the frequency FQ/P equal to the pitch.

It can be seen that the oscillator 1, the mixer 2, the divider 5, the phase detector 6 and the low-pass filter 8 form a phase-locked loop whose balance is controlled by the phase detector 6 and whose balance level -and consequently whose frequency FS -is controlled by the division order N of the divider 5, which is programmable.

At balance, the two input frequencies applied to the phase detector 6 are strictly identical, and the system balance equa-tion is FS H.. (N/P)] x Q. Thus it can be seen that, by modifying the order N of the variable-order divider, it is possible to vary the output fre-quency FS of the oscillator by a quantity FQ/P equal to the pitch p to be achieved (this pitch being determined by the order of division of the fixed-order divider 7).

Such a generator with indirect synthesis has not the band-width limitations of the generators with direct synthesis.

As a matter of fact, for such a generator with indirect synthesis, the only theoretical bandwidth limitation is that of the variable-frequency oscillator 1, which bandwidth can be chosen as wide as desired.

However, chosing an oscillator with a wide operating band- width necessarily implies a significant sensitivity of varia-tion of the frequency (the wider the bandwidth, the greater the correlative frequency deviation for the same variation of the control voltage), hence a high sensitivity to thermal noise and a poor frequency stability.

A further limitation of this circuit is due to the fact that the parameters of the low-pass correcting network 8 must he optimized as a function of the cutoff frequency of the loop, which requires a tradeoff between the rapidity of frequency switching (as the switching time cannot be shorter than the convergence time of the loop) and the phase stability (a good loop stability requiring a relatively long time constant).

And last but not least, the major disadvantage of such a frequency synthesizer results from the presence of the pro- grammable divider (circuit 5) which is a circuit that, by na-ture, produces a high phase noise.

This divider being one of the elements of the loop, any phase fluctuation it introduces and that can be observed at its output will be subsequently found at its input, hut multi-plied by N.Moreover, if this is considered in terms of power, the phase noise at the output of the frequency synthesizer will be multiplied by N2.

This consequently limits in a significant manner the va-lues of N that may he chosen. For certain values of N, the

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noise becomes even predominant, which obliges to strictly li- mit the range of variation of frequency much under the capa-bibilities of the variable-frequency oscillator itself.

Thus the maximum value reached by this order determines the performance of the synthesizer, and an acceptable phase stability can Finally only be obtained by chaining a phirality of phase-locked loops (for example a fine-pitch loop, a me-diurn-pitch loop, and a coarse-pitch loop), which makes the device very costly to implement; thus, with respect to direct synthesis, the advantage that resulted from the simplicity of the basic schematic is lost.

Therefore, for a comparable level of performance and in spite of the difficulties of implementation mentioned above, the direct synthesis often appears to be more interesting in practice than indirect synthesis.

However, in either case, one comes to circuits which are complex and difficult to implement, which highly increases the cost of the frequency synthesizer thus obtained.

A purpose of the present invention is to remedy these va-rious disadvantages by proposing a frequency synthesizer that combines the respective advantages of the devices with direct synthesis and with indirect synthesis while having a relati- vely simpl&'structure and avoiding the use of complex and cos-tly circuits and components.

More precisely, as this will be seen hereinafter, a fcc- quency synthesizer according of the present invention, in spi-te of its structure with a relatively simple principle, may have cumulatively the following qualities:

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-very low phase noise; -stability and spectral purity (low level of parasitic lines) of the frequency obtained; -very wide operating bandwidth in spite of a very fine pitch of variation; in an embodiment that will he described herein-after, it will re seen that it possible to cover without dif-.

ficulty a range of 2000-2500 IHz by 5-MHz steps in a conti-nuous manner; however, this example is only illustrative and the technique according to the present invention can without major difficulty cover a bandwidth of about one octave; -rapid switching on frequency changes: in the embodiment that will be described, this switching time is of about 5 is.

These qualities are obtained by starting from the conven- tional basic schematic of the frequency synthesizer with pha-se-locked loop of the prior art described above with reference to Figure 1, i.e., a frequency synthesizer with a single pha- se-locked loop, this loop comprising successively a varia-ble-frequency oscillator delivering at its output a signal with an output frequency which is a function of a control sig-nal applied as an input; a mixer circuit, receiving at its first input the signal produced by this variable-frequency oscillator, and at its second input a basic reference frequen-cy; a frequency-reducing chain receiving the signal delivered by the output of this mixer circuit; a phase detector circuit receiving at its first input the signal delivered by this fre-quency reducing chain, and at its second input at least one predetermined frequency defining the desired pitch of varia- tion of this output frequency; and a low-pass filtering net- work receiving as input the output signal from the phase de- tector circuit and delivering at its output the control vol-tage for the variable-frequency oscillator.

The frequency synthesizer of the present invention is cha-racterized in that

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-said frequency-reducing chain is essentially without a pro-grammable Frequency divider circuit; -said frequency-reducing chain includes in cascade hetween the variable-frequency oscillator and the phase detect:r cir- cuit, a plurality of frequency-converter stages, each compri-sing a mixer circuit, this mixer circuit eing an heterodyne mixer circuit receiving at its first input the signal from the output of the preceding frequency converter or, for the first stage, said output frequency of said variable-frequency oscillator; receiving at its second input a programmable refe-rence Frequency or, in the case of the first stage, said 5asic reference frequency; and delivering at its output, through a low-pass filtering network, the signal applied to the subse-quent frequency-converter stage or, in the case of the last stage, to the first input of the phase detector circuit; -the range of variation of the possible frequencies at the output of the frequency-converter stages decreases from the input to the output of the frequency-reducing chain; and -the determination of the output frequency of the variable-frequency oscillator results essentially from a combination of the commands of said programmable reference frequencies.

This configuration allows to avoid using the programmable frequency dividers of the frequency synthesizers of the prior art -and consequently to eliminate the disadvantages, in par-ticular the high phase noise, which are inherent to them and which become prohibitive when the orders of division become significanC-, while retaining a single phase-locked loop, which allow to ensure a fast switching of the frequencies.

Thus, according to the present invention, a plurality of intermediate frequency conversions is achieved through the addition of additional mixers, while reducing the range of variation of the intermediate frequencies along the frequency-reducing chain.

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It should be noted that although it is advantageous t eliminate any programmable frequency divider in the frequency- reducing chain, it is not indispensable that the frequency-reducing chain 5e totally without such a circuit.

As a matter of fact, it has be seen above that frequency dividers introduce a phase noise mainly for the high orders of multiplication (the phase noise power being multiplied by the square N2 of the order of multiplication N), so the fre- quency-reducing chain of the frequency synthetizer of the pre-sent invention could possibly include a programmable frequency divider stage, provided the maximum order of division therof remains low.

That is the reason why by "essentially without programcna- hie frequency divider circuit", it will be understood a fre-quency-reducing chain in which the changes in frequency result mainly -but not necessarily exclusively -from the heterodyne mixing performed by the various frequency converter stages.

Advantageously, the predetermined frequency defining the pitch of variation which is applied to the phase detector cir-cuit is also a programmable frequency so as to have avaitable a plurality of different Frequencies, selectable and combina-ble with said programmable reference frequencies.

Very advantageously, the basic reference frequency and the programmable reference frequencies as well as, if such is the case, the predetermined frequency defining the pitch of variation, are obtained by means of frequency generator circuits with direct synthesis.

It is also possible to generate in a very simple manner the frequency hops necessary to cover the full band of output frequencies by generating a very high number of different fre-quencies wit'rnut ever having a high order of multiplication.

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The absence of high orders of multiplication allows to have frequency generators with direct synthesis, each of which has a relatively simple structure since they generate only a relatively small number of frequencies (typically between two and five), therefore with a high signal quality in spite of a relatively simple basic structure.

Moreover, it can be seen that, thanks to these successive frequency conversions, in no point of the chain there is a high order of multiplication. This has a dual advantage -first, the circuits that generate the various reference Fre- quencies can be relatively simple and all operate under opti- mum conditions, which allows to combine a low cost of the cir-cuits with a good quality of the signal; and -the qualities of these signals will be retained in spite of the mixings, for the various mixers in the frequency con- verter stages will all operate with input and output frequen-cies varying in relatively limited bands, hence producing a low level of parasitic lines (as a matter of fact, the level of the intermodulation products is the more so high as the frequencies applied as input vary over a wide band).

Although it is preferred, the use of direct-synthesis ge-nerators for the programmable reference frequencies is not indispensable and it is possible, as a variant, to use other types of generators, for example phase-locked systems with indirect synthesis (each reference frequency generator being then implemented according to the basic schematic in Figure 1).

Using direct-synthesis generators for the reference fre-quencies is preferable as regards the rapidity of switching and phase noise. It is in addition advantageous to he able to control the generators from a single frequency reference, i.e., the various frequency generator circuits with direct synthesis operate in a coherent manner from a single fixed-frequency oscillator delivering a common standard frequency.

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It is possible to use, as a variant, several separate standard frequencies (i.e., several reference crystal oscil- latocs) but the phase-locked loop would no longer be a syn- chronoLis loop, which would introduce additional parasitic ii-nes and would impair the performance of the loop, possibly as regards the switching time.

In the case where the reference frequency generators are direct-synthesis circuits, they may advantageously have the following characteristics -at least some of the frequency generator circuits with di-rect synthesis are frequency multiplier circuits; -at least some of the frequency multiplier circuits include a comb generator in series with a programmable pass-band fil-ter, a frequency divider with a fixed order being possibly placed at the input of the comb generator; -at least some of the frequency generator circuits with di- rect synthsis are circuits producing fractional orders of rnul-t iplicat ion; -at least some of the circuits producing fractional orders or multiplication include a programmable frequency divider, a frequency multiplier with a fixed order being possibly pla-ced at the input of this circuit; and -at least some of the circuits producing fractional orders of multiplication include a mixer circuit receiving at its first input a standard frequency or a multiple thereof, and receiving at its second input a frequency delivered by the programmable frequency divider, the output signal from this mixer circuit being applied to a low-pass filter controlled simultaneously with the programmable frequency divider.

Preferably, all the heterodyne mixer circuits of the fre- quency-converter stages of the frequency-reducing chain per- form an infradyne mixing, i.e., the bandwidth of the interme-diate frequencies is successively reduced, or "compressed", in each stage. -12

However, this caracteristic is not indispensable for im-plementing the present invention, the essential being that, on the whole, there is a reduction of the bandwidth between the input and the output of the frequency-reducing chain taken as a whole; it is also possible to envisage that, at one of the frequency converter stages, the reduction in intermediate frequency is not accompanied by a correlative reduction of the bandwidth of the intermediate frequency produced at the output, but it would nevertheless be necessary to compensate for this non-reduction of the bandwidth by an additional re-ductionin another stage, upstream or downstream, to obtain an equivalent overall compression.

If it is desired to further increase the resolution of the pitch of variation of the synthesizer, it is possible to use for the basic reference frequency a programmable frequency delivered itself y a frequency synthesizer circuit generating frequencies with a very fine pitch extending over a narrow band, SO as to obtain at the output of the variable-frequency oscillator frequencies with this very fine pitch but extending over a wide bandwidth.

One has thus a fine pitch produced by the frequency syn-thesizer proper of the present invention, and an additional "superfine" pitch produced by a Furtrier synthesizer (which may also have a structure comparable to that of the invention), and it is possible to combine these two pitches in the desired manner to obtain, in the IuU useful bandwidth, any desired frequency at this superfine pitch.

This configuration is advantageous due to the fact that, if a single pitch was used and that it was attempted to reduce it, one woud create intermodulatjon products at relatively low frequencies that must be filtered, thus reducing the band-width of the loop and consequently its rapidity of switching.

-13 -On the other hand, if a fine pitch and a superfine pitch are combined as in the proposed variant, it is possible to retain all the inherent qualities of the initial system, as will he explained in greater detail hereinafter.

Finally, the present invention proposes to add to the fre-quency synthesizer a prepositioning circuit allowing to speed up the acquisition of the selected frequency and especially to compensate for the effect of the drifts due to external factors (in particular thermal drifts) whose amplitude is hi gher than the lock-in range of the loop.

This prepositioning circuit comprises -a combining circuit, very advantageously a frequency-phase detector whose output is connected to the control input of the variable-frequency oscillator; -switching means activated during a loop prepositioning pre-liminary phase and allowing, for one, to apply to one of the inputs of this combining circuit the signal delivered by the last frequency converter stage, and to the other input of the combining circuit said predetermined frequency defining the pitch of variation and, for another, to inhibit the loop feed-back control; and -between the combining circuit and the control input of the variable-frequency oscillator, means for memorizing the level of the control signal reached at the end of the prepositioning phase, so that this signal level determines the starting point for the convergence of the loop when the latter switches back to the Feedback control mode after desactivation of the swit-ching means.

Preferably, the prepositioning circuit of the voltage-controlled oscillator comprises in addition converter means whose output is connected to the control input of the variable- frequency oscillator, these means receiving as input a fre-quency control signal corresponding to the frequency at which -14 -

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it is desired to position the variable-frequency oscillator, as well as, between these converter means and the control in-put of the variable-frequency oscillator, means for storing this corresponding level of the control signal so that this signal level determines the starting point of the prepositio-fling of the loop upon activation of the switching means.

Other features and advantages of the present invention will become apparent from the following detailed description of preferred embodiments given as a non-limitative example with reference to the accompanying drawings, in which -Figure 1, already mentioned, is a block diagram illustrating in a simplified manner a prior art frequency synthesizer with a phase-locked loop; -Figure 2 is a block diagram illustrating in a simplified manner a frequency synthesizer with a phase-locked loop accor-ding to an embodiment of the present invention; -Figure 3 shows an embodiment of the frequency synthesizer in Figure 2, allowing to cover in a continuous manner the ran-ge from 2000 MHz to 2500 MHz by 5.-MHz steps; -Figure 4 shows the details of a reference frequency genera-tar with direct synthesis allowing to obtain fractional orders of multiplication; and -Figure 5 shows a further, optimized possible embodiment of the frequency synthesizer of Figure 2, also allowing ta cover in a continuous manner the range from 2000 MHz to 2500 MHz by 5-MHz steps.

-15 -General principle of the synthesizer.

In figure 2, the reference numerals 1, 2, 3, 4, 6 and 8 denote elements homologuous of the elements in Figure 1 having the same reference numerals: the variable oscillator 1, which is generally a voltage-controlled oscillator (VCO), delivers an output Frequency FS applied to one of the inputs of a mixer 2 which receives at its second input a basic reference fre-quency FR4 generated by increasing, by means of a multiplier circuit with a fixed order 4, a standard frequency FQ genera-ted by a crystal oscillator 3.

The output signal of the mixer 2 is applied to a frequen-cy-reducing chain, and the output signal from this frequency-reducing chain is applied to one of the inputs of a phase detector 6 which receives at its second input a frequency FR1 defining the desired pitch of variation of the output frequency. The phase-locked loop PLL is clnsed by con-necting the output of the phase detector 6 to the input of the variable-frequency oscillator 1 through a low-pass cor- recting network 8 (we shall omit for the time being the sum-ming circuit 46 whose role in the prepositioning process will be explained later, this circuit playing no functional role in the normal locking phase).

The frequency-reducing chain, comprises for example three frequen-cy conversions, this number being, of course, not limiLative.

These frequency conversions are performed by mixers 20, 20' and 20" (the upstream mixer 20" of the first frequency conversion being in fact the first mixer 2 receiving he basic -16 - reference frequency FR4), each of these mixers being associa-ted at its output with a respective filtering network 30, 30' 30" permitting to eliminate the disturbing components of the image frequency that would be capable of disturbing the stahi-lization of the loop to the desired frequency.

Thus, at the output of each of the filters 30, 30', 30", a single intermediate Frequency, respectively Fl1, Fl2, Fl3, is delivered.

To obtain these intermediate frequencies El1, Fl2, Fl3, two frequencies are brought to beating, according to the prin-.

ciple of heterodyne mixing. The frequency Fl3 of' the first mixe,r 20" is thus obtained through beating between the output frequency ES and a reference frequency FR (generally, but not necessarily, fixed as will be explained at the end of the description); the frequency Fl2 results from beating between the intermediate frequency Fl3 delivered by the mixer 20" and a variable reference frequency FR3.

The lowest intermediate frequency Fl1 is applied to one of the inputs of the phase detector 6 through a switching cir-cuit 40 (that will be omitted for the time being and whose role will be explained later in the prepositioning phase; this circuit does not play any functional role in the loop normal locking phase).

The other input of the phase detector receives a reference frequency FR1 defining the desired pitch of variation p. Very advantageously, this reference frequency FR1 is also a fre-quency programmable among several values so as to have a high number of possible frequencies at the output.

The various reference frequencies FR1, FR2, FR3 are gene- rated by generators 10, 10', 10", all of which are programma-ble generators controlled by a frequency control signal CF1, CE2, CF3 generated by a sequencer circuit 50 from a single control signal CF delivered by the user and corresponding to the frequency to which it is desired to position the variable-.

frequency oscillator..

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By "programmable frequency generator", it is to he under- stood a generator whose frequency can be chosen between a num- ber of discrete values through a logic-type command, For exam-ple a digital word, applied to the circuit.

Very advantageously, the circuits 10, 10' and 10" that generate the programmable reference frequencies are direct-synthesis generators operating from the frequency FQ delivered by the frequency standard 3, so as to allow a coherent (i.e., synchronous) synthesis of the various frequencies. Several possible configurations will be described hereinafter For the-se reference frequency generator circuits.

With the phase-locked loop thus formed, it can be seen that, when balance is reached, the frequencies FR1 and Fl1 are identical.

The balance equation of the system is then written as FS FR4 --FR3 FR2 � FR1.

Preferably, to optimize the balance of the system, the frequencies FIn will be chosen such that Fl IFI -FR I n-i n n i.e., so that all the mixings of the loop be of the subtrac-tive (infradyne) type; in this case, thanks to the low-pass filtering network 30, 30', 30", all the disturbing components of the image frequency (sum frequencies FIn + FR) which might disturb the stabilization of the oop to the desired frequen-cy, are eliminated.

In other words, this configuration corresponds to a suc-cessive reduction, in each frequency converter stage, of the range of variation of the possible frequencies.

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However, it is not absolutely indispensable, for implemen-ting the present invention, that all the mixer stages operate in the infradyne mixing mode; it is possible, for one or more stages (but not for all stages) to chose the SUm signal (su-pradyne mixing) instead of the difference signal (infradyne mixing) through a different filtering network at the output.

However, it is indispensable that, in the whole, (i.e., bet-ween the first mixer 2 and the phase detector 6) there is a reduction of the range of' variation of the frequencies.

However, it should be noted that, at the output of a mi- xer, the sum signal is generally more polluted than the dif- ference signal, which would impair the performance of the who-le system to the same degree.

That is the reason why, in the rest of the description, we shall always consider the case where all the mixings are of the subtractive type and where the bandwidth is conseque-ntly progressively "compressed" in each stage.

The above balance equation (1), corresponding to the exam-ple of Figure 2 where there are three successive frequency conversions, provides eight possible solutions For the output frequency FS.

It is therefore essential to provide an auxiliary means to be able to position the oscillator to the desired frequency among all the possible values corresponding to a single given set of reference frequencies (FR4, FR3, FR2, FR1).

This is achieved, according to a particularly advantageous feature of the present invention, by a prepositioning device (elements 40 through 46) which applies to toe control input of me variable-frequency oscillator 1 a control voltage such that the dc component. delivered by the phase detector 6 is virtually zero, even before the loop begins to converge.

In other words, the prepositioning device will allnw to -19 -position in a quasi-immediate manner and without intervention of the phase-locked loop, the variable-Frequency oscillator to a frequency very close to the desired frequency and in any case included within the lock-in range of the phase-locked loop. It will thus he possible, within a few microseconds, to position the oscillator to a frequency extremely close to the final frequency, so the loop can converge very rapidly to its balance point.

This feedback circuit includes a switch 40 (electronic-type switch) cannected in series with the input of the phase detector 6 that receives the signal Fl1, this switch being controlled by a control signal 5Y3 delivered by the sequencer that ensures the overall synchronization of the whole sys-tem.

When closed, trie switch 40 closes the phase-locked loop PLL which operates then in the conventional manner described above.

On the other hand, when it is open, it fully desactivates this mop. When the loop is thus desactivated, the signal F!1 at the output of the reference frequency generator is applied to a Frequence-phase detector 41 through a Further switch 42, also of the electronic type and such that, when the switch is open, the switch 42 is closed, and conversely. The fre- quence-phase detector 41 receives at its other input the refe-rence frequency FR1 It can thus be seen that when the loop PLL is desactiva-ted, both signals SI and FR1 that were previously applied to the phase detector 6 are now applied to the frequency-phase detector 41, with the loop PLL being inhibited.

The Frequency-phase detector, which is a circuit well known to those skilled in the art, has the particular characteristic of delivering a signal which, by its sign, indicates whether -20 -the difference of the Frequencies applied to its inputs is positive or negative (a simple phase detector does not indica-te this, for it generates a beat which is the same, whatever the sign of the difference of the frequencies). Then, when its operating point is close to balance (i.e., when it oscil-lates between a positive signal and a negative signal at the output), it provides a phase feedback control by generating at its output a pulse whose width depends on the phase diffe-rence between the two input frequencies.

In opposition to its wide frequency lock-in range, the frequency-phase detector has the disadvantage of having a pha- se noise much higher than that of the conventional phase de-tectors. This disadvantage would not allow to achieve the very high phase stability desired for the frequency synthesizer of the present invention if such a frequency-phase detector was simply used instead of the phase detector 6.

In the configuration shown in Figure 2, the (positive or negative) output signal from the frequency-phase detector is applied to the control input of the variable-frequency asciI-lator 1 through a sample-and-hold circuit 43 and a summing circuit 46. The summing circuit receives at another of its inputs, through a further sample-and-hold circuit 44 control-led in conjunction with the first one (by the synchronizing signals S?1 and a voltage produced by a digital-to-analog converter 45 from a frequency command CE5, the whole circuitry being designed so that the voltage delivered by the digital-.

to-analog converter 45 corresponds to the center frequency to which it is desired to position the variable-frequency os-cillator 1. To this center frequency will be added (algehrai-.

cally) the output signal from the frequency-phase detector, which allows an extremely fast positioning to the desid fre-quency.

-21 -More precisely, during the prepositioning step correspon-.

ding to this rapid locking to the desirsd frequency, the swit:h 42 directs the signals Fl1 and FR2 to the frequency-phase de-tector 41, the sample-and-hold circuits 43 and 44 being in the sampling mode and the switch 40 being open, which inhibits the phase-locked loop PLL proper.

In a second step, after storing the voltage generated by the acquisition aid device, the loop PLL Lakes control in or-der to ensure the phase stabilization of the synthesizer. The switch 42 is then open, the sample-and-hold circuits 43 and 44 are in the hold mode and the switch 40 is closed, which activates the loop PLL the output signal from the phase de-tector 6 thus adds up algebraically and as a function of the phase deviation to the prepositioning voltage stored by the sample-and-hold circuits 43 and 44, which ensures the fine phase feedback control.

All of these operations are carried out under the control of the sequencer 50 which delivers in a coordinated manner the various synchronization signals SY. and the frequency con-trol digital words CF1.

It should be noted that during this second step, the error correction voltage generated by the loop is very close to zero thanks to the quality of the prepositioning performed in the first step. The phase acquisition is, therefore, very short, about ten to twenty times the reciprocal of the own angular frequency corresponding to the cutoff frequency of the loop.

It can be seen that there is thus provided a frequency synthesizer extremely performing in all respects (parameters listed at the very beginning of the present description), while using -a single phase-locked loop; -reference frequency generators 10, 10', 10" with relatively -22 -modest characteristics (a level of parasitic lines 20dB Ioqer than the level of the carrier having no noticeable effect on the overall performance of the frequency synthesizer); -a reduced number of frequencies for each of these reference frequency generators (from two to five different frequencies), which allow to use circuits which are both simple and highly performing.

A possible improvement of the present invention, if it is desired to benefit from a "sperfine" pitch, consists in providing, instead of fixed basic reference frequency FR4, a frequency varying by a very fine pitch over a narrow band about this frequency FR4.

Through the combination of the two pitches (normal pitch p and superfine pitch), it will be possible to obtain a frequen-cy variation in a very wide band with this superfine pitch.

It should e noted that in this improved variant, the re-maining circuits are not modified in any way since the fre-.

quency variationF of the basic reference frequency FR4 is identically found in the output frequency FS: therefore, at the output of the mixer 20", and consequently in the remaining Frequency-reducing chain, there will be no frequency variation caused by The intermediate frequencies Fl3, Fl2 and Fl1 thus not being modified in any way, no single parasitic line is genera-ted in the loop. The only additional parasitic lines will be generated at the first mixer 20", hut the intermodulation pro-ducts generated at this stage will have a high order, which allows to guarantee a low level of parasitic lines.

-23 -

I

Description of a preferred embodiment

Figure 3 illustrates a concrete embodiment of a frequency synthesizer covering the range from 2000 MHz to 2500 MHz with a 5-MHz pitch, with a typical frequency switching time (inclu-ding phase acquisition) of about 10 ps.

In this Figure, there are again the same basic elements as those in Figure 2, which are denoted by the same reference numerals.

The numerical values indicated next to the various con- nections between circuits correspond to frequency values ex-pressed in megahertz. Where these values are separated by a diagonal, this indicates the discrete frequency values that can be obtained, and the values between square brackets mdi-cate the frequency ranges being covered.

In this Figure, one has detailed the various reference frequency generators 10, 10', 10" each of which is formed by a comb generator 12, 12', 12" followed by a programmable pass-band filter 13, 13', 13" controlled by a frequency control digital word CF1, CF2, CF3 so as to retain among the frequen-cies produced by the comb generator only a single frequency corresponding to a predetermined harmonic order (the numerical values appearing above the circuits 13, 13', 13" indicate the various harmonic orders that can thus he selected).

It can be noticed that, in any case, the variation between end frequencies is always extremely moderate (at most, twice in the illustrated example), which allows to employ programma-ble filters which are both simple and highly performing.

Each generator 10, 10', 10" is very advantageously imple- mented in the manner described in the French patent N0 88- 08528 entitled "Frequency multiplier with programmable order of multiplication' that can be referred to for more details.

I

This multiplier may possibly be preceded by a fixed-order frequency divider 11, 11' The basic reference frequency FR4 is generated by two fi-xed-order frequency multipliers 4 connected in cascade.

With the various numerical values indicated in Figure 3 (that. will be considered as part of the present description), it can be seen that the generator 10 generates the fine-pitch frequencies FR1 in the 20-40-MHz range through the comb gene-rator 12 receiving the 5-MHz pitch obtained by dividing by ten the 50-MHz crystal-oscillator standard frequency. The corn- mand CF1 applied to the programmable filter 13 allows to se-lect. the order of the desired harmonic (4, 5, 6, 7 or 8).

In the same manner, the generator 10' generates the medium-pitch reference frequencies FR2 in the 100-175-MHz range through a comb generator 12' receiving the 25-MHz pitch obtained by dividing -by two the standard frequency FQ. The command CF2 allows to select the harmonic 4, 5, 6 or 7.

Finally, the generator 10" generates the coarse-pitch fre- quencies FR3 in the 250-400-MHz range through the comb gene-rator 12" directly receiving the 50-MHz signal equal to the standard frequency FQ. The command CF3 allows to select the harmonic 5 or 8.

The choice of the reference frequencies FR1, FR2 and FR3 is made so as to be able to utilize the combinations given by the above-indicated balance equation as applied to this embodiment FS FR4 -4-FR3 + FR2 + FR1 (1) It has been said above that the mixings performed in 20, 20', 20" and 6 are preferably subtractive mixings, according to the expression Fl tFI -FR n-I n n

I

With regard to the mixings performed in 20 and 20', the proposed structure gives for the difference Fl -FR a sign that can be either positive or negative.

That is the reason why there is provided that the switch 42 can interchange the inputs of the frequency-phase detector 41 when the sign of Fl3 -FR3 -FR2 is negative, so as to en-sure the convergence of the prepositioning loop.

This interchange is initiated by an appropriate command CF4 generated by the sequencer 50 as a function of the respec-tive values of the other frequency commands CF1, CF2 and CF3.

To obtain a continuous coverage of the sub-bands of the frequencies Fl1, Fl2 and Fl3, the choice of the frequencies FR2 and FR3 must satisfy the following relationships for N {1,2)-pitch(FRN1) < Fl -FiNmin + pitch(FR1) (2) FR -FR > (2F1) + pitch(FR) (3) N+lrnax N-i-lmin -Nmin 1 It is furthermore advantageous to chose FR > Fl N+lmin Nmax It should be noted in addition that under these conditions it is preferable to apply the reference frequency to the "lo-cal oscillator" terminal of the mixers insofar as the leak of the local oscillator signal can be reduced by filtering (as a matter of fact, mixers are circuits which have two, non symmetrical, "local oscillator" and "radio frequency" input terminals).

The manner in which it is possible to obtain a full cove-rage of the 2000-2500-MHz range is explained by Table I below which gives the values of the various reference frequencies and intermediate frequencies of the successive mixings.

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Table I

FS Fl3 FR3 FR2 Ft1 = FR1 2000 50 250 200 175 25 2005 55 195 20 2010 60 190 150 40 2015 65 185 35 2020 70 180 30 10.2025 75 175 25 2030 80 170 20 2035 85 165 125 40 2040 90 160 35 2045 95 155 30 2050 100 150 25 2055 105 145 20 2060 110 140 100 40 2065 115 135 35 2070 120 130 30 2075 125 125 25 2080 130 120 20 2085 135 115 150 35 2090 i40 110 40 2095 145 105 125 20 2100 150 100 25 2105 155 95 30 2110 160 90 35 2115 165 85 40 220 170 80 100 20 2125 175 75 25 2130 180 70 30 3135 185 65 35 2140 190 60 40 2145 195 400 205 175 30 2150 200 200 25 etc. etc. etc. etc. etc. etc. -27 -

S

It can thus be seen that it is possible to cover without discontinuity the totality of the desired frequency range through an appropriate selection of the control words CF..

Furtherrncire, it an be noted that, as can be ssen from the balance equation (1), the range of frequencies ES which can really be covered extends (again without discontinuity) from 1985 MHz through 2565 MHz.

Utilization of fractional orders of multiplication for the generation of the reference frequencies In the embodiment shown in Figure 3, the reference fre-quency generators were implemented with the simplest structure allowing the direct synthesis, i.e. through generation of har-monics of a reference frequency.

However, taking into account the increase in noise caused by the frequency multiplication process, it may prove more advantageous to use a higher standard frequency FQ, for exam-pie EQ 150 MHz instead of EQ 50 MHz.

On the other hand, if such a higher frequency is chosen, the orders of multiplication will have to be fractional.

A circuit such as that shown in Figure 4 permits to advan-tageously achieve the thus necessary fractional orders.

The reference frequency generator 10 thus includes (in its most complex configuration) a frequency multiplier 14 with a fixed ordèr rn1 receiving at its input the standard frequency FQ, and delivering at. its output a frequency m1xFQ.

This frequency m1xFQ is applied, for one, to a second Ire-quency multiplier 15 with a Fixed order rn2 that consequently delivers a frequency m1xm2FQ and, for another, to a program-mahie frequency divider 16 whose order of division M is chosen by the digital control word CF. so as to deliver a signal at the frequency m1xFQ/N.

-28 -The signals 15 and 16 are applied to the two inputs of a mixer 17 that delivers at its output, through the programma- ble hand-pass filter 13 controlled by the same frequency con-trol word CF1, a reference frequency FR. given by FR. FQ m1 [m2 + 1/NJ.

The schematic diagram of this reference frequency enera- tor with fractional order 10 in Figure 4 corresponds to a ma- ximum, most complex, configuration and it is possible to sim-plify its structure by deleting certain of its elements, in particular either of the multipliers 14 or 15.

Description of a preferred embodiment

of an optimized Frequency synthesizer There will be described, with reference to Figure 5, a circuit allowing to achieve the same performance as t'iat F the circuit shown in Figure 3 (i.e., a full coverage of the 2000-2500-MHz range by 5-MHz steps), but with a choice of the reference frequencies and the intermediate frequencies which allows to greatly simplify the structure of certain of the reference frequency generators.

The reference frequency generator 20 generating the fre-quency FR1 is similar to that in Figure 3, except that the divider is a divider by thirty instead of being a divider by ten, for there is used as standard frequency a frequency FQ of 150 MHz instead of 50 1Hz.

On the other hand, the remaining reference frequency gene-rators 10' and 10" have been simplified a common multiplier by two 14 drives, for one, a divider 16 with only two program- mable orders (2 and 3) to give a medium-pitch reference Ire-quency FR of 100 MHz or 150 MHz.

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I

The multiplier 14 drives, for one, a circuit 10" allowing to generate fractional orders of multiplication and implemen- ted on the principle of the circuit in Figure 4 but in a sim- plified manner by deleting the second multiplier 15. The cor-responding programmable frequency divider 16 allows to select only three orders of division (3, 4 and 6), which gives a coar-se-pitch reference frequency FR3 having only four values 225, 250, 375 and 400 MHz.

As can be seen by examining the Figure, the intermediate frequency Fl2 has two band discontinuities which are in fact related to the modification of the medium pitch corresponding to the reference frequency FR2 which is increased by 25 to MHz. On the other hand, the reference frequency generator 10" generates two frequency doublets FR3 spaced by the coarse pitch of 150 MHz, the internal pitch of each doublet being of 25 MHz (225/250 MHz for one and 375/400 MHz for the other).

However these discontinuities do not prevent a full cove-rage of the 2000-2500-MHz range, as can easily be shown in the same manner as for the embodiment of Figure 3.

As a matter of fact, for any frequency with the 5-Mhz pitch included in this range, there will always be a combination FR1, FR2, FR3 permitting to obtain the desired frequency ES.

Finally, it should be noted that in addition to the sim- plification of the circuits, the frequency synthesizer imple-mented according to Figure 5 has a performance higher than that of that shown in Figure 4 as to the phase noise (which is an extreiiiely important parameter in certain applications) thanks to the reduction of the order of multiplication used to generate the frequencies FR2 and, mainly, the frequencies FR3.

Claims

a -30 -IClaims 1. A frequency synthesizer with a single phase-locked loop, said loop including successively -a variable-frequency oscillator delivering as output a sig-nal with an output frequency which is a function of a control signal applied as input; -a mixer circuit receiving at its first input the signal ge- nerated by said variable-frequency oscillator, and at its se-cond input a basic reference frequency; -a frequency-reducing chain receiving the signal from the output of said mixer circuit; -a phase detector circuit receiving at its first input the signal delivered by said frequency-reducing chain and at its second input at least one predetermined frequency defining the desired pitch of variation of said output frequency; and -a low-pass filtering network receiving as input the output signal from said phase detector circuit, and delivering as output the dontrol voltage for said variable-frequency oscil-lator, wherein -said frequency-reducing chain is essentially without a pro-grammable frequency divider circuit; -said frequencyreducing chain includes, in cascade between said variable-frequency oscillator and said phase detector circuit, a plurality of frequency converter stages, each corn- prising a mixer circuit, said mixer circuit being an hetero-dyne mixer circuit receiving at its first input the signal from the output -31 -Iof the preceding frequency converter stage or, for the first stage, said output frequency of the variable-frequency oscil-lator * receiving at its second input a programmable reference fre- quency or, in the case of the first stage, said basic referen-ce frequency; and * delivering as output, through a low-pass filtering network, the signal applied to the next frequency converter stage or, in the case of the last stage, to the first input of said pha-se detector circuit; -the range of variation of the possible frequencies at the output of said frequency converter stages decreases from the input to the output of said frequency-reducing chain; -the determination of the output frequency of the variable-frequency oscillator results essentially from a combination of the ôornmands of said programmable reference frequencies.
2. A frequency synthesizer according to claim 1, wherein said predetermined frequency defining said pitch of variation, which is applied to said phase detector circuit is also a pro-grammable frequency, so as to have a plurality of different frequencies, selectable and combinable with said programmable reference frequencies.
3. A frequency synthesizer according to claim 1, wherein said basic reference frequency and said programmable reference fre-quencies aswelL as, if such is the case, said predetermined frequency defining the pitch of variation are obtained by means of frequency generator circuits wiht direct synthesis.
4. A frequency synthesizer according to claim 3, wherein the various frequency generator circuits with direct synthesis -32 -I3perate in a coherent manner from a single Fixed-frequency oscillator delivering a common standard frequency.
5. A frequency synthesizer according to claim 3, wherein at least some of said frequency generators with direct synthesis are frequency multiplier circuits.
6. A frequency synthesizer according to claimS, wherein at least certain of said frequency multiplier circuits comprise a comb generator in series with a programmable band-pass filter, a frequency deivider with a fixed order being possibly provi-ded at the input of said comb generator.
7. A frequency synthesizer according to claim 3, wherein at least certain of said frequency generator circuits with direct synthesis are circuits producing fractional orders of multi-p1 i cat i on.
8. A frequency synthesizer according to claim 7, wherein at least c2rtain of said circuits producing Fractional orders of multiplication comprise a programmable frequency divider, a frequency multiplier with a fixed order 5eing possihly pla-ced at the input of said circuit.
9. A frequency synthesizer according to claim 8, wherein at least certain of said circuits producing fractional orders of multiplication comprise a mixer circuit receiving at its first input a standard frequency or a multiple thereof, and recei- ving at its second input a frequency delivered by said pro-grammable frequency divider, the output signal from said mixer circuit being applied to a programmable pass-band Fitter con- trolled simultaneously with said programmable frequency divi-de r.-33 -
10. A frequency synthesizer according to claim 1, wherein all said heterodyne mixer circuits of said frequency converter stages of said frequency-reducing chain operate in the infra-dyne mixing node.
11. A frequency synthesizer according to claim 1, wherein said frequency-reducing chain performs three successive fre-quency conversions.
12. A frequency synthesizer according to claim 1, wherein said basic reference frequency is a programmable frequency delivered itself by a frequency synthesis circuit generating frequencies with a very fine pitch extending over a narrow band, so as to obtain at the output of said variable-frequency oscillator frequencies with this very fine pitch but extending over a wide hand.
13. A frequency synthesizer according to claim 1, wherein said synthesizer includes a circuit for prepositioning said variable-frequency oscillator, said circuit comprising -a combining circuit whose output is connected to the control input of said variable-frequency oscillator; -switching means activated in a loop prepositioning prelimi- nary phase and allowing, for one, to apply to one of the in-puts of said combining circuit the signal delivered by the last frequency converter stage and to the other output of said combining circuit said predetermined frequency defining the pitch of variation and, for another, to inhibit the feedback control of the loop; and -between said combining circuit and the control input of said variable-frequency oscillator, means for storing the level of said control signal reached at the end of said prepositin- -34 -ning phase so that this signal level determines the starting point. for the convergence of the loop when the latter switches back to the feedback control mode alter desactivation of the switching means.
14. A frequency synthesizer according tn claim 13, wherein said combining circuit al said prepositioning circuit is a frequency-phase detector.
15. A frequency synthesizer according to claim 13, wherein said prepositioning circuit of the variable-frequency oscilla-tor comprises in addition -converter means whose output is connected to the control input of said variable-frequency oscillator, said means recei-ving as input a frequency control signal corresponding t: the frequency to which it is desired to position said variable-frequency osci Ilator; -between said converter means and said control input of the variable-frequency oscillator, means for storing said control signal corresponding level so that said signal level determi-nes the starting point of the prepositioning of said loop upon activation of said switching means.
16. A frequency synthesizer with a single phase-locked loop substantially as hereinbefore described with reference to Figures 2-5 of the accompanying drawings.Amendments to the claims have been filed as follows 1. A Frequency synthesizer wiLl a single phaselocked loop, said loop including successively -a variable_frequency oscillator delivering as output a sig-nal wit'i an output Frequency which is a function of a contral signal applied as input; -clEmixer circuit receiving at its first input the signal ge- nerated by said variable-Frequency oscillator, and at its Se-co(td input a basic reference frequency; -a frequency_reducing chain receiving the signal from the one output of said/mixer cir:uit; -a phase detector circuit receiving at its first input the signal delivered by said frequency-reducing chain and at. its second input at least one predetermined Frequency defining the desired pit:h of variation of said output frequency; and -a low-pass filtering network receiving as input the output signal from said phase detector circuit, and delivering as Output the control voltage for said variable_frequency oscit-lator, wherein -said frequency-reducing chain is essentially without a pro-grammab].e frequency divider circuit; -said frequency_reducing chain includes, in cascade between said variable_frequency oscillator and said phase detector circuit, a plurality of frequency converter stages,the first frequency converter stage comprjsjn said one mixer circuit and each of the others comprising a respective other mixer circuit, each of said mixer circuits being an hererodyne mixer circuit: * receiving at. its First input the signal from the out;ut ( f the preceding frequency converter stage or, Fur the first stage, said output frequency of the variable-Frequency oscit-lator; * receiving at its second input a programmable reference Ire- quency or, in the case of the first stage, said basic referen-ce frequency; and * delivering as output, through a low-pass fi1tring network, the signal applied to the next frequency converter stage or, in the case of the last stage, to the first input of said pha..se detector circuit; frequency Converter stages are arranged so that the -the! range of vriatton of the possible frequencies at the eaqh of output of/said frequency converter stages decreases from the input to the output of said frequency_reducing chain; -the determination of the output frequency of the variable-frequency oscillator results essentially from a combination of the commands of said programmable refe.rence frequencies; and wherein said synthesizer includes a circuit for prepositioning said variable-frequency oscillator, said circuit comprising: -a combining circuit whose output is connected to the control input of said variable-frequency oscillator; -switching means activated in a loop prepositioning preliminary -phase and allowing simultaneously, for one, to apply to one of' the inputs of said combining circuit the signal delivered by the last fre-quency converter stage and to the other irt put of said combining circuit said predetermined frequency definjng the pitch of variation and, for another, to inhibit the feedback control of the loop; and -between said combining Circuit and the control input of' said variable_frequency oscillator, means for storing the level of said control signal reached at the end of said prepositioning phase so that this signal level determines the starting point for the conver-gence of the loop when the latter switches back to the feedback control mode after deenergization of' the switching means. (2. A frequency synthesizer according to claim 1, wherein said pre-determined frequency defining said pitch of variation, which is applied to said phase detector circuit is also a programmable fre-quency, so as to have a plurality of different frequencies, selectable and combinable with said programmable reference frequencies.3. A frequency synthesizer according to claim 1, wherein said basic reference frequency and said programmable reference frequencies as well as, if such is the case, said predetermined frequency defining the pitch of variation are obtained by means of frequency generator circuits with direct synthesis.14* A frequency synthesizer according to claim 3, wherein the various frequency generator circuits with direct synthesis 3%, operate in a coherent manner From a single Fixed_frequency oscillator delivering a common standard frequency.5. A frequency synthesizer according to claim 3, wherein at least some of said Frequency generators with direct synthesis are frequency multiplier circuits.6. A frequency synthesizer according to claim 5, wherein at least certain of said frequency multiplier circuits comprise a it) comb generator in series with a programmable band-pass filter, a frequency deivider with a fixed order being Possibly provi-ded at the input of said comb generator.7. A frequency synthesizer according to claim 3, wherein at least certain of said frequency generator circuits with direct synthesis are circuits producing fractional orders oF multi plicat ion.9. A frequency synthesizer according to claim 7, wherein at least cortain of said circuits producing fractional orders of multiplication comprise a programmable frequency divider, a frequency multiplier with a fixed order being possibly pla-ced at the input of said circuit.9. A frequency synthesizer according to claim 8, wherein at least certain of said circuits producing fractional orders of multiplication comprise a mixer circuit receiving at its first input a standard frequency or a multiple tnereof, and recei- ving at its second input a frequency delivered by said pro-grammable frequency divider, the output signal from said Ilixer circuit being applied to a programmable pass-band filter con- trolled simultaneously with said programmable frequency divi-de r. 3c110. P1 frequency synthesizer according U claim 1, aherin all said heterodyne mixer circuits of said Frequency cunverter stages of said frequency-reducing chain pet'ate in the infra-dyne mixing node.11. Frequency synthesizer according to claim 1, wherein said frequency-recjucing chain performs three SUCCCSSiyC Fre-.quency conversions.12. A frequency synthesizer according to claim 1, wherein said basic reference frequency is a programmable frequency delivered itself by a frequency synthesis circuit generating frequencies with a very fine pitch extending over a narrow band, so as to obtain at the output of said variable-frequency oscillaUr frequencies with this very fine piUb but extndin over a wide hand.13. A frequency synthesizer according to claim 1, wherein said combining circuit of said prepositioning circuit is a frequency-phase detector.IC Leo (10.1.11. A frequency synthesizer according to claim 1, wherein said prepositioning cir:uit of the variable_frequency oscilla-tor comprises in addition -converter means whose output is connected to the control input of said variable_frequency oscillator, said means rcei-ving as input a frequency control signal corresponding t: the frequency to which it is desired to position said variable-frequency oscillator; -between said converter means and said control input of the varia51efrequency oscillator, means for storing said control signal corresponding level so that said signal level determi-nes the starting point of the prepositioning of said loop upon activation of said swit:hing means.15. A frequency synthesizer with a single phase-locked loop substantially as hereinbefore described with reference to Figures 2-5 of the accompanying drawings.