GB2218869A - Frequency source using PLL'S - Google Patents

Abstract

An agile frequency source comprising a plurality of substantially identical frequency adaptive divider-less translation phase lock loops (1-4) connected in cascade wherein the connection between the output (Fout) of each loop except the last and the input (Fin) to the next loop includes frequency dividing means (21) and mixing means (22) wherein the frequency divided output of a loop is mixed with a frequency (F1) to form a first translation oscillator input (1TO) input for each loop except the first, and each loop feedback path includes means for mixing down the intermediate frequency with a selected one of a number of different second translation oscillators frequencies (2TO) to the reference frequency (Fref) of the loop for frequency/phase detection. <IMAGE>

Description

AGILE FREQUENCY SOURCE.

This invention relates to an agile frequency source providing a large number of closely spaced frequencies with fast switching between channels.

Future communication systems will continue to make ever greater demands upon synthesised frequency sources in terms of agility and spectral purity whilst maintaining minimum complexity, size and cost.

The application of known techniques of frequency synthesis to meet the requirements of future agile systems results in fundamental conflicts. When considering a conventional divider phase lock loop indirect synthesis technique it is found that the constraints on the highest usable reference frequency compatible with the channel spacing conflict with the need for wide loop bandwidth to achieve fast switching.

Additionally the use of dividers within a phase lock loop introduces a worsening of spectral purity known as multiplicative degradation. Alternatively, configuring architectures using conventional divide, mix and filter direct synthesis techniques results in complex circuits with unacceptable limitations to performance in terms of spurious outputs and bandwidth. These aspects of frequency synthesis techniques are well covered in the published literature, see for example Egan, William F.

'Frequency Synthesis by Phase Lock", New York, John Wiley; Rhode, Ulrich L. 'Digital PLL Frequency Synthesisers, Theory and Design', Prentice-Hall , New Jersey; 1983 also Robins, W.P. 'Phase Noise in Signal Sources, Theory and Applications', Peter Peregrinus, IEE, 1982; and Gorski-Popiel, Jerzy. 'Frequency Synthesis: Techniques and Applications', IEEE Press 1975.

According to the present invention there is provided an agile frequency source comprising a plurality of substantially identical frequency adaptive divider-less translation phase lock loops connected in cascade wherein the connection between the output of each loop except the last and the input to the next loop includes frequency dividing means and mixing means wherein the frequency divided output of a loop is mixed with a fixed frequency to form a first translation oscillator frequency input for each loop except the first, and each loop feedback path includes means for mixing down the intermediate frequency with a selected one of a number of different second translation oscillators frequencies to the reference frequency of the loop for phase/frequency detection.

One example of a frequency adaptive divider-less translation phase lock loop is a phase lock loop the feedback path of which includes mixers whereby selected translation oscillator frequencies are mixed with a proportion of the loop output frequency to form one or more intermediate frequencies the final one of which is then phase/frequency compared with a reference frequency to provide a control signal for a voltage controlled oscillator. The loop output frequency is determined by the combination of the loop reference frequency and the selected translation oscillator frequencies, together with a specific intermediate frequency and voltage controlled oscillator pretune control.

In a preferred embodiment of the invention the source includes a frequency reference generator arranged to produce said reference frequency, and said translation oscillator frequencies wherein said reference frequency is applied to phase/frequency detector means in each loop.

The invention will now be described with reference to the accompanying drawings in which: Figure 1 is a block diagram of a frequency source, Figure 2 illustrates the resolution implementation of the four-loop source of Figure 1, and Figure 3 illustrates the four loop source of Figure 1 in greater detail.

The frequency source as shown in Figures 1 and 3 is based on a cascade architecture of frequency adaptive divider-less phase lock loops 1 - 4. Each loop incorporates a voltage controlled oscillator 10 which provides the loop output. Part of the loop output is utilised in a feedback path where it is fed to a first mixer 11 together with an input frequency, which will be referred to in more detail later. The output of mixer 11 is passed via an intermediate frequency filter 12 to a second mixer 13. A selector switch 14 selects one of a number of second translation oscillator frequencies to be mixed with the intermediate frequency filter output.

Another filter 15 selects the required intermediate frequency from the output of mixer 13 to feed to a phase/frequency detector 16 together with a reference frequency Fret. The output of detector 16 is passed through the loop active filter 17 to form a control signal voltage for the oscillator 10.

All the basic phase lock loops are identical In the case of the fourth loop the input frequency is a fixed frequency F. which is also referred to as the in first translation oscillator frequency 1T04. The selected translation oscillator frequency applied via switch 17 can be referred to as the second translation frequency 2T04. The output of the loop, Fount, in each loop except the first provides the basis for the input F. or first translation frequency lTO to the next in higher loop. Before the output of a loop is applied to the next loop it is first passed through a fixed divide-by-ten divider 21 and a mixer 22 where the divided down frequency is mixed with a further fixed frequency F1. The output of mixer 22 after filtering forms the Fin or lTO for the next higher loop.

in Finally, each loop includes means 18 for pretuning the oscillator 10.

This architecture provides, in the case of a four loop arrangement as shown with a choice of three frequencies 2TO for each loop, ten thousand channels across a selected section of the UHF band. Figure 2 illustrates the successive increase in resolution obtained by cascading the four sections. The 1/10 resolution provided by each of the four loops can be folded into any one of the ten available sub-bands in the next loop.

Referring to a single loop, the expression for the output frequency is: F out = lTO + IF1 (1) and IF1 = A. F ref (2) where A = a varying numerical coefficient of IF1 relative to Fref and F ref = the loop reference frequency.

Therefore: Fount = lTO + AFref (3) From the overall frequency source diagram of Figure 1 the following equation for the final output frequency Fount is derived:

Therefore

In each of the loops the coefficients of IF1 vary independently, hence the designations A1, A2, A3 and A4.

Note that when all the IF1 coefficients are equal at the highest value, the upper and lower output band frequencies can be calculated from:

Also note that the overall bandwidth AF' out = 2 x 1.111 x 4.5 Fref (8) and the smallest frequency increment Fch 2 x Fref 0.5 h- ref (9) The above equations relate to the four section decadic series injection architecture, hence the 1gn-l term in equation (9) where n = the number of decadic loops.

The frequency plan of the synthesiser is arranged so that F. and in d F1 are selected to ensure that the the output frequency band for each of the loops is the same. Thus the loops are a common design as are the divide, mix and filter functions for each section.

This commonality is a significant advantage in terms of design effort economy and manufacturing cost for this synthesis technique.

The frequency references section 30 derives all the fixed, high purity frequencies for the four synthesiser sections from a single high stability 10 MHz reference. The switch matrix block 31 switches 1 of 3 frequencies to each of the loop second translation oscillator (2TO) inputs. The control logic block 32 decodes a parallel BCD input bus to provide pretune and phase sense control to each loop and also controls the switch matrix.

The common loop structure illustrated in Figure 3 employs a wideband VCO phase locked via divider-free frequency translation to a high reference frequency which allows wide loop bandwidth, ensuring fast switching. The divider-free nature of the loop results in the elimination of multiplicative degradation of phase noise within the loop bandwidth, a well-known disadvantage of divider loops. The loop synthesises a 250 MHz output band, having 25 MHz sub-bands with fine frequency resolution injected at the first translation oscillator (lTO) input. A feature of the loop is the pretune circuit 18 which employs an 8-bit D/A converter and achieves +1 MHz accuracy on the required frequency over the temperature range Oo to +300C.

A key element in the loop is the voltage controlled oscillator 10. In order to meet system requirements of high spectral purity in terms of low phase noise and high spurious rejection with fast switching between channels the VCO has stringent requirements in terms of tuning range, sensitivity and linearity together with low phase noise. Such a VCO is disclosed in our co-pending application No. 8807567.6.

Total switching time for the synthesiser is a function of frequency pretune time and phase lock time for each of the loops. The action of the pretune acts in parallel for each loop whereas the phase lock times are additive. However, the phase errors below loop 1 of the synthesiser are progressively reduced by division, with the result that loop 1 tends to dominate the phase lock time. The total switching time can be expressed as: TT Tpretune + T04 +T02 +T01 where Tpretune = frequency pretune time of loops 1 to 4 in parallel.

T04 to 01 = phase lock time for each loop 1 to 4.

The spectral purity in terms of single sideband phase noise is governed by the output loop. The earlier cascaded loops make their contribution by algebraic addition into the output loop via the first translation oscillator input. Indeed, the output spectral purity of the synthesiser is an algebraic summation of each of the output loop injection frequency purities inside the loop bandwidth. Outside the loop bandwidth, the spectral purity tracks that of the VCO.

Claims (4)

CLAIMS.

1. An agile frequency source comprising a plurality of substantially identical frequency adaptive divider-less translation phase lock loops connected in cascade wherein the connection between the output of each loop except the last and the input to the next loop includes frequency dividing means and mixing means wherein the frequency divided output of a loop is mixed with a fixed frequency to form a first translation oscillator frequency input for each loop except the first, and each loop feedback path includes means for mixing down the intermediate frequency with a selected one of a number of different second translation oscillators frequencies to the reference frequency of the loop for phase/frequency detection.

2. An agile frequency source according to Claim 1 including a frequency reference generator arranged to produce said fixed frequency, said local oscillator frequencies and a reference frequency wherein said reference frequency is applied to phase/frequency detector means in each loop.

3. An agile frequency source according to claim 1 or 2 wherein each loop includes a pretune means comprising a digital-to-analogue converter to which a digital representation of the desired frequency is fed, the analogue output of the converter being applied as a control signal for the loop VCO.

4. An agile frequency source subatantially as described with reference to the accompanying drawings.