GB2215540A - Frequency synthesisers - Google Patents

Abstract

A frequency synthesiser for use in a radar or a frequency hopping equipment comprises a frequency adaptive divider- less phase lock loop 100 having elements in its feed-back path for mixing selected local oscillator frequencies 2L0; 40 or 60 with a portion of the loop output. A wide loop band-width for fast switching of frequency channels and high spectral purity of output are obtained. In an input control logic 400, the desired output frequency is preset manually or automatically by an external source and an output signal 1 pre-tunes the loop oscillator to desired output frequency and control signals 3-5 select the required local oscillator frequencies 2L0, 40, 60. A phase control signal 2 is applied to the loop phase/frequency detector. The reference unit 300 includes a single crystal oscillator and provides a number of different fixed frequencies, some of which are applied to a direct synthesiser unit 200 to derive a selectable local oscillator frequency 2L0. The main loop operates over a number of sub-bands in each of which 2L0 is switchable over a fixed range with a frequency spacing. <IMAGE>

Description

FREQUENCY SYNTHESISER This invention relates to a frequency synthesiser exhibiting high spectral purity and fast switching over a number of channels in a high frequency band.

Future radar systems continue to make ever greater demands upon synthesised frequency sources in terms of agility and spectral purity whilst maintaining minimum complexity, size and cost.

For example, a radar frequency source may be required to provide 128 channels over greater than 300 MHz of bandwidth in the 10cm band. High spectral purity in terms of low phase noise and high spurious rejection is required together with fast switching between channels.

The application of known techniques of frequency synthesis to the radar requirements outlined results in fundamental conflicts. When considering a conventional divider phase lock loop indirect synthesis, it is found that the constraints on the highest usable reference frequency compatible with the channel spacing conflict with the need for wide loop bandwidth to achieve fast switching. Additionally, the use of dividers within a phase lock loop introduces a worsening of spectral purity known as multiplicative degradation.

Alternatively, configuring architectures using conventional divide, mix and filter direct synthesis techniques results in complex circuits with unacceptable limitations to performance in terms of spurious outputs and bandwidth. These aspects of frequency synthesis technique are well covered in the literature, see for example Manasseswitsch, Vadium. "Frequency Synthesisers Theory and Design". New York, NY: John Wiley, 1976 and Egan, William F. "Frequency Syntesis by Phase Lock". New York, NY: John Wiley, 1981 amongst many available.

In considering each of the frequency source objectives in turn, it is clear that a novel architecture is required to meet the uncompromising and conflicting requirements.

According to the present invention there is provided a frequency synthesiser arrangement including a frequency adaptive divider-less translation (FAST) phase lock loop having a feedback path and means for producing a plurality of different local oscillator frequencies, the loop feedback path including means for mixing selected local oscillator frequencies with a portion of the loop output.

In one embodiment of the invention the local oscillator frequency producing means includes a frequency reference unit arranged to generate a number of different reference frequencies and a direct frequency synthesis unit arranged to derive from the reference frequencies the plurality of local oscillator frequencies.

In a preferred embodiment of the invention the phase lock loop includes a voltage controlled oscillator and a control logic unit adapted to provide a control signal simulating a control voltage to be applied to the voltage controlled oscillator to pretune the oscillator to a desired output frequency, the control logic unit simultaneously generating control signals to select required local oscillator frequencies to be mixed with the loop output in the loop feedback path.

In yet another embodiment of the invention the control logic unit is adapted to generate additional control signals to select from the reference frequencies a reference frequency to be applied to the loop feedback path mixing means to act as further local oscillator frequency.

The above and other embodiments of the invention will now be described with reference to the accompanying drawings, in which: Figure 1 is a block diagram of the main components of a frequency synthesiser arrangement, Figure 2 illustrates a phase lock loop, Figure 3 illustrates a direct frequency synthesis unit, Figure 4 illustrates a frequency reference unit, Figure 5 illustrates a control logic unit.

In the block diagram shown in Figure 1 a frequency adaptive divider-less translation phase lock loop 100 receives, under control of signals from a control logic unit 400, selected local oscillator frequencies from a direct frequency synthesiser unit 200. The local oscillator frequencies are in turn derived from a reference frueqency unit 300, which can itself provide additional local oscillator frequencies for the loop 1. The following detailed description of the frequency synthesiser arrangement refers to Figures 2-5, which should be considered in the general relationship shown in Figure 1.

The phase lock loop 100 comprises a loop output unit 101, a loop intermediate frequency unit 102 (hereinafter referred to as the loop feedback path) and a loop phase detector and filter unit 103. The loop output unit 101 includes inputs via a summing amplifier 104 the output of which is applied to a voltage controlled oscillator 105. The VCO output is fed via an isolator 106 and a bandpass filter 107 to form the loop output. A signal splitter 108 takes a portion of the isolator output and applies it via an attenuator 109 to a mixer 110. The other input to the mixer 110 is a first local oscillator or reference signal. The input to feedback path 102 is the output of mixer 110 and is fed via bandpass filter 111 and amplifier 112 to a second mixer 113. The other input to mixer 113 is a second local oscillator signal obtained from the direct synthesis unit 200.The output of mixer 113 is passed via low pass filter 114 and amplifier 115 to a third mixer 116. The other input to mixer 116 is a third local oscillator signal selected, by switch 117 under the control of control unit 400, from two different L.O.

frequencies provided by frequency reference unit 300.

The output of mixer 116 is passed via low pass filter 118 to phase frequency detector 119 in the phase detector and filter unit 103 where it is compared with a reference frequency also provided by unit 300. The output of detector 119 is passed through a loop active filter 120 and a low pass notch filter 121 to form one input to the summing amplifier 104. The other output to the summing amplifier is a so-called "pretune", i.e. a signal corresponding to the desired output frequency.

The pretune signal is a digital signal received from the control unit 400 via D/A converter 122 and sample and hold circuit 123.

The direct synthesiser unit 200 receives a number of different fixed frequencies from the frequency reference unit 300 and, utilising mixers 201-208, together with selector switches 209, 210 and one frequency divider 211, provides the required second LO to be fed to mixer 113 in the loop feedback path. Using input frequencies of 30MHz, 60MHz, 80MHz, 100MHz, 320MHz and 640MHz the direct synthesis unit 200 can provide 2nd LO frequencies in the range 450-490MHz, divided into 16 channels at 2.5MHz spacing.

The frequency reference unit 300 (Figure 4) inlcudes a crystal controlled stable 80MHz reference frequency source 301, the output of which provides the fixed frequencies 30-640MHz for the direct synthesis unit 200, using frequency dividers 302-304, frequency multipliers 305-307 and mixers 308-311. Note that mixer 310 receives one input which is a feedback of 420MHz from the direct synthesis unit 200. The 2980MHz output of unit 300 provides the first L.O. applied to mixer 110 in the loop 100, and the 40MHz output provides a reference frequency for the phase frequency detector 119 in the loop 100. The 60MHZ and 100MHz frequencies from unit 300, in addition to being inputs to the synthesiser unit 200, also provide alternative L.O. inputs to mixer 116 in the loop 100 via switch 117.

The control logic unit 400 (Figure 5) generates the required pretune signal and controls the selection of L.O. signals to be applied to the loop. The pretune is input either manually, via thumbwheel switches 401-403, or automatically from an external source via input line 404. In the manual case the switches 401-403 enter a binary coded decimal (BCD) number into a BCD-to-binary conversion from PROM 405. The binary output of PROM 405 is entered into a latch 406. The input via line 404 is already in binary form and is received by the line receiver 407. The choice of internal or external pretune is determined by an internal/external multiplex control on line 408. The external pretune signal in receiver 407 is entered into latch 406, line 404 also carries a strobe signal which is passed from receiver 407 to a monostable 409 together with a trigger signal received on line 410.The monostable triggers the operation of latch 406 and, via line driver 411, the sample and hold circuit 123 (Figure 2). The pretune binary number in latch 406 is fed to the D/A converter 122 in the loop and to a control PROM 412.

PROM 412 generates control signals for the phase frequency detector multiplexer 119 and the selector switch 117 in the loop, and for the selector switches 209, 210 in the synthesiser unit 200 (Figure 3) via line driver circuits 413-416.

The main loop provides eight 40MHZ (nominal) sub-bands across a band of 320MHz. Thus the arrangement shown in Figures 2 - 5 employs divider less translation from the output frequency to the reference frequency and enables the implementation of a frequency plan based on a single stable reference frequency, as can be seen from the Table.

TABLE I

Sub- Output lLO IF1 2LO IF2 3LO IF3 bands 1 3290-3327.5 2980 310-347.5 450-487.5 140 100 40 2 3330-3367.5 " 350-387.5 " 100 60 40 3 3370-3407.5 " 390-427.5 n 60 100 40 4 3410-3447.5 " 430-467.5 n 20 60 40 5 3450-3487.5 " 470-507.5 n 20 60 40 6 3490-3527.5 n 510-547.5 n 60 100 40 7 3530-3567.5 n 550-587.5 n 100 60 i 40 8 3570-3607.5 " 590-627.5 n 140 100 40 This plan ensures coherence of the output frequency as the channels are rapidly switched in automatic mode, e.g. in a frequency hopping equipment.

The phase frequency detector 119 operates at 40MHz, therefore the phase locked VCO steps in 40MHz sub-bands with the frequency synthesiser 200 providing the sixteen 2.5MHz channels in each sub-band. Correct phase locking is ensured by the six control outputs 1-6 from the control logic unit 400.

A specific example will now be described. Consider the case where an output frequency of 3402.5 MHz corresponding to channel 46 is required. Firstly 046 is selected either on the thumbwheel switches 401-403 or the corresponding binary number is received on line 404 and the trigger control on line 410 is activated. The BCD word from the switches is decoded to binary and the binary number is then input to the control PROM 405 via the latch 406. The seven bit control for the pretune D/A converter 122 is derived directly from the latched binary word on line 417. The D/A converter 122 produces a pretune voltage which is held in the sample and hold circuit 123 and applied to the summing amplifier 104 input, which pretunes the voltage controlled oscillator 105 to within a prescribed frequency tolerance of the required output.For simplicity, assume the pretune sets the VCO to 3402.5MHz.

After the isolator 106 the output is split, one signal provides the output via the band filter 107, the other signal is mixed with the lLO in mixer 110 to provide IF1 at 422.5 MHz. Referring to Table 1 it can be seen that these frequencies fall in sub-band 3. The 2LO is set to 482.5 MHz.

TABLE II

7 CHANNEL F OUT SWITCH 209 SWITCH 210 POSITION POSITION 1 450.0 1 4 2 452.5 1 3 3 455.0 1 2 4 457.5 1 1 5 460.0 2 4 6 462.5 2 3 7 465.0 2 2 8 467.5 2 1 9 470.0 3 4 10 472.5 3 3 11 475.0 3 2 12 477.5 3 1 13 480.0 4 4 14 482.5 4 3 15 1 485.0 4 2 16 487.5 4 1 Table II shows that this is channel 14 within the direct synthesiser obtained with switch 209 in position 4 and switch 210 in position 3.These switches are fast response solid state high isolation types which receive their control data from outputs 4 and 5 of the switch control logic 400.

The 422.5MHz IF1 is mixed with the 482.5MHz 2LO to produce an IF2 of 60MHz. The 3LO of 100MHZ is selected via switch 117 which receives control data from output 3 of the switch control logic unit 400. The resulting IF3 of 40MHz is compared with the 40MHz reference frequency in the phase/frequency detector 119 to produce a voltage after the loop filter/amplifier 120 which is used to phase lock the main loop. Correct phase sense is ensured by a multiplex control signal from output 2 of the control unit which controls the inputs to the phase/frequency detector 119.

The output frequency is an algebraic function of the frequencies input to the FAST loop, and in general form is given by: FoUt = lLO + IF1 (1) where IF1 = 2LO + 3LO + F ref (2) the second and third terms simplify, such that: IF1 = 2LO + A.Fref (3) where A = a varying material coefficient of IF2 relative to Fref Also 2LO = f1 + #f0-15 (4) for fl = IFlcf - B.F ref (5) where IFlcf IF1 centre frequency B = a fixed numerical coefficient Fret = FAST loop reference frequency and #f0-15 = N x Fch (6) where N = o to 15 channel designation Fch = channel spacing Therefore 2LO = IFI cf B.Fref + N.Fch (7) and combining (7) and (3) F out = lLO + IFl cf - B. F ref + N.F.ch t ref (8) and note that lLO + IFl cf = Fount centre frequency (9) Also note that

where

= the output frequency band M = the number of A coefficients.

There are two main complementary performance advantages to this architecture. The first is that the FAST loop reference frequency is high, which allows the loop bandwidth to be set wide, thus achieving fast switching.

The second is the elimination of dividers inside the loop together with their degrading effect on spectral purity inside the loop bandwidth.

By these means a frequency synthesiser can be built to exhibit the best performance features of both direct and phase lock loop (indirect) frequency synthesis.

Claims (7)

1. A frequency synthesiser arrangement including a frequency adaptive divider-less translation phase lock loop having a feedback path and means for producing a plurality of different local oscillator frequencies, the loop feedback path including means for mixing selected local oscillator frequencies with a portion of the loop output.

2. A frequency synthesiser arrangement according to Claim 1 wherein the local oscillator frequency producing means includes a frequency reference unit arranged to generate a number of different reference frequencies and a direct frequency synthesis unit arranged to derive from the reference frequencies the plurality of local oscillator frequencies.

3. A frequency synthesiser arrangement according to claim 1 or 2 wherein the phase lock loop includes a voltage controlled oscillator and a control logic unit adapted to provide a control signal simulating a control voltage to be applied to the voltage controlled oscillator to pretune the oscillator to a desired output frequency, the control logic unit simultaneously generating control signals to select required local oscillator frequencies to be mixed with the loop output in the loop feedback path.

4. A frequency synthesiser arrangement according to claims 1, 2 or 3 wherein the control logic unit is adapted to generate additional control signals to select from the reference frequencies a reference frequency to be applied to the loop feedback path mixing means to act as further local oscillator frequency.

5. A frequency synthesiser arrangement substantially as described with reference to the accompanying drawings.

6. A method of synthesising a plurality of frequencies using a dividerless phase lock loop comprising the steps of pretuning a voltage controlled oscillator in the loop, generating a plurality of different local oscillator frequencies, selecting a combination of the local oscillator frequencies separately with a portion of the loop output in a loop feedback path, comparing the feedback path output with a fixed reference frequency and forming from the comparison an oscillator control signal for the voltage controlled oscillator.

7. A method of synthesising a plurality of frequencies substantially as described with reference to the accompanying drawings.