GB2024546A - Frequency Synthesisers - Google Patents
Frequency Synthesisers Download PDFInfo
- Publication number
- GB2024546A GB2024546A GB7915132A GB7915132A GB2024546A GB 2024546 A GB2024546 A GB 2024546A GB 7915132 A GB7915132 A GB 7915132A GB 7915132 A GB7915132 A GB 7915132A GB 2024546 A GB2024546 A GB 2024546A
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- frequency
- output
- division
- input
- multiplication
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- 238000000034 method Methods 0.000 claims description 17
- 230000000694 effects Effects 0.000 claims description 13
- 230000001419 dependent effect Effects 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000003786 synthesis reaction Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
- 239000013078 crystal Substances 0.000 description 2
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/185—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using a mixer in the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
A frequency synthesiser adjustable in fine frequency steps includes a series connection of an adjustable divider 11 and a multiplier e.g. a phase lock loop 12, wherein the division and multiplication factors differ by an offset integer b. The phase locked loop multiplier may include an adjustable divider 14 or in an alternative arrangement the input frequency F is heterodyned with the controlled oscillator VCO 13 frequency and the difference divided by the offset integer b before application to the loop phase detector 15. Any frequency or phase difference at the detector 15 is eliminated by the control signal from the detector which adjusts the VCO frequency. By making b very much smaller than N, the minimum step change in output frequency is approximately F . b/N<2>. The offset integer b may be fixed or adjustable. By a proper selection of the values of b, N, e.g. using a microprocessor or a look-up table stored in a memory, an output frequency approximating any desired value can be obtained. Further fine step adjustment is obtainable by cascading circuits 11, 12 with a similar arrangement. <IMAGE>
Description
SPECIFICATION
Improvements in and Relating to Frequency
Adjusting Methods and Systems
This invention relates to frequency adjusting methods and systems for adjusting the frequency of an electrical signal to approximate to a desired frequency.
Synthesis of a desired frequency can be carried out using a phase-locked loop to generate an output frequency which is a whole multiple of a base frequency fed to the phase comparator of the loop, the multiplication factor being introduced by an integer division operation applied to the output frequency feedback. A change in output frequency to approximate that frequency to a desired value is effected by changing the multiplication factor of the loop.
Clearly the output frequency can only be adjusted in steps equal to the base frequency. Since it is undesirable to have a very low base frequency or a very high multiplication factor, frequency synthesis so effected either has large steps in output frequency or is restricted to low frequency bands.
According to the invention, there is provided an electrical frequency adjusting system, comprising first and second interconnected frequency changing circuits arranged to serially process and input frequency to produce an output frequency differing therefrom, one said circuit serving to effect frequency division by an integer division factor, the other said circuit serving to effect frequency multiplication by an integer multiplication factor differing from said division factor by an offset integer, and factor-adjusting means for adjusting the division and multiplication factors by the same absolute integer value to enable adjustment of the output frequency over a range of frequencies.
According to the invention, there is further provided a frequency synthesiser, comprising frequency generating means for generating a first frequency, frequency dividing means connected to divide the first frequency by an integer division factor to produce an intermediate frequency, frequency multiplication means connected to multiply the intermediate frequency by an integer multplication factor to produce an output frequency, the multiplication and division factors differing by an offset integer, and output frequency adjusting means for adjusting the division and multiplication factors by the same absolute integer value to enable adjustment of output frequency over a range of frequencies.
According to the invention, there is also provided a method of adjusting an output frequency to approximate to a desired frequency, the method comprising the steps of changing an input frequency to an intermediate frequency, changing the intermediate frequency to an output frequency approximating to the said desired frequency, one said frequency changing step being a frequency division by an integer division factor and the other frequency changing step being a frequency multiplication by an integer
multiplication factor differing from the division factor by an offset integer, and adjusting the division and multiplication factors within predetermined limits to values such that the ratio of the offset integer to the division factor is the closest available approximation within those
limits to the difference between the input and desired frequencies expressed as a proportion of the input frequency.
According to the invention, there is further provided an electrical frequency adjusting system, comprising first and second frequency changers connected in series, means feeding an input frequency to the first frequency changer so that the second frequency changer produces an output frequency differing from the input frequency, one said frequency changer serving to effect frequency division by an integer division factor and the other said frequency changer serving to effect frequency multiplication by a multiplication factor differing from the division factor by an offset integer, means for adjusting the division and multiplication factors within predetermined limits, and factor-adjusting means connected to set the division and multiplication factors to values such that the ratio of the offset integer to the division factor is the closest available approximation within said limits to the difference between the input and desired frequencies expressed as a proportion of the input frequency.
According to the invention, there is also provided an electrical frequency adjusting system, for producing a variable output frequency, comprising a variable frequency divider having a division factor N connected to receive an input
frequency, a phase comparator having first and second inputs, means connected the first input of
the phase comparator to receive the output from the first frequency divider, an adjustable oscillator producing the said output frequency, a second frequency divider having a variable division factor (N-b) connected to receive the said output frequency, means feeding the output of the second frequency divider to the second input of the phase comparator, the phase comparator being operative to measure the phase difference between the signals at its two inputs and to produce a control output dependent on the sign and magnitude of the said difference, and means feeding the control output to the adjustable oscillating means to adjust the value of the output frequency so as to reduce the said difference to zero, whereby the output frequency is equal to the input frequency divided by the first division factor and multiplied by the second division factor.
According to the invention, there is yet further provided an electrical frequency adjusting system for producing a variable output frequency, comprising a first frequency divider having a variable division factor N and connected to receive and divide an input frequency, a phase comparator having first and second inputs, means feeding the output of the first frequency divider to the first input of the phase comparator, an adjustable oscillator producing the said output frequency, frequency subtracting means connected to receive the output frequency and the input frequency and to produce a difference frequency dependent on their difference, the second frequency divider having a division factor b and connected to receive and divide the said difference frequency, means feeding the output of the second frequency divider to the second input of the phase comparator, the phase comparator being operative to compare the phases of the signals at its two inputs and to produce a control output dependent on the sign and magnitude of any such phase difference, and means feeding the control output to the adjustable oscillating means to adjust the output frequency in a sense and by an amount so as to reduce the said phase difference to zero, whereby the output frequency is equal to the input frequency divided by the first division factor and multiplied by the difference between the first division factor and the second division factor.
Frequency adjusting methods and systems, each according to the invention, will now be particularly described by way of example only, with reference to the accompanying diagrammatic drawings, in which:
Figure 1 is a block circuit diagram of one of the systems;
Figure 2 is a block diagram representing the system of Fig. 1 in simplified form;
Figure 3 is a block circuit diagram of another of the systems;
Figure 4 is a block circuit diagram of a frequency adjusting system comprising two cascaded systems of the Figure 1 form; and
Figure 5 is a block circuit diagram of a frequency synthesiser.
The frequency adjusting system shown in
Figure 1 comprises a frequency divider 11 which divides an input frequency F by an integer division factor N. The resulting intermediate frequency F/N is then multiplied up by an integer multiplication
factor (N-b) using a frequency multiplier 12
(indicated by dashed lines in Figure 1) formed by
a phase-locked loop comprising a voltage
controlled oscillator 13, a frequency divider 14
(with a division factor of (N-b), a phase
comparator 15, and low pass filter 1 6. The output
Fo of the multiplier 12 is the frequency F/N
multiplied by (N-b), that is, Fo=R(1-b/N) which
is generated at the output of the voltage
controlled oscillator 13. The frequency Fo is the
system output frequency.The divider 11 and the
multiplier 12 can be considered as two frequency
changing circuits which serially process an input
frequency F to give an output frequency Fo=F( 1 - b/N), and can therefore be represented as shown
in Figure 2.
Figure 3 shows a modified form of the system
of Figure 1 in which parts corresponding to parts
in Figure 1 are similarly referenced.
In Figure 3, the frequency F/N is again fed into
one input of the phase comparator 1 5. The second input of the comparator 1 5 receives the output frequency of a frequency divider 1 7 which has a division factor b, thus differing from the frequency divider 14 of Figure 1 which has a
division factor of (N-b). The input of the divider 1 7 is fed from the output of a mixer 18 which receives the first input from the VCO 1 3 and a second input carrying the input frequency F.
A filter (not shown) selects the difference frequency output (F--F,) from the mixer 1 8 for application to the divider 1 7.
In the phase-locked loop of Figure 3, therefore, F--F, F
b N thus, F0 F F b b N thus,
F-bF Fo= N or, Fo=F( 1-b/N) Therefore, the arrangement of Figure 3 operationally corresponds to the arrangement of
Figure 1 and can again be represented by the block diagram of Figure 2.
Referring to Figure 2, the value of the integer b, which may be termed an offset integer, can be either positive or negative, constant or variable, (in the case of the Figure 3 arrangement b is positive when F0 is greater than F so that the mixer output fed to the divider 1 7 is F,-F).
Initially considering b to be kept constant, then as the value of the integer N is varied by the same absolute value in both the division factor of the divider 11 and the multiplication factor of the multiplier 1 2, the output frequency of the system varies in steps S of a magnitude which may be calculated by considering the successive values of the output frequency, (that is, for N=N' and N'+1)
It can be seen that the step changes in output frequency are b/N times the frequency F/N fed to multiplier 12. This is in contrast to one known form of frequency synthesiser which simply multiplies up a base frequency F by an integer factor giving output frequency steps of F. Thus for the same output frequency step size, the frequency fed to the multiplier is N/b larger in the
Figure 2 system which is of advantage.
Considering a specific example, for an output frequency of around 1MHz alterable in 1 Hz step sizes, the previous synthesiser would require a base frequency of 1 Hz and a value of N of 106.
The Figure 2 system can use a multiplier input frequency of 1 kHz and the values of N of 103 with b equal to unity.
For a given value of b, the Figure 2 system has a stepped output frequency range, the span of which is determined by the maximum and minimum values of N. Since the frequency step size S is approximately Fb/N2, the size of step will decrease (and the output frequency increase) as N is increased.
By changing the value of b to a different integer, another stepped frequency range can be obtained by varying the value of N. Making b settable to a number of different values enables a corresponding number of stepped frequency ranges to be obtained. These ranges may overlap with each other depending on the range of values of N available.
Not only will the frequency step size S vary within each stepped frequency range as N changes, but the higher frequency ranges (that is, with lower values of b) will generally have smaller step sizes.
The maximum and minimum values of N and b to give a desired overall output frequency span AF without interruptions between successive stepped frequency ranges can be readily derived as set out below.
1) The overall output frequency span AF is given by
2. For the lowermost output frequency, use N=Nmjn, b=b max. As the output frequency is required to increase, increase N keeping b constant until a value of N is reached satisfying
At this point, change b to bmaX1 and start again from N=Nm,n. When a value of N is then reached satisfying
change 6 to 6,,,--2 and put N back to Nmin Continue in this way untii the full range of output frequencies has been generated.The value of Nmax is then given by
To provide an output frequency approximating to any particular desired frequency in the overall output frquency span of the system, the appropriate value oft and N are calculated to select the stepped frequency range required and the nearest spot frequency in that range to the desired frequency. The division factors of the dividers 11 and 14 are then set to N and (N-t) respectively. The selection of the values of the factors N and (N-t) may be performed in any suitable manner, for example using a microprocess or a look-up table held in memory and arranged to output factor values appropriate for the desired frequency.
The error between the desired and actual output frequency of the synthesiser is at most equal to half the frequency step size S, thus: E--S 2
The maximum error will occur when S is greatest, that is, when t is a maximum and N a minimum:
From an alternative viewpoint, selection of the required value oft and N to give an output frequency approximating to a desired frequency may be considered as a selection of the multiplication and division factors (within the possible ranges of these factors as set by the system design) such that the ratio of the offset b to the division factor N is the closest available approximation to the difference between the input and desired frequencies expressed as a proportion of the input frequency.Thus if Fd is the desired frequency
(The above equation may be derived by setting the output frequency formula given in Figure 1 to approximately equal Fd).
In cases where the range of output frequencies is sufficiently small, the voltage controlled oscillator in the multiplying circuit could advantageously be crystal controlled, thereby giving a spectraily very pure output frequency.
Two or more frequency adjusting systems of the Figure 2 form can be cascaded to give a wider overall frequency span (Figure 4 system) or finer frequency steps.
In the Figure 4 system, two frequency adjusting systems 20 and 21 (indicated by dashed lines) are used, each having the form shown in Fig. 1 (but alternatively each could have the form shown in Fig. 3). The systems 20 and 21 respectively act as fine and coarse frequency adjusting means. The system 20 has integer division and multiplication factors of N and (N-b) respectively and generates an output frequency F( 1-b/N) from an input frequency of F.
The system 21 has integer division, and multiplication factors M and (M-c) and processes the output frequency of the system 20 to produce a final output frequency of F( 1-b/N) (1 -c/M).
The second, "coarse", frequency adjusting system is arranged to have a large step change in output frequency and a wide overall span of output frequencies. The first, "fine", frequency adjusting system 20 is used to provide intermediate frequency steps. Thus, for example, the "coarse" system could have c=1, M=50 to
100 giving a possible 1% change in output frequency with a maximum step size of approximately 4.10-2%. If the "fine" system 20 has b=1, N=1000 to 2000, its range of output frequency adjustment is 5x 10-2%. which is sufficient to cover the largest step change due to the "coarse" system. The largest step change due to the "fine" system 20 is 1 part in 1 Off. Thus the overall system of Figure 4 produces step changes of 1 ppm over a range of 1% of output frequency.
To give very fine step changes in frequency the
Figure 4 system can be modified by setting M equal to N and c equal to (-b). The overall system output frequency is thus:
The step change in output frequency for a change in the value of N for both circuits 20 and 21 is:
2b
N3
For example, for N=l 03, b=1, a fractional change in output frequency of the order of 2 parts in 109 is possible.
The frequency adjusting system of Figure 2 car be used to compensate for an error in a frequency standard due, for example, to temperature provided the temperature dependency of the error is known.
Thus if the output of the frequency standard is
F(1 +x) where xis the undesired error to be compensated for, then after processing by the
Figure 2 system an output frequency is produced of F(1 +x) (1-b/N). This output frequency can be kept constant by choosing N and b to give:
(1 +x) (1-b/N)=constant K
b (1-K)+x N 1+x
The desired frequency adjusting systems can
be advantageously used in frequency synthesisers
having a wide range of output frequencies, as shown in Figure 5. In the synthesiser shown in this Figure, a frequency adjusting system 30 precedes a divider 31 dividing by a factor K and a multiplier circuit 32 multiplying by a factor m, either of which can be variable.Varying the value of the factor m causes large steps in output frequency while the frequency adjusting system 30 can be used to give intermediate steps. Since the output of the frequency adjusting system 30 has only small changes in output frequency, the voltage controlled oscillator 33 of the system 30 could advantageously be crystal contr6lled, giving a spectrally very pure reference frequency to the multiplier circuit 32. For example, if the output frequency required is 30 to 60 MHz in 10 Hz steps accurate to 2 Hz, the input frequency to the multiplier circuit 32 could be made approximately
10 kHz. The multiplication factor m would then in the range 3000 to 6000. The frequency adjusting system 30 would be required to have a range of 333 ppm, and suitable ranges of N and b would be 10000 to 1 5000 and 5 to 2 respectively.
These values would give a maximum output step
size of 0.05 ppm or 3 Hz at 60 MHz; the maximum frequency error would then be 1.5 Hz.
An advantage of varying K and keeping m constant, instead, is that the loop 32 then has a constant gain.
In Figure 5, the frequency adjusting system 30 is shown as being a system of the form shown in
Fig. 1. Instead, of course, it could be a system of the form shown in Fig. 3.
In the systems described above the reference to Figures 1, 2 and 3, the step of frequency division has been illustrated as being carried out before the step of frequency multiplication.
However, it will be appreciated that the order of these steps can be reversed so as to carry out frequency multiplication before frequency division.
The system shown in Figure 3 may be advantageous as compared with the system of
Figure 1 in certain circumstances because the system of Figure 3 involves only a single variable divider (divider 11).
Claims (31)
1. An electrical frequency adjusting system, comprising first and second interconnected frequency changing circuits arranged to serially process an input frequency to produce an output frequency differing therefrom, one said circuit serving to effect frequency division by an integer division factor, the other said circuit serving to effect frequency multiplication by an integer multiplication factor differing from said division factor by an offset integer, and factor-adjusting means for adjusting the division and multiplication factors by the same absolute integer value to enable adjustment of the output frequency over a range of frequencies.
2. A system according to claim 1 , in which the value of the offset integer is alterable by the factor-adjusting means, each offset integer value corresponding to a respective output frequency range within which the output frequency can be varied by adjustment of the division and multiplication factors.
3. A system according to claim 2, in which the said frequency ranges form a continuous span of frequencies over which the output frequency can be varied.
4. A system according to any one of claims 1 to 3, in which the first frequency changing circuit is the circuit effecting frequency division by the division factor.
5. A system according to claim 4, in which the second frequency changing circuit is a phaselocked loop connected to the first frequency changing circuit to effect multiplication of the output of the first frequency changing circuit by the said multiplication factor.
6. A system according to claim 4, in which the phase-locked loop comprises an adjustable oscillator for producing the said output frequency, a phase comparator having two inputs and an output, a frequency divider having a division factor equal to the said integer multiplication factor, means connecting the divider to divide the output frequency of the oscillator and to feed it to one input of the phase comparator, and means connecting the other input of the phase comparator to receive the output of the first frequency changing circuit, the phase comparator being operative to determine the phase difference between the signals received at its two inputs and being connected to adjust the frequency of the adjustable oscillator in response to any said difference and in a direction and by an amount to reduce the difference to zero.
7. A system according to any one of claims 1 to 4, in which the second frequency changing circuit comprises a phase-locked loop including adjustable oscillator means producing the said output frequency, the loop comprising means connected to compare and determine the difference between the output of the first frequency changing circuit and the quotient obtained by dividing the difference between the input frequency and the output frequency by the said offset integer and means to adjust the oscillator means in a direction and by an amount to reduce the difference to zero, whereby to effect multiplication of the output of the first frequency changing circuit by the said multiplication factor.
8. A system according to claim 7, in which the phase-locked loop comprises a frequency subtracting circuit connected to subtract the output frequency from the input frequency to produce a difference frequency, a phase comparator having two inputs and an output, a frequency divider having a division factor equal to the said offset integer, means connecting the divider to receive the difference frequency and to feed it one input of the phase comparator, means connecting the other input of the phase comparator to receive the output of the first frequency changing circuit, the phase comparator being operative in response to any phase difference between the signals at its two inputs to adjust the output frequency of the oscillating means in a direction and by an amount to reduce the said difference to zero.
9. A system according to any preceding claim, cascade-connected to another similar said system.
10. A system according to any one of claims 1 to 8, cascade-connected to another similar said system, and in which the division and multiplication factors of the system are such that one system serves as a coarse frequency adjusting system and the other system serves as a fine frequency adjusting system.
11. A system according to claim 10, in which the values of the division factor and offset integer of one system are arranged to be the same as the corresponding values of the other system, but with the offset integers of opposite sign.
12. A system according to any one of claims 1 to 8, in combination with a frequency standard unit which comprises a frequency source arranged to generate an output frequency having a parameter-dependent frequency error from a nominal frequency; and including means connecting the first frequency changing circuit to receive the source output frequency as the input frequency, and means connecting the factor
adjusting means to be responsive to the said parameters to set the division and multiplication factors in dependence on the parameter to minimise the frequency error between the source output frequency and the nominal frequency.
13. A circuit according to claim 12, in which said parameter is temperature.
14. A frequency synthesiser, comprising frequency generating means for generating a first frequency, frequency dividing means connected to divide the first frequency by an integer division factor to produce an intermediate frequency, frequency multiplication means connected to multiply the intermediate frequency by an integer multiplication factor to produce an output frequency, the multiplication and division factors differing by an offset integer, and output frequency adjusting means for adjusting the division and multiplication factors by the same absolute integer value to enable adjustment of output frequency over a range of frequencies.
1 5. A synthesiser according to claim 14, in which the multiplication means is a phase-locked loop.
16. A method of adjusting an output frequency to approximate to a desired frequency, the method comprising the steps of changing an input frequency to an intermediate frequency, changing the intermediate frequency to an output frequency approximating to the said desired frequency, one said frequency changing a step being a frequency division by an integer division factor and the other frequency changing step being a frequency multiplication by an integer multiplication factor differing from the division factor by an offset integer, and adjusting the division and multiplication factors within predetermined limits to values such that the ratio of the offset integer to the division factor is the closest available approximation within those limits to the difference between the input and desired frequencies expressed as a proportion of the input frequency.
17. A method according to claim 16, in which the first-mentioned and second-mentioned frequency changing steps respectively effect said frequency division and frequency multiplication.
18. A method according to claim 17, in which the offset integer is kept constant.
1 9. An electrical frequency adjusting system, comprising first and second frequency changers connected in series, means feeding an input frequency to the first frequency changer so that the second frequency changer produces an output frequency differing from the input frequency, one said frequency changer serving to effect frequency division by an integer division factor and the other said frequency changer serving to effect frequency multiplication by a multiplication factor differing from the division factor by an offset integer, means for adjusting the division and
multiplication factors within predetermined limits,
and factor-adjusting means connected to set the division and multiplication factors to values such that the ratio of the offset integer to the division factor is the closest available approximation within said limits to the difference between the input and desired frequencies expressed as a proportion of the input frequency.
20. A system according to claim 19, in which the first frequency changer is connected to effect the frequency division and the second frequency changer is arranged to effect the frequency multiplication.
21. A system according to claim 19 or 20, in which the frequency changer effecting multiplication is a phase-locked loop.
22. An electrical frequency adjusting system, for producing a variable output frequency, comprising a variable frequency divider having a division factor N connected to receive an input frequency, a phase comparator having first and second inputs, means connecting the first input of the phase comparator to receive the output from the first frequency divider, an adjustable oscillator producing the said output frequency, a second frequency divider having a variable division factor (N-b) connected to receive the said output frequency, means feeding the output of the second frequency divider to the second input of the phase comparator, the phase comparator being operative to measure the phase difference between the signals at its two inputs and to produce a control output dependent on the sign and magnitude of the said difference, and means feeding the control output to the adjustable oscillating means to adjust the value of the output frequency so as to reduce the said difference to zero, whereby the output frequency is equal to the input frequency divided by the first division factor and multiplied by the second division factor.
23. An electrical frequency adjusting system for producing a variable output frequency, comprising a first frequency divider having a variable division factor N and connected to receive and divide an input frequency, a phase comparator having first and second inputs, means feeding the output of the first frequency divider to the first input of the phase comparator, an adjustable oscillator producing the said output frequency, frequency subtracting means connected to receive the output frequency and the input frequency and to produce a difference frequency dependent on their difference, the said frequency divider having a division factor b and connected to receive and divide the said difference frequency, means feeding the output of the second frequency divider to the second input of the phase comparator, the phase comparator being operative to compare the phases of the signals at its two inputs and to produce a control output dependent on the sign and magnitude of any such phase difference, and means feeding the control output to the adjustable oscillating means to adjust the output frequency in a sense and by an amount so as to reduce the said phase difference to zero, whereby the output frequency is equal to the input frequency derived by the first division factor and multiplied by the difference between the first division factor and the second division factor.
24. An electrical frequency adjusting system substantially as described with reference to Figure 1 of the accompanying drawings.
25. An electrical frequency adjusting system substantially as described with reference to Figure 3 of the accompanying drawings.
26. An electrical frequency adjusting system substantially as described with reference to Figure 4 of the accompanying drawings.
27. A frequency synthesiser, substantially as described with reference to Figure 5 of the accompanying drawings.
28. A method of frequency adjustment, substantially as described with reference to Figure 1 of the accompanying drawings.
29. A method of frequency adjustment, substantially as described with reference to Figure 2 of the accompanying drawings.
30. A method of frequency adjustment, substantially as described with reference to Figure 4 of the accompanying drawings.
31. A method of frequency synthesis substantially as described with reference to Figure 5 of the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB7915132A GB2024546B (en) | 1978-05-26 | 1979-05-01 | Frequency synthesisers |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB2347078 | 1978-05-26 | ||
| GB7915132A GB2024546B (en) | 1978-05-26 | 1979-05-01 | Frequency synthesisers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2024546A true GB2024546A (en) | 1980-01-09 |
| GB2024546B GB2024546B (en) | 1982-12-22 |
Family
ID=26256535
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB7915132A Expired GB2024546B (en) | 1978-05-26 | 1979-05-01 | Frequency synthesisers |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2024546B (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0141452A2 (en) * | 1983-09-28 | 1985-05-15 | Philips Patentverwaltung GmbH | Circuit arrangement for a receiver with two phase-locked loops |
| EP0244571A2 (en) * | 1986-05-02 | 1987-11-11 | Hewlett-Packard Company | Low phase noise RF synthesizer |
| DE3801418A1 (en) * | 1988-01-20 | 1989-08-03 | Telefunken Electronic Gmbh | Frequency synthesis circuit |
| GB2245441A (en) * | 1990-06-13 | 1992-01-02 | Motorola Israel Ltd | Fine-tune frequency adjuster |
| EP0500516A2 (en) * | 1991-02-20 | 1992-08-26 | Telefonaktiebolaget L M Ericsson | Broad band frequency synthesizer for quick frequency retuning |
| FR2717643A1 (en) * | 1994-03-15 | 1995-09-22 | Samsung Electronics Co Ltd | Transceiver signal processor for digital wireless telecommunications device. |
| EP0897616A1 (en) * | 1996-04-22 | 1999-02-24 | Motorola, Inc. | Frequency synthesizer with temperature compensation and frequency multiplication and method of providing the same |
| EP1100192A2 (en) * | 1999-09-28 | 2001-05-16 | Infineon Technologies AG | Oscillator for multiband receiver |
| EP1473700A2 (en) * | 2003-05-01 | 2004-11-03 | Genesis Microchip, Inc. | Enumeration method for the link clock rate and the pixel/audio clock rate |
| CN111120121A (en) * | 2019-12-25 | 2020-05-08 | 潍柴动力股份有限公司 | Frequency drive control method, frequency drive control device, engine controller and storage medium |
-
1979
- 1979-05-01 GB GB7915132A patent/GB2024546B/en not_active Expired
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0141452A2 (en) * | 1983-09-28 | 1985-05-15 | Philips Patentverwaltung GmbH | Circuit arrangement for a receiver with two phase-locked loops |
| EP0141452A3 (en) * | 1983-09-28 | 1987-02-04 | Philips Patentverwaltung Gmbh | Circuit arrangement for a receiver with two phase-locked loops |
| EP0244571A2 (en) * | 1986-05-02 | 1987-11-11 | Hewlett-Packard Company | Low phase noise RF synthesizer |
| EP0244571A3 (en) * | 1986-05-02 | 1989-03-22 | Hewlett-Packard Company | Low phase noise rf synthesizer |
| DE3801418A1 (en) * | 1988-01-20 | 1989-08-03 | Telefunken Electronic Gmbh | Frequency synthesis circuit |
| GB2245441B (en) * | 1990-06-13 | 1994-04-06 | Motorola Israel Ltd | Fine-tune frequency adjustor |
| GB2245441A (en) * | 1990-06-13 | 1992-01-02 | Motorola Israel Ltd | Fine-tune frequency adjuster |
| EP0500516A2 (en) * | 1991-02-20 | 1992-08-26 | Telefonaktiebolaget L M Ericsson | Broad band frequency synthesizer for quick frequency retuning |
| EP0500516A3 (en) * | 1991-02-20 | 1993-04-21 | Telefonaktiebolaget L M Ericsson | Broad band frequency synthesizer for quick frequency retuning |
| FR2717643A1 (en) * | 1994-03-15 | 1995-09-22 | Samsung Electronics Co Ltd | Transceiver signal processor for digital wireless telecommunications device. |
| EP0897616A1 (en) * | 1996-04-22 | 1999-02-24 | Motorola, Inc. | Frequency synthesizer with temperature compensation and frequency multiplication and method of providing the same |
| EP0897616B1 (en) * | 1996-04-22 | 2014-04-23 | Wi-LAN Inc. | Frequency synthesizer with temperature compensation and frequency multiplication and method of providing the same |
| EP1100192A3 (en) * | 1999-09-28 | 2002-07-17 | Infineon Technologies AG | Oscillator for multiband receiver |
| US6600912B1 (en) | 1999-09-28 | 2003-07-29 | Infineon Technologies Ag | Receiver for various frequency bands |
| EP1100192A2 (en) * | 1999-09-28 | 2001-05-16 | Infineon Technologies AG | Oscillator for multiband receiver |
| EP1473700A2 (en) * | 2003-05-01 | 2004-11-03 | Genesis Microchip, Inc. | Enumeration method for the link clock rate and the pixel/audio clock rate |
| EP1473700A3 (en) * | 2003-05-01 | 2008-10-22 | Genesis Microchip, Inc. | Enumeration method for the link clock rate and the pixel/audio clock rate |
| CN111120121A (en) * | 2019-12-25 | 2020-05-08 | 潍柴动力股份有限公司 | Frequency drive control method, frequency drive control device, engine controller and storage medium |
| CN111120121B (en) * | 2019-12-25 | 2022-04-05 | 潍柴动力股份有限公司 | Frequency drive control method, frequency drive control device, engine controller and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2024546B (en) | 1982-12-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |