DE3801418A1 - Frequency synthesis circuit - Google Patents

Abstract

The invention relates to a frequency synthesis circuit with phase locked loop (PLL) and a reference divider for generating the reference frequency and controlled frequency divider with variable divider factor. According to the invention, the divider factor at the reference divider is also changed for setting the various output frequencies, as a result of which the reference frequency is no longer constant. In this arrangement, all frequencies, which are all integral multiples of a given channel allocation frequency, can be generated gaplessly by using permissible frequency tolerances.

Description

The invention relates to a frequency synthesis circuit with a phase locked loop (PLL) , which contains a controlled frequency divider with a variable divider factor (N) , and a reference divider, which divides the reference frequency supplied to it with the divider factor (M) down to the comparison frequency and feeds this comparison frequency to a phase detector .

Such circuits are used to process the necessary frequencies in radio devices, for example in CB radio devices and "cordless" telephones, and in television and radio receivers. In this case, further different frequencies are derived from a single reference frequency of high stability, which is generated, for example, by a quartz crystal, which in turn are also very precise and constant. This allows the construction of frequency grids with a constant channel spacing, as is generally required for radio systems. If, for example, such a frequency grid is made up of n radio channels with a channel spacing frequency f _K , the output frequency f _{A is} calculated using the following formula:

f _A = f ₀ + μ f _K , (1)

μ ε {0 ,. . ., n- 1}

where f ₀ denotes the frequency of the zeroth channel and μ the channel number.

The frequency synthesis of such a circuit takes up the principle of the phase-locked control loop (PLL = phase locked loop) back in the literature has been described many times. This is exemplified on the book "Theory and Application of Phase Locked Loops" by Best, R., published by AT Verlag Aarau, Stuttgart 1981, in particular Chapter 1, pages 11-13, and Chapter 7.7, pages 85-89.

Fig. 1 shows a known frequency synthesis circuit, as used for producing a frequency raster with constant channel spacing. The reference frequency f _ref generated by a crystal oscillator OSZ is fed to a reference divider with a fixed division factor M , which divides the reference frequency f _{ref down} to the comparison frequency f ₁. A phase detector PD , to which the reference frequency f ₁ is supplied, forms with a control filter LF (LF = Loop Filter), a voltage-controlled oscillator VCO (VCO = Voltage Controlled Oscillator), a prescaler (prescaler) with the divider factor V and a frequency divider with the Reduction factor N is a control loop. The output frequency f _{A is} tapped at the output 2 of the voltage-controlled oscillator VCO with the value NVf ₁. Since the number of components for a given device should be as small as possible, as many functions as possible are combined in a highly integrated circuit. In addition, efforts are also being made to use CMOS technology as VLSI technology for frequency synthesis, since it is characterized by low power loss. The reference divider, the phase detector PD and the frequency divider are therefore generally combined to form a highly integrated circuit 1 in CMOS technology, this being possible at very high output frequencies NVf ₁ only if these output frequencies are divided down into frequency ranges by the prescaler (prescaler) that can be processed directly by CMOS circuits.

The circuit according to FIG. 1 therefore generates 2 output signals at the output, the frequencies f _{A of which are} an arbitrary integer multiple N of the frequency Vf ₁:

f _A = N · V · f ₁. (2)

To generate these output frequencies f _A , the frequency divider is designed with an adjustable divider factor N. With an overall high output frequency of, for example, 900 MHz and a small channel grid frequency of, for example, 25 kHz, the comparison frequency f ₁ by the prescaler by its sub-ratio V is smaller than the channel grid frequency f _K , because because of the equations (1) and (2) applies

f _K = V · f ₁. (3)

This enables the control loop to snap into place quickly not possible after changing channels.

The invention is therefore based on the object of specifying a frequency synthesis circuit with which all integer multiples of the comparison frequency f 1 can be generated and which at the same time allows the desired output frequencies to be set quickly.

This object is achieved according to the invention in a frequency synthesis circuit of the type mentioned at the outset in that the reference divider can be controlled to set a variable divider factor M in order to generate a variable comparison frequency.

A frequency synthesis circuit is known from the above-mentioned literature on page 86, Figure 79 d, with which it is possible to generate integer multiples of the comparison frequency f 1 without gaps. Such a circuit is shown in FIG. 2, which uses a so-called "2-modulus prescaler" instead of the fixed prescaler in FIG. 1, the reduction factor of which can take two values, V or V + 1. An external control signal determines which divider factor is valid. In addition, this circuit has two coupled frequency dividers with the constant divider factor N ₁ or N ₂. At the output 2 , the output frequency f _A can be tapped with the value (N ₁ V + N ₂ ) f ₁. The reference divider, the two frequency dividers with the divider factors N ₁ and N ₂, the phase detector PD and the AND gate 3 are combined on a highly integrated circuit 1 . The possibility of being able to generate all integer multiples of the comparison frequency f ₁ at the output has to be bought with this circuit due to an increased circuit complexity.

The circuit according to the invention, on the other hand, has essentially the same circuit parts as that of FIG. 1, but the divider factor M of the reference divider is not constant, but is adjustable. To set the different output frequencies, the divider factor M is also changed on the reference divider, whereby the comparison frequency f ₁ is no longer constant. According to a first embodiment of the invention, the permissible frequency tolerance Δ f at the output frequency is used to generate a predeterminable output frequency grid. The output frequencies f _A then no longer follow the strict law according to equation (1), but are calculated accordingly

where f _{ref is} the reference frequency of the crystal oscillator OSZ and μ represents the number of channels. The divisor factors N and M therefore depend on the number of channels μ and are therefore no longer constant. This non-linear relationship can be linearized in certain areas with high output frequencies, limited number of channels and low channel grid frequency, whereby a skilful choice of N ( m ) and M ( μ ) results in a minimal error in the output frequencies.

According to a further embodiment of the invention, the output frequencies f _{A are} in the 900 MHz range. The tolerance spectrum Δ f preferably applies to ± 2.5 kHz.

In a preferred embodiment of the invention, the divisor factor N ( μ ) or M ( μ ) assumes the value 3805 + μ or 6886 + 2 μ , where μ is the number of channels.

The frequency synthesis circuit according to the invention has a significantly lower circuit complexity compared to the circuit according to the prior art according to FIG. 2, wherein at the same time a high comparison frequency f 1 can be realized in order to ensure a rapid locking into a desired output frequency.

The invention is based on an embodiment are explained in more detail. Here shows

Fig. 3 shows a frequency synthesis circuit according to the invention, and

Fig. 4 the frequency difference Δ f between the frequency of the inventive synthesis circuit of Fig. 1 produced output frequencies in the 900 MHz range and the target frequencies μ as a function of the channel number.

The inventive circuit according to Fig. 3 comprises a reference divider, the division factor M can be adjusted. Otherwise, the construction of this circuit corresponds to that of FIG. 1. The adjustable reference divider, the phase detector PD and the frequency divider with adjustable divider N are combined on an integrated circuit 1 using CMOS technology. The phase detector PD forms a phase-locked loop together with the control filter LF , the voltage-controlled oscillator VCO , the prescaler and the frequency divider. At output 2 of the oscillator VCO , the output frequency f _A with the value

decreased. Here, f _ref means the reference frequency generated by the crystal oscillator OSZ , V the division factor of the prescaler and M ( μ ) or N ( μ ) the division factors of the reference divider or frequency divider, which depend on the number of channels μ . The reference signal of frequency f _ref is fed to the adjustable reference divider _ref this reference frequency f with the respectively set divider M (μ) to the comparison frequency f ₁ divides down, which is then fed to the phase detector PD.

The frequency synthesis circuit according to the invention can advantageous for the generation of the channel frequencies in the 900 MHz range, for example for a cordless phone, be used. Here is a channel grid of 40 Channels with a channel spacing of 25 kHz, the channel frequencies in the at the end of this description listed table are listed. The allowable Tolerance for the channel frequencies is ± 2.5 kHz.

To generate this channel grid, the divider factor of the reference divider and the frequency divider is set as a function of the number of channels μ . The following applies to the divisor factor M ( μ ) or N ( μ ) of the reference divider or frequency divider:

μ - < N ( μ ) = 3805 + μ , or

μ - < M ( μ ) = 6886 + 2 μ . (4)

This means that the division factors M ( μ ) or N ( μ ) of the reference divider or the frequency divider increase by a factor of 1 or by a factor of 2 if the channel number μ is increased by a factor of 1.

The following table shows the channel frequencies generated with the circuit according to the invention according to FIG. 3 for the 40 channels. In this case, is in the first column of the channel number m, in the second column, the desired frequency f _{A, Soll,} in the third column of the comparison frequency f ₁, in the fourth column of the output frequency generated f _A, and the last column of the frequency difference Δ f the target frequency f _{A, target} from the output frequency f _{A, actual} :

Δ f = f _{A, target} - f _{A, actual} . (5)

It can be seen immediately from the last column of this table that the frequency difference for all 40 channels is smaller than the permissible tolerance. The Fig. 4 again shows the frequency difference Δ f μ as a function of the channel number. This also shows that the frequency differences are within the tolerance range of ± 2.5 kHz.

Claims (5)

1. Frequency synthesis circuit with phase locked loop (PLL) , which contains a controlled frequency divider with a variable divider factor (N) , and a reference divider that divides the reference frequency (f _ref ) supplied to it with the divider factor (M) down to the comparison frequency (f ₁ ) and this comparison frequency (f ₁ ) feeds a phase detector (PD) , characterized in that in order to generate a variable comparison frequency (f ₁ ) the reference divider can be controlled for setting a variable divider factor (M) . 2. Frequency synthesis circuit according to claim 1, characterized in that the following applies to the output frequencies (f _A ): where V is the divider factor of the in-phase-locked loop prescaler and m is the channel number of a frequency channel spacing, and in that the division factors N (μ) and M (μ) as a function of the channel number (μ) are chosen so that the output frequencies (f _A) of individual channels are within a predetermined tolerance range ( Δ f) . 3. Frequency synthesis circuit according to claim 2, characterized in that the output frequencies (f _A ) of the frequency channel grid are in the 900 MHz range. 4. Frequency synthesis circuit according to claim 2 and 3, characterized in that for the tolerance spectrum ( Δ f) applies: Δ f ± 2.5 kHz. 5. Frequency synthesis circuit according to claim 2 and 3, characterized in that for the division factors N ( μ ) and M ( μ ) applies: μ - < N ( μ ) = 3805 + μ , and
μ - < M ( μ ) = 6886 + 2 μ .