GB2387012A

GB2387012A - Liquid crystal display driving method

Info

Publication number: GB2387012A
Application number: GB0313948A
Authority: GB
Inventors: Chang Gon Kim; Jong Sang Back
Original assignee: LG Philips LCD Co Ltd
Current assignee: LG Display Co Ltd
Priority date: 2000-12-15
Filing date: 2001-07-18
Publication date: 2003-10-01
Anticipated expiration: 2021-07-18
Also published as: GB2387012B; GB2387013A; GB0313948D0; GB2387013B; GB0313951D0

Abstract

A method used in driving a liquid crystal display is disclosed. It is determined if an input signal, such as a vertical synchronisation signal or a data enable signal, has an error. A desired signal is outputted depending on whether or not the input signal period is within the range. Such output signals could include a colour signal, a black signal, a message signal, a time varying signal or a signal based on a previous image signal. Also disclosed is a system for determining the presence or absence of a signal and also a system for determining if the period of an input signal is within a range of periods. An advantage is that damage to a display can be avoided.

Description

238701 2

LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF

This invention relates to a liquid crystal display, and more particularly to a liquid crystal display and a 10 driving method thereof that are adaptive for detecting a presence of an input signal applied to the liquid crystal display. Generally, a liquid crystal display (LCD) has been employed a notebook PC, an office automation equipment and an audio/video equipment, etc. owing to advantages of a small dimension, a thin thickness--*- a Chat FeMer 20 consumption. In particular, an active matrix liquid crystal display using thin film transistors (TFT's) as switching devices is suitable for displaying a dynamic image. 25 Fig. l is a block diagram showing a configuration of the conventional LCD. In Fig. l, an interface part l0 receives a data (RGB data) and control signals (e.g., an input clock, a horizontal synchronizing signal, a vertical synchronizing signal and a data enable signal) inputted 30 from a driving system such as a personal computer (not shown) to apply them to a timing controller 12. A low voltage differential signal (LVDS) interface and a transistor transistor logic (TTL) interface are largely -- 1

used for a data and control signal transmission to the driving system. Such interfaces may be integrated into a single chip along with the timing controller 12 by collecting each function of them.

The timing controller 12 takes advantages of a control signal inputted via the interface 10 to produce control signals for driving a data driver 18 consisting of a plurality of drive IC's (not shown) and a gate driver 20 lo consisting of a plurality of gate drive IC's (not shown).

Also, the timing controller 12 transfers a data inputted from the interface 10 to the data driver 18. A reference voltage generator 16 generates reference voltages of a digital to analog converter (DAC) used in the data driver 15 18, which are established by a producer on a basis of a transmissivity to voltage characteristic of the panel. The data driver 18 selects reference voltages of an input data in response to control signals from the timing controller 12 and applies the selected reference voltage to the 20 liquid crystal display panel 2, thereby controlling a rotation angle of the liquid crystal. The gate driver 20 makes an on/off control of the thin film transistors (TFT's) arranged on the liquid crystal panel 22 in response to the control signals inputted from the timing 25 controller 12. Also, the gate driver 20 allows the analog image signals from the data driver 18 to be applied to each pixel connected to each TFT. A power voltage generator 14 supplies an operation voltage to each element, and generates a common electrode voltage and applies it to 30 the liquid crystal panel 22.

Fig. 2 is a schematic block diagram showing a configuration of the timing controller in Fig. 1. In Fig.

2, the timing controller 12 includes a control signal generator 22 and a data signal generator 24. The timing controller 12 receives a horizontal synchronizing signal, a vertical synchronizing signal, a data enable signal, a 5 clock and a data (R,G,B). The vertical synchronizing signal represents a time required for displaying one frame field. The horizontal synchronizing signal represents a

time required for displaying one line of the field. Thus,

the horizontal synchronizing signal includes pulses 10 corresponding to the number of pixels included in one line.

The data enable signal represents a time supplying the pixel with a data.

The data signal generator 24 rearranges a data so that 15 desired bits of data (R,G,B) inputted from the interface 10 can be supplied to the data driver 18. The control signal generator 22 receives the horizontal synchronizing signal, the vertical synchronizing signal, the data enable signal and the clock signal to generate various control 20 signals and apply them to the data driver 18 and the gate driver 20. The control signals required for the data driver 18 and the gate driver 20 will be described below.

Herein, the control signals used commonly other than the control signals required specially will be described.

The control signals required for the data driver 18 include source sampling clock (SSC), source output enable (SOE), source start pulse (SSP) and liquid crystal polarity reverse (POL) signals, etc. The SSC signal is 30 used as a sampling clock for latching a data in the data driver 18, and which determines a drive frequency of the data drive IC. The SOE signal transfer a data latched by the SSC signal to the liquid crystal panel. The SSP signal

is a signal notifying a latch or sampling initiation of the data during one horizontal synchronous period. The POL signal is a signal notifying the positive or negative polarity of the liquid crystal for the purpose of making 5 an inversion driving of the liquid crystal.

The control signals required for the gate driver 20 include gate shift clock (GSC), gate output enable (GOE) and gate start pulse (GSP) signals, etc. The GSC signal is 10 a signal determining a time when a gate of the TFT is turned on or off. The GOE signal is a signal controlling an output of the gate driver 20. The GSP signal is a signal notifying a first drive line of the field in one

vertical synchronizing signal.

The control signals inputted to the data driver 18 and the gate driver 20 as mentioned above are generated by the control signals inputted from the interface lo. Thus, if no control signal is input from the interface lo, then the 20 timing controller 12 fails to generate a control signal.

In other words, if any control signals are not inputted from the interface lo in a power-on state, then the liquid crystal panel 2 does not display a picture. If a state in which the liquid crystal panel 2 does not display a 25 picture upon power-on is sustained, then the liquid crystal is deteriorated to leave traces. Such deteriorated traces are viewed even when the LCD make a normal display to cause a trouble of the LCD.

30 In order to prevent the deterioration of the liquid crystal, it is necessary that the timing controller is controlled in accordance with a presence or absence of input signal. For the controlling of the timing controller,

tle presence of tle input signal must be deter mined accurately.

Accordingly, it is an object of tle present invention to provide a liquid crystal display and a driving method thereof that ale adaptive for detecting a :>resece arid a frequency ravage of an input signal applied to flee liquid crystal display.

In order to achieve sliest and other objects of tle invention, according to o',e aspect of tle present invention there is provided a method of driving a display comprising receiving an input signal 1laving a first frequency; generating a signal will, a desired frequency front the input signal; detecting wletler the signal Title a desired frequency leas alternating states; counting a nunbet of no-alternating states if tle signal with a desired frequency does riot leave alternating states; and determining wletler the number is greater tea ogle.

According to a firtler aspect of the present invention there is provided a beetled of driving a display comprising receiving aft input signal leaving a first period corresponding to a nunlaer of lilies in the display; determining wletler the first period is within a first reference period range, flee first reference period range leaving a maxitnun period and a nininrm period; arid outputting a signal of a first state if the first period is less thank the reference period range minimum period or greater than tle reference period range maximum period.

According to a further aspect of the present invention there is provided a method of driving a display comprising receiving an input signal having a first period corresponding to a number of lines in the display; determining whether the first period is less than a first reference period and greater than a second reference period, the first reference period having a maximum period or a minimum period; and outputting a signal of a first state if the first period is less than the first reference period and greater than the second reference period.

According to a further aspect of the present invention there is provided a method of driving a display comprising receiving a vertical synchronization signal; generating a signal with a desired frequency from the vertical synchronization signal' the signal with a desired frequency indicating whether the vertical synchronization signal has an error; and outputting a desired video signal to the display when the error is detected.

According to a further aspect of the present invention there is provided a method of driving a display comprising receiving a data enable signal; generating a signal with a desired frequency from the data enable signal, the signal with a desired frequency indicating whether the data enable signal has an error; and outputting a desired video signal to the display when the error is detected.

According to a further aspect of the present invention there is provided a liquid crystal display device including a timing controller provided with a signal presence determiner for detecting an application of an input signal

from an interface, wherein said signal presence determiner comprises; an oscillator for generating a reference clock having the same frequency as a horizontal synchronizing signal and a pre-synchronizing signal having the same frequency as a vertical synchronizing signal; a period detector for comparing a data enable signal from the exterior thereof with the reference clock to output a period of the input signal with the aid of a detection reference signal and the pre-synchronizing signal; a period comparator for comparing a period range between a desired maximum value and a desired minimum value of the input signal; and signal presence/absence comparing means for determining a presence/absence of the input signal in response to a number of pulses of the input signal detected within a period range between the maximum value and the minimum value during the application of the detection reference signal.

Herein, said period range between the maximum value and the minimum value of the period comparator can be controlled by a user. Also, said pulse number of the signal presence/absence comparing means can be controlled by a user.

According to a further aspect of the present invention there is provided a method driving a liquid crystal display device including a timing controller provided with a signal presence determiner for detecting an application of an input signal from an interface, said method comprising the steps of generating a reference clock having the same frequency as a horizontal synchronizing signal and a pre-synchronizing signal having the same frequency as a vertical synchronizing signal; comparing a data enable signal

from the exterior with the reference clock to output a period of the input signal with the aid of a detection reference signal and the presynclronizing signal; comparing a period range between a desired maximum value and a desired minimum value of the input signal; and determining a presence/absence of the input signal in response to a number of pulses of the input signal detected within a period range between the maximum value and the minimum value during the application of the detection reference signal.

For a better understanding of the present invention' embodiments will now be described by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a block diagram showing a configuration of a prior liquid crystal display; Fig. 2 is a schematic block diagram showing a configuration of the timing controller in Fig. 1; Fig. 3 is a schematic block diagram showing a

configuration of a timing controller according to an embodiment of the present invention; Fig. 4 is a flow chart representing an operation of an embodiment of the signal presence determiner shown in Fig. 5 3; - Fig. '5 is a waveform diagram representing a process of generating a judgment signal from the signal presence determiner shown in Fig. 3; Fig. 6 is a block diagram of a multiplexer provided at the 10 timing controller shown in Fig. 3; Fig. 7 is a flow chart representing an operation of another embodiment of the signal presence determiner shown in Fig. 3i Fig. 8 is a timing diagram representing a process of 15 generating a judgment signal from the signal presence determiner shown in Fig. 7i Fig. 9 is a block diagram of the period detector shown in Fig. 7; Fig. 10 is a block diagram of the period comparator shown 20 in Fig. 7; and Fig. 11 is a block diagram of the signal presence/absence comparator shown in Fig. 7.

Referring to Fig. 3, there is shown a timing controller according to an embodiment of the present invention. The timing controller 34 includes a control signal generator 30 for receiving timing synchronizing signals of a 30 horizontal synchronizing signal, a vertical synchronizing signal, a data enable signal and a clock pulse to generate control signals applied to a data driver 18 and a gate driver 20, a data signal generator 32 for receiving a data

(R. G. B) inputted from the interface 10 and then aligning them to apply the same to the data driver 18, and a signal presence determiner 28 for detecting an application of various control signals inputted from the interface 10.

S The timing controller further includes an oscillator 26 for applying a desired frequency of reference signal to the signal presence determiner 28.

The control signal generator 30 receives a horizontal 10 synchronizing signal, a vertical synchronizing signal, a data enable signal and a clock signal to generate various control signals for driving the liquid crystal display panel, and applies the generated control signals to the data driver 18 and the gate driver 20. The vertical 15 synchronizing signal represents a time required for displaying one frame of the field. The horizontal

synchronizing signal represents a time required for displaying one line of the field. Thus, the horizontal

synchronizing signal includes pulses corresponding to the 20 number of pixels included in one line. The data enable signal represents a time at which the pixel is supplied with a data.

The data signal generator 32 receives a data (R,G,B) from 25 the interface 10, and rearranges the received data (R,G,B) so that the data can be supplied to the liquid crystal display panel 2 and then applies the same to the data driver 18. The oscillator 26 generates a desired reference clock and makes a frequency division of the reference 30 clock to apply a pre-synchronizing signal having the same frequency as an input signal to the signal presence determiner 28.

An operation of the signal presence determiner 28 will be described with reference to Fig. 4 below.

In Fig. 4, the signal presence determiner 28 includes a 5 frequency comparator 44 for receiving an input signal 42 and a pre-synchronizing signal 41, and a signal presence comparator 46 and a signal absence comparator 48 for checking a variation in a compared frequency signal.

10 The input signal 42 is received from the interface 10 and the presynchronizing signal 41 having the same frequency as the input signal 42 is inputted from the oscillator 26 to the frequency comparator 44. The frequency comparator 44 compares a frequency of the pre-synchronizing signal 41 15 with that of the input signal 42. In other words, the frequency comparator 44 compares a frequency of the pre-

synchronizing signal with a frequency of the input signal 42 detected during a desired period. At this time, the detected frequency has a +5Hz range of the pre 20 synchronizing signal 41.

Accordingly, a frequency within +5Hz compared from the frequency comparator 44 is applied to the signal presence comparator 46. The signal presence comparator 46 compares 25 the input signal 42 with the presynchronizing signal 41 like the A region in Fig., 5 to apply a low-state judgment signal indicating to be an effective signal input to the control signal generator 30 when the input signal 42 is larger than a repetition number of high state or low state 30 and a set value N. At this time, the control signal generator 30 having received a low-state judgment signal is supplied with an input signal received from the interface 10. The later operation conforms to an operation

of generating a general control signal.

However, when a frequency compared at the frequency comparator is more than +5Hz, the input signal is applied 5 to the signal absence comparator 48. The signal absence comparator 48 compares the input signal 42 with the ore-

synchronizing signal 41 like the B region in Fig. 5 to apply a high-state judgment signal indicating to be an ineffective signal input to the control signal generator 10 30 when the input signal 42 is smaller than a repetition number of high state or low state and a set value N. At this time, the control signal generator 30 having received a high-state judgment signal receives the pre-

synchronizing signal 41 from the oscillator 26 to display 15 a full black, a full white or a certain picture information on the liquid crystal display panel 2.

To this end, the control signal generator 30 includes a multiplexer (MUX) 40 as shown in Fig. 6. Referring to Fig. 20 6, a pre-synchronizing signal, an input signal and a judgment signal are inputted to the MUX 40- The MUX 40 selectively outputs any one of the pre-synchronizing signal and the input signal in response to an input state of the judgment signal. The MUX 40 outputs an input signal 25 when a low-state judgment signal is inputted from the signal presence determiner 28 while outputting a pre-

synchronizing signal when a high-state judgment signal is inputted therefrom.

30 The control signal generator 30 generates a control signal in response to a synchronizing signal outputted from the MUX 40 and applies the control signal to the gate driver 20 and the data driver 18. At this time, the data signal

generator 32 applies a data signal stored in a storage device in advance to the data driver 18.

Fig. 7 is a flow chart representing an operation of S another embodiment of the signal presence determiner shown in fig. 3.

Referring to Fig. 7, the signal presence determiner includes a period detector for receiving an input signal 10 50 and a pre-synchronizing signal 52, a period comparator 56 for comparing the detected period range with a set period range, a signal presence comparator 58 and a signal absence comparator 60 for determining a presence of the compared period, and a signal presence/absence comparator 15 62 for determining a presence of a signal finally.

The period detector 54 receives the input signal 50 and the presynchronizing signal 52 to compare periods of them, thereby outputting a period signal Pvsync and a detection 20 reference signal Refveync. The period comparator 56 compares the period signal Pvsync from the period detector 54 with the set maximum (MAX) and minimum (MIN) values to output a comparator output signal COM. The signal presence comparator 58 and the signal absence comparator 60 25 determine a presence of an input signal Vsync in response to the comparator output signal COM from the period comparator 56 to output a judgment signal. The signal presence/absence comparator 62 finally determines a presence of the judgment signal to output a detection 30 signal DET.

As shown in Fig. 8, the signal presence determiner compares an input signal Vsync inputted from the interface i3

lO with a pre-synchronizing signal Refclk inputted from the oscillator 26 to output a detection signal DET.

Hereinafter, this will be described with reference to Fig. 5 9 to Fig. ll in detail.

Referring to Fig. 9, the period detector 54 has two input terminals and two output terminals. An input signal Vsync from the interface lO is applied to a first input terminal 10 Vsync while a pre-synchronizing signal Refclk from the oscillator 26 is applied to a second input terminal Refolk.

The period detector 54 compares two signals applied to the first and second input terminals Vsync and Refclk to output a period signal Pvsync and a detection reference 15 signal Refvsync for the input signal Vsync, and applies the same to the period comparator 56.

Referring to Fig. lO, the period comparator 56 includes a first comparator 70 having two input terminals and one 20 output terminal, and a second comparator 72 having two input terminals and one output terminal. A period signal Pvsync detected from the period detector 54 is inputted to a first input terminal Pvsync of the first comparator 70 while a period signal MAX having a set maximum period 25 value MAX is inputted to a second input terminal MAX thereof. A period signal MIN having a set minimum period value MIN is inputted to a first input terminal MIN of the second comparator 72 while a period signal Pvsync detected from the period detector 54 is inputted to a second input 30 terminal thereof.

The period comparator 56 compares the period signal Pvsync from the period detector 54 with the maximum period value

MAX and the minimum period value MIN of the first and second comparators 70 and 72 to detect a period range of the period signal Pvsync.

S At this time, a period of the period signal Pvsync larger than the maximum period value MAX is detected at the first comparator 70 while a period of the period signal Pvsync smaller than the minimum period value MIN is detected at the second comparator 72. An output signal COM detected 10 from the first and second comparators 70 and 72 in this manner is applied to the signal presence comparator 58 and the signal absence comparator 60. In this case, a period signal Pvsync beyond a range of the maximum and minimum periods MAX and MIN is applied to the signal absence 15 comparator 60, whereas a period signal Pvsync within the maximum and minimum periods MAX and MIN is applied to the signal presence comparator 58.

Referring to Fig. ll, the signal presence comparator 58 20 and the signal absence comparator 60 have two input terminal and one output terminal. An output signal COM within a range set at the period comparator 56 is a first input terminal COM of the signal presence comparator 58 while a detection reference signal Refvsync from the 25 period detector 54 is applied to a second input terminal Refvsync thereof.

Accordingly, the signal presence comparator 58 determines to be a presence signal DET when the number of continuous 30 pulses of the output signal COM during an input interval of the detection reference signal Retvsync is larger than a set P value. For instance, it determines to be a signal presence if a pulse having continuous "l" values is larger is

than a set P: values whereas it determines to be a signal absence if not. The presence signal DET determined in this manner is applied to the signal presence/absence comparator 62. Herein, the set P value can be controlled 5 by a user.

An output signal COM beyond a range set from the period comparator 56 is a first input terminal COM of the signal absence comparator 60 while a detection reference signal 10 Refvsync from the period detector 54 is applied to a second input terminal Refvsync thereof.

Accordingly, the signal absence comparator 60 determines to he an absence signal DET when the number of continuous 15 pulses of the output signal COM during an input interval of the detection reference signal Refvsync is smaller than_ a set P value. The absence signal DET determined in this manner is applied to the signal presence/absence comparator 62.

In the signal presence/absence comparator 62, an input signal 50 determined to be a presence signal from the signal presence comparator 58 and the signal absence comparator 60 outputs a signal corresponding to a normal 2s operation. On the other hand, an input signal 50 determined to be an absence signal is applied to the control signal generator 30 to receive a pre-synchronizing signal from the oscillator 26, thereby outputting a full black, a full white or a certain pre-stored data. At this 30 time, the certain data allows a black data or a text data, etc. showing an absence signal input state to be displayed on the liquid crystal display panel 2.

As described above, according to the present invention, the signal presence/absence determiner of the timing controller further includes the period detector and the period comparator, thereby detecting a presence/absence of 5 an input signal from the interface. Furthermore, a frequency range of the input signal is detected, so that it becomes possible to support various frequency ranges of a liquid crystal module for a monitor.

10 Although the present invention has been explained by the embodiments shown in the drawings described above, it should be understood to the ordinary skilled person in the art that the invention is not limited to the embodiments, but rather that various changes or modifications thereof 15 are possible without departing from the spirit of the invention. Accordingly, the scope of the invention shall be determined only by the appended claims and their equivalents.

Claims

Claims:

1. A method of driving a display comprising: receiving an input signal having a first frequency; generating a signal with a desired frequency from the input signal; detecting whether the signal with a desired frequency alternates between a high state and a low state; counting a number of states of which the signal with a desired frequency does not alternate between the high state and the low state; and detemmining whether the number is greater than one.

2. The method according to claim 1, wherein the input signal includes a vertical synchronization signal.

3. The method according to claim 1 or 2, wherein the input signal includes a data enable signal.

4. The method according to claim 1, 2 or 3, wherein a reference signal having substantially the same frequency as the first Frequency is used to determine whether the signal with a desired frequency alternates between the high state and the low state.

5. The method according to claim 1, 2 or 3, wherein the first frequency of the input signal is compared to a reference frequency to determine whether the signal with a desired frequency has alternating states.

6. The method according to any of claims 1 to 5, wherein the input signal is from a computer and is for a liquid crystal display.

7. The method according to any one of claims 1 to 6, wherein the input signal is detemmined to have an error if the number is greater than one.

8. A method of driving a display comprising: receiving a vertical synchronization signal; generating a signal with a desired frequency from the vertical synchronization signal, the signal with a desired frequency indicating whether the vertical synchronization signal has an error; and outputting a desired video signal to the display when the error is detected.

9. A method of driving a display comprising: receiving a data enable signal; generating a signal with a desired frequency from the data enable signal, the signal with a desired frequency indicating whether the data enable signal has an error; and outputting a desired video signal to the display when the error is detected.

10. The method according to claim 8 or 9, wherein the desired video signal is an all black signal.

11. The method according to claim 8 or 9, wherein the desired video signal includes color signal.

12. The method according to claim 8 or 9, wherein the desired video signal includes an image signal based on a previous image signal.

13. The method according to claim 8 or 9, wherein the desired video signal includes a message signal.

14. The method according to claim 8 or 9, wherein the desired video signal changes with time.

15. A method of driving a display comprising:

receiving an input signal having a first period within which the input signal is inputted to a number of lines in the display; determining whether the first period is within a first reference period range, the first reference period range having a maximum period and a minimum period; and outputting a signal of a first state if the first period is less than the reference period range minimum period or greater than the reference period range maximum period.

16. The method according to claim 1 S. wherein the receiving, determining and outputting steps are repeated and determining if the first state is output a second time.

17. A method of driving a display comprising: receiving an input signal having a first period within which the input signal is inputted to a number of lines in the display; determining whether the first period is less than a first reference period and greater than a second reference period, the first reference period having a maximum period and the second reference period having a minimum period; and outputting a signal of a first state if the first period is less than the first reference period and greater than the second reference period.

18. The method according to claim 17, wherein the receiving, determining and outputting steps are repeated and determining if the first state is output a second time.

19. A liquid crystal display device including a timing controller provided with a signal presence determiner for detecting an application of an input signal from an interface, wherein said signal presence determiner comprises: an oscillator for generating a reference clock having the same frequency as a horizontal synchronizing signal and a pre- synchronizing signal having the same frequency as a vertical synchronizing signal; a period detector for comparing a data enable signal from the exterior thereof with the reference clock to output a period of the input signal with the aid of a detection reference signal and the pre-synchronizing signal;

a period comparator for comparing a period range between a desired maximum value and a desired minimum value of the input signal; and signal presence/absence comparing means for determining a presence/absence of the input signal in response to a number of pulses of the input signal detected within a period range between the maximum value and the minimum value during the application of the detection reference signal.

20. The liquid crystal display device as claimed in claim 19, wherein said period range between the maximum value and the minimum value of the period comparator can be controlled by a user.

21. The liquid crystal display device as claimed in claim 19 or 20, wherein said pulse number of the signal presence/absence comparing means can be controlled by a user.

22. A method driving a liquid crystal display device including a timing controller provided with a signal presence determiner for detecting an application of an input signal from an interface, said method comprising the steps of: generating a reference clock having the same frequency as a horizontal synchronizing signal and a pre-synchronizing signal having the same frequency as a vertical synchronizing signal; comparing a data enable signal from the exterior with the reference clock to output a period of the input signal with the aid of a detection reference signal and the pre synchronizing signal; comparing a period range between a desired maximum value and a desired minimum value of the input signal; and determining a presence/absence of the input signal in response to a number of pulses of the input signal detected within a period range between the maximum value and the minimum value during the application of the detection reference signal.

23. The method as claimed in claim 22, wherein said period range between the maximum value and the minimum value can be controlled by a user.

24. The method as claimed in claim 22 or 23, wherein said pulse number of the input signal can be controlled by a user.

25. A method of driving a display, substantially as hereinbefore described with reference to and/or substantially as illustrated in any one of or any combination of Figures 3 to 11 of the accompanying drawings.

26. A liquid crystal display device substantially as hereinbefore described with reference to and/or substantially as illustrated in any one of or combination of Figures 3 to 11 of the accompany drawings.