KR20050023851A - Method and Apparatus for Driving Liquid Crystal Display Device - Google Patents

Abstract

PURPOSE: A method for driving a liquid crystal display device and an apparatus for driving the same are provided to supply the black signal to the timing controller in place of the clock signal supplied from the system when the clock signal is a frequency of an abnormal range. CONSTITUTION: An apparatus for driving a liquid crystal display device includes a system(40), a timing controller(30) and a frequency controller(42). The system supplies synchronization signal and a clock signal. The timing controller generates the control signals by converting the synchronization signals with reference to the clock signal. And, the frequency controller is installed between the system and the timing controller to limit the frequency range of the clock signal.

Description

Driving method and driving device of liquid crystal display device {Method and Apparatus for Driving Liquid Crystal Display Device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving apparatus and method of a liquid crystal display device, and more particularly, to a driving apparatus and method of a liquid crystal display device capable of displaying a stable screen regardless of a frequency variation of a clock signal.

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. The liquid crystal display device is implemented in an active matrix type in which switching elements are formed in each cell, and is applied to display devices such as computer monitors, office equipment, and cellular phones. As a switching element used in an active matrix type liquid crystal display device, a thin film transistor (hereinafter, referred to as TFT) is mainly used.

1 is a view schematically showing a driving device of a conventional liquid crystal display device.

Referring to FIG. 1, in a driving apparatus of a conventional liquid crystal display, m × n liquid crystal cells Clc are arranged in a matrix type, m data lines D1 to Dm and n gate lines G1 to A liquid crystal panel 2 having Gn intersected and a TFT formed at an intersection thereof, a data driver 4 for supplying a data signal to the data lines D1 to Dm of the liquid crystal panel 2, and gate lines. The gate driver 6 for supplying the scan signal to the G1 to Gn, the gamma voltage supply unit 8 for supplying the gamma voltage to the data driver 4, and the synchronization signal supplied from the system 20 are used. To generate the voltages supplied to the liquid crystal panel 2 by using the timing controller 10 for controlling the data driver 4 and the gate driver 6 and the voltage supplied from the power supply 12. DC converter (hereinafter, referred to as "DC / DC converter", 14) and back An inverter 16 for driving the bite 18 is provided.

The system 20 supplies the vertical / horizontal synchronization signals Vsync and Hsync, the clock signal DCLK, the data enable signal DE and the data R, G, and B to the timing controller 10.

The liquid crystal panel 2 includes a plurality of liquid crystal cells Clc formed in a matrix at the intersections of the data lines D1 to Dm and the gate lines G1 to Gn. Each TFT formed in the liquid crystal cell Clc supplies a data signal supplied from the data lines D1 to Dm to the liquid crystal cell Clc in response to a scan signal supplied from the gate line G. In addition, a storage capacitor Cst is formed in each of the liquid crystal cells Clc. The storage capacitor Cst is formed between the pixel electrode of the liquid crystal cell Clc and the front gate line, or is formed between the pixel electrode of the liquid crystal cell Clc and the common electrode line to maintain a constant voltage of the liquid crystal cell Clc. Let's do it.

The gamma voltage supply unit 8 supplies a plurality of gamma voltages to the data driver 4.

The data driver 4 converts the digital video data R, G, and B into analog gamma voltages (data signals) corresponding to the gray scale values in response to the control signal CS from the timing controller 10. The gamma voltage is supplied to the data lines D1 to Dm.

The gate driver 6 sequentially supplies scan pulses to the gate lines G1 to Gn in response to the control signal CS from the timing controller 10 to supply a horizontal signal to the liquid crystal panel 2. Select.

The timing controller 10 controls signals for controlling the gate driver 6 and the data driver 4 using the vertical / horizontal synchronization signals Vsync and Hsync and the clock signal DCLK input from the system 20. Create (GCS, DCS). The gate control signal GCS for controlling the gate driver 6 may include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE), and the like. This includes. The data control signal DCS for controlling the data driver 4 includes a source start pulse (SSP), a source shift clock (SSC), and a source output signal (SOC). And a polarity signal (POL). The timing controller 10 rearranges the data R, G, and B supplied from the system 20 and supplies the data driver 4 to the data driver 4.

The DC / DC converter 14 boosts or reduces the voltage of 3.3V input from the power supply 12 to generate the voltage supplied to the liquid crystal panel 2. The DC / DC converter 14 generates a gamma reference voltage, a gate high voltage VGH, a gate low voltage VGL, a common voltage Vcom, and the like.

The inverter 16 supplies a driving voltage (driving current) for driving the backlight 18 to the backlight 18. The backlight 18 generates light corresponding to a driving voltage (or driving current) supplied from the inverter 16 and supplies the light to the liquid crystal panel 2.

The liquid crystal display device driven as described above generates the data control signal DCS and the gate control signal GCS based on the clock signal DCLK input from the system 20. In other words, the conventional liquid crystal display generates control signals DCS and GCS by converting the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync based on the clock signal DCLK, and the generated control signal. The images corresponding to the data are displayed using the DCS and GCS.

On the other hand, the clock signal DCLK supplied from the system 20 is changed in frequency due to external noise, EMI, and the like. Here, when the frequency of the clock signal DCLK is changed, the timings of the control signals DCS and GCS generated based on the clock signal DCLK are also changed. In practice, when the frequency of the clock signal DCLK is converted above a predetermined limit, the timings of the control signals DCS and GSC are also converted to correspond to the clock signal DCLK, so that the LCD does not display a normal image. Problems that can not occur.

Accordingly, it is an object of the present invention to provide a driving apparatus and method for a liquid crystal display device capable of displaying a stable screen irrespective of frequency variation of a clock signal.

In order to achieve the above object, a driving apparatus of a liquid crystal display according to an embodiment of the present invention is a system for supplying synchronization signals and a clock signal, and generating control signals by converting the synchronization signals based on the clock signal. And a timing controller disposed between the system and the timing controller to limit a frequency range of the clock signal.

In the driving device of the liquid crystal display, the frequency controller supplies the clock signal to the timing controller when the clock signal is within an allowable frequency range, and supplies the black signal to the timing controller in other cases. do.

In the driving device of the liquid crystal display, the allowable frequency range of the clock signal is experimentally set to a range in which a normal image can be displayed on the liquid crystal panel.

In the driving device of the liquid crystal display, the frequency controller includes a black signal generator for generating the black signal, a first comparator for comparing the clock signal with an upper limit frequency that is the highest frequency of the allowable frequency range, and the allowance. A second comparator for comparing the lower limit frequency, which is a minimum frequency of a frequency range, with the clock signal, an OR gate for performing an OR operation on the outputs of the first comparator and the second comparator, and the black signal under control of the OR gate And a selector for transmitting any one of a clock signal to the timing controller.

In the driving apparatus of the liquid crystal display, the first comparator outputs a logic signal of "0" when the frequency of the clock signal is lower than the upper limit frequency.

In the driving device of the liquid crystal display, the second comparator outputs a logic signal of "0" when the frequency of the clock signal is higher than the lower limit frequency.

In the driving device of the liquid crystal display, the selector may output the clock signal when a logic signal of "0" is supplied from the or gate.

In the driving device of the liquid crystal display, the timing controller displays a black screen on the liquid crystal panel when the black signal is input.

According to an exemplary embodiment of the present invention, a method of driving a liquid crystal display device includes supplying synchronization signals and a clock signal from a system to a timing controller, and converting the control signals by converting the synchronization signals based on the clock signal by the timing controller. Generating and limiting a frequency range of the clock signal by a frequency controller provided between the system and the timing controller.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 2 and 3.

2 is a block diagram illustrating a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 2, in the driving apparatus of the liquid crystal display according to the exemplary embodiment of the present invention, m × n liquid crystal cells Clc are arranged in a matrix type, m data lines D1 to Dm and n gates are provided. A liquid crystal panel 22 having lines G1 to Gn intersected and TFTs formed at the intersections thereof, and a data driver 24 for supplying data signals to the data lines D1 to Dm of the liquid crystal panel 22. And a gate driver 26 for supplying a scan signal to the gate lines G1 to Gn, a gamma voltage supply unit 28 for supplying a gamma voltage to the data driver 24, and a frequency control unit 42 from the frequency control unit 42. A timing controller 30 for controlling the data driver 24 and the gate driver 26 by using the supplied clock signal DCLK and the synchronization signal supplied from the system 40, and the power supply unit 32. Supplied to the liquid crystal panel 22 by using a voltage DC / DC converter 34 for generating the pressures, inverter 36 for driving the backlight 38, and frequency controller for controlling the frequency range of the clock signal DCLK supplied from the system 40 (42) is provided.

The system 40 supplies the vertical / horizontal synchronization signals (Vsync, Hsync), the data enable signal (DE), and the data (R, G, B) to the timing controller 30 as well as the clock signal (DCLK). It supplies to the control part 42.

The liquid crystal panel 22 includes a plurality of liquid crystal cells Clc disposed in a matrix at the intersections of the data lines D1 to Dm and the gate lines G1 to Gn. Each TFT formed in the liquid crystal cell Clc supplies a data signal supplied from the data lines D1 to Dm to the liquid crystal cell Clc in response to a scan signal supplied from the gate line G. In addition, a storage capacitor Cst is formed in each of the liquid crystal cells Clc. The storage capacitor Cst is formed between the pixel electrode of the liquid crystal cell Clc and the front gate line, or is formed between the pixel electrode of the liquid crystal cell Clc and the common electrode line to maintain a constant voltage of the liquid crystal cell Clc. Let's do it.

The gamma voltage supply unit 28 supplies a plurality of gamma voltages to the data driver 24.

The data driver 24 converts the digital video data R, G, and B into analog gamma voltages (data signals) corresponding to the gray scale values in response to the control signal CS from the timing controller 30. The gamma voltage is supplied to the data lines D1 to Dm.

The gate driver 26 sequentially supplies scan pulses to the gate lines G1 to Gn in response to the control signal CS from the timing controller 30 to supply a horizontal signal of the liquid crystal panel 22. Select.

The timing controller 30 receives the vertical / horizontal synchronization signals Vsync and Hsync from the system 40, and receives the clock signal DCLK or the black signal from the frequency setting unit 42. When the clock signal DCLK is input from the frequency setting unit 42, the timing controller 30 generates control signals GCS and DCS for controlling the gate driver 26 and the data driver 24. The gate control signal GCS for controlling the gate driver 26 may include a gate start pulse (GSP), a gate shift clock (GSC), a gate output signal (GOE), and the like. This includes. The data control signal DCS for controlling the data driver 24 includes a source start pulse (GSP), a source shift clock (SSC), and a source output signal (SOC). And a polarity signal (POL). The timing controller 30 rearranges the data R, G, and B supplied from the system 40 and supplies the data driver 24 to the data driver 24. When the black signal is input from the frequency setting unit 42, the timing controller 30 generates a gate control signal GCS and a data control signal DCS to display a black screen on the liquid crystal panel 22. And control the data.

The DC / DC converter 34 generates a voltage supplied to the liquid crystal panel 22 by increasing or decreasing the voltage of 3.3V input from the power supply unit 32. The DC / DC converter 34 generates a gamma reference voltage, a gate high voltage VGH, a gate low voltage VGL, a common voltage Vcom, and the like.

The inverter 36 supplies a driving voltage (driving current) for driving the backlight 38 to the backlight 18. The backlight 38 generates light corresponding to a driving voltage (or driving current) supplied from the inverter 16 and supplies the light to the liquid crystal panel 22.

The frequency controller 42 supplies the clock signal DCLK to the timing controller 30 when the clock signal DCLK supplied from the system 40 is in the normal range, and transmits the black signal when the frequency signal is in the abnormal range. 30). Here, the frequency within the forward three ranges is experimentally determined as the frequency within the range that no screen abnormality occurs. In practice, the frequency in the normal range varies slightly depending on the inch, resolution, type of timing controller used, and the like. Therefore, frequencies within the range where no screen abnormality occurs (that is, frequencies between the lower limit frequency and the upper limit frequency) are determined by various experiments.

The frequency controller 42 includes a first comparator 52 for comparing the frequency of the clock signal DCLK supplied from the system 30 with the upper limit frequency as shown in FIG. 3, and a clock supplied from the system 30. A second comparator 54 for comparing the frequency of the signal DCLK and a lower limit frequency, an OR gate 56 for performing an OR operation on the outputs of the first comparator 52 and the second comparator 54, and an or gate A selector 58 for outputting any one of a frequency of the clock signal DCLK supplied from the system 30 and a black signal input from the black signal generator 60 in response to the output signal of 56; do.

The first comparator 52 compares the frequency of the clock signal DCLK with the upper limit frequency. Here, the upper limit frequency represents a range of the maximum clock frequency at which no screen abnormality occurs. The first comparator 52 outputs a first control signal (for example, a logic signal of "0") when the clock frequency is lower than the upper limit frequency, and in other cases, the second control signal (for example, Logic signal of " 1 "

The second comparator 54 compares the frequency of the clock signal DCLK with the lower limit frequency. Here, the lower limit frequency represents the range of the minimum clock frequency at which no screen abnormality occurs. The second comparator 54 outputs a first control signal (for example, a logic signal of " 0 ") when the clock frequency is higher than the lower limit frequency. Otherwise, the second comparator 54 outputs a second control signal (for example, Logic signal of " 1 "

The OR gate 56 receives the outputs of the first and second comparators 52 and 54. This or gate 56 is provided with a clock frequency supplied from the system 40 if the output of each of the first and second comparators 52 and 54 is a first control signal (eg, a logic signal of " 0 "). Is a normal range, a low signal (for example, a logic signal of " 0 ") is supplied to the selector 58. And OR gate 56 is supplied from system 40 if the output of either of the first and second comparators 52,54 is a second control signal (e.g., a logic signal of " 1 "). If the clock frequency is an abnormal range, a high signal (for example, a logic signal of "1") is supplied to the selector 58.

The black signal generator 60 generates a black signal to supply the black signal to the data lines D1 to Dm. When the clock signal DCLK supplied from the system 40 is above or below the normal range, that is, when the clock signal DCLK having a frequency of an abnormal range is supplied, the black signal generator 60 breaks the screen. Since it becomes unstable, processing with a black signal makes it possible to display a stable screen.

The selector 58 selects any one of a clock signal DCLK supplied from the system 40 and a black signal supplied from the black signal generator 60 according to a logic operation signal supplied from the or gate 56. Supply to the timing controller 30. In other words, if the clock signal DCLK supplied from the system 40 is in the normal range of frequency, the OR gate 56 supplies a low signal to the selector 58. Accordingly, the selector 58 supplies the clock signal DCLK supplied from the system 40 to the timing controller 30. If the clock signal DCLK supplied from the system 40 is in an abnormal range of frequency, the OR gate 56 supplies a high signal to the selector 58. Accordingly, the selector 58 supplies the black signal supplied from the black signal generator 60 to the timing controller 30. Accordingly, the screen abnormality can be improved by treating the screen abnormality generated due to the abnormal range clock signal DCLK supplied from the system 40 as a black signal.

Referring to the operation of the frequency control unit 42 as an example, it is assumed that the upper limit frequency of the first comparator 52 is set to 50 MHz and the lower limit frequency of the second comparator 54 is set to 10 MHz. . In addition, it is assumed that the frequency of the normal range of the clock signal DCLK supplied from the system 40 is 10 MHz to 50 MHz.

First, if a clock signal DCLK having a frequency in the normal range of 25 MHz from the system 40 is supplied to the first and second comparators 52 and 54 in the frequency control section 42, the first comparator 52 Since it is lower than the upper limit frequency, a logic signal of "0" is output, and the second comparator 54 outputs a logic signal of "0" because it is higher than the lower limit frequency. The outputs of the first and second comparators 52 and 54 are supplied to the input terminals of the or gate 56. Therefore, the OR gate 56 outputs the logic signal of "0" by a logic operation. The logic signal of "0" output from the OR gate 56 is input to the control terminal of the selector 58. Since the selector 58 inputs a logic signal of "0" from the or gate 56, the system includes a 25 MHz clock signal DCLK supplied from the system 40 and a black signal generated from the black signal generator 60. A clock signal DCLK of 25MHz supplied from 40 is selected and supplied to the timing controller 30.

If the clock signal DCLK having 60 MHz, which is higher than the upper limit frequency of the normal range, is supplied from the system 40 to the first and second comparators 52 and 54 in the frequency controller 42, the first comparator Reference numeral 52 denotes a logic signal of "1" because it is higher than the upper limit frequency, and the second comparator 54 outputs a logic signal of "0" because it is higher than the lower limit frequency. The outputs of the first and second comparators 52 and 54 are supplied to the input terminals of the or gate 56. Therefore, the OR gate 56 outputs the logic signal of "1" by a logic operation. The logic signal of "1" output from the OR gate 56 is input to the control terminal of the selector 58. Since the selector 58 receives a logic signal of "1" from the or gate 56, the black signal of the 60 MHz clock signal DCLK supplied from the system 40 and the black signal generated from the black signal generator 60 is black. The black signal generated from the signal generator 60 is selected and supplied to the timing controller 30. Accordingly, the screen abnormality can be improved by treating the screen abnormality generated due to the abnormal range clock signal DCLK supplied from the system 40 as a black signal.

If the clock signal DCLK having 5 MHz, which is lower than the lower limit frequency of the normal range, is supplied from the system 40 to the first and second comparators 52 and 54 in the frequency controller 42, the first comparator Reference numeral 52 denotes a logic signal of "0" because it is lower than the upper limit frequency, and outputs a logic signal of "1" because the second comparator 54 is lower than the lower limit frequency. The outputs of the first and second comparators 52 and 54 are supplied to the input terminals of the or gate 56. Therefore, the OR gate 56 outputs the logic signal of "1" by a logic operation. The logic signal of "1" output from the OR gate 56 is input to the control terminal of the selector 58. Since the selector 58 receives a logic signal of "1" from the or gate 56, the black signal of the 5 MHz clock signal DCLK supplied from the system 40 and the black signal generated from the black signal generator 60 is black. The black signal generated from the signal generator 60 is selected and supplied to the timing controller 30. Accordingly, the screen abnormality can be improved by treating the screen abnormality generated due to the abnormal range clock signal DCLK supplied from the system 40 as a black signal.

As described above, the driving apparatus and method of the liquid crystal display according to the present invention supply the black signal to the timing controller instead of the clock signal supplied from the system if the clock signal supplied from the system is in an abnormal range of frequencies. Accordingly, it is possible to improve the screen abnormality caused by the clock signal having an abnormal range of frequencies supplied from the system.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a block diagram showing a driving device of a conventional liquid crystal display device.

2 is a view showing a driving device of a liquid crystal display device according to an embodiment of the present invention;

3 is a view illustrating in detail the frequency control unit shown in FIG.

<Description of Symbols for Main Parts of Drawings>

2,22 LCD panel 4,24 Data driver

6,26: gate driver 8,28: gamma voltage supply

10,30: timing controller 12,32: power supply

14,34: DC / DC converter 16,36: inverter

18,38: backlight 20,40: system

42: black signal generator 52, 54: first and second comparators

56: or gate 58: selection unit

60: black signal generator

Claims (16)

A system for supplying synchronization signals and a clock signal; A timing controller for generating control signals by converting synchronization signals based on the clock signal; And a frequency controller disposed between the system and the timing controller to limit a frequency range of the clock signal. The method of claim 1, And the frequency controller supplies the clock signal to the timing controller when the clock signal is within an allowable frequency range, and supplies a black signal to the timing controller in other cases. The method of claim 2, The allowable frequency range of the clock signal is experimentally set to a range in which a normal image can be displayed on the liquid crystal panel. The method of claim 2, The frequency control unit A black signal generator for generating the black signal; A first comparator for comparing the upper limit frequency which is the highest frequency of the allowable frequency range with the clock signal; A second comparator for comparing the clock signal with a lower limit frequency which is a minimum frequency of the allowable frequency range; An OR gate for ORing the outputs of the first and second comparators; And a selector for transmitting one of the black signal and the clock signal to the timing controller under control of the or gate. The method of claim 4, wherein And the first comparator outputs a logic signal of " 0 " when the frequency of the clock signal is lower than the upper limit frequency. The method of claim 4, wherein And the second comparator outputs a logic signal of " 0 " when the frequency of the clock signal is higher than the lower limit frequency. The method of claim 4, wherein And the selector outputs the clock signal when a logic signal of " 0 " is supplied from the or gate. The method of claim 2, And the timing controller displays a black screen on the liquid crystal panel when the black signal is input. Supplying the synchronization signals and the clock signal from the system to the timing controller; Generating control signals by converting synchronization signals based on the clock signal by the timing controller; And limiting a frequency range of the clock signal by a frequency controller provided between the system and the timing controller. The method of claim 9, The clock signal is supplied to the timing controller by the frequency controller when the clock signal is within the allowable frequency range, and the black signal is supplied to the timing controller in other cases. . The method of claim 10, The allowable frequency range of the clock signal is experimentally set to a range in which a normal image can be displayed on the liquid crystal panel. The method of claim 10, Limiting the frequency range of the clock signal by the frequency control unit A first step of generating the black signal by a black signal generator; A second step of comparing the clock signal with an upper limit frequency which is the highest frequency of the allowable frequency range by a first comparator; A third step of comparing the clock signal with a lower limit frequency which is a minimum frequency of the allowable frequency range by a second comparator; A fourth step of performing an OR operation on the outputs of the first and second comparators by an OR gate; And a fifth step of transmitting one of the black signal and the clock signal to the timing controller by a selector controlled by the or gate. The method of claim 12, And a logic signal of " 0 " is outputted by the first comparator when the frequency of the clock signal is lower than the upper limit frequency in the second step. The method of claim 12, And a logic signal of " 0 " is output by the second comparator when the frequency of the clock signal is higher than the lower limit frequency in the third step. The method of claim 12, And the clock signal is output by the selector when a logic signal of " 0 " is supplied from the or gate in the fifth step. The method of claim 12, And a black screen is displayed on the liquid crystal panel by the timing controller when the black signal is input.