TWI415087B - Liquid crystal display device with clock signal embedded signaling - Google Patents

Abstract

A display device includes a display panel, a timing controller generating a timing controlling signal having a plurality of states, each state representing both data information and clock information, and a source driver receiving and decoding the timing controlling signal to recover the data information and the timing information for generating a clock signal and a data signal for driving the display panel.

Description

Liquid crystal display with clock signal embedded in the clock signal

The embodiments described herein relate to a display device, and more particularly to a display device having an embedded clock signal.

Recently, flat panel displays are gradually being implemented in liquid crystal display and plasma display technologies, and have been built into screens such as personal computers and television receivers. In general, a circuit mounted to a flat panel display is composed of a timing controller, a power supply unit, a gate voltage generator, a data driver integrated circuit, and a gate driver integrated circuit. In the display device equipped with a large-size and high-resolution screen, countermeasures against electromagnetic interference (EMI) caused by the transmission line, especially for the interface between the timing controller and the driver integrated circuit The countermeasures against interference have become quite necessary.

In order to overcome electromagnetic interference and achieve high-speed data transmission with low power at the same time, various standards have been developed for the interface using the differential signaling method, such as Reduced Swing Differential Signaling (RSDS), Mini-Low Voltage Differential Signaling (Mini-LVDS) and Point-to-Point Differential Signaling (PPDS).

Figure 1 is a schematic diagram of a conventional display device utilizing the RSDS standard, and Figure 2 is a schematic diagram of a conventional display device utilizing the mini-LVDS standard. In Figures 1 and 2, display device 100 or 200 includes one or more data signal lines 12 (differential signal lines) for transmitting data signals DATA and a single clock signal line separate from the data lines 12. (Differential signal line) 11 transmits a single clock signal CLOCK, wherein the clock signal CLOCK is synchronized with the data signal DATA. The display device 100 or 200 employs a Multi-Drop Method in which a plurality of source drivers 110_1 to 110_m share the same clock signal line 11. The disadvantage of this configuration is that the maximum operating rate is limited by the large load of the clock signal. In addition, because the impedance is not matched at the signal line separation, the information transmission is susceptible to signal distortion and severe electromagnetic interference.

Figure 3 is a schematic diagram of a conventional display device utilizing the PPDS standard. In FIG. 3, the display device 300 includes a plurality of clock signals CLOCK_1 to CLOCK_m, which are respectively transmitted to the respective source drivers 310_1 to 310_m, thereby solving the first and second displays using the RSDS or mini-LVDS1 standard. A large load problem with a single clock signal encountered by the device. In addition, a plurality of data signal lines 32_1 to 32_m are respectively connected to the source drivers 310_1 to 310_m to respectively transmit the data signals DATA_1 to DATA_m, thereby solving impedance mismatch and electromagnetic interference. However, in most applications, the clock signals CLOCK_1 to CLOCK_m must be transmitted at a higher rate, and as a result, different clock signal lines 31_1 to 31_m need to be built. This leads to higher manufacturing costs. In addition, The data signal DATA_i and the clock signal CLOCK (i between 1 and 0) for sampling the data signal DATA_i cannot avoid the offset (Skew), resulting in inaccurate sampling process or additional circuitry to compensate for this bias. shift.

Another configuration (not shown) has recently been proposed to address impedance mismatch and electromagnetic interference problems by sequentially transmitting clock signals to source drivers connected in series. However, the clock signal will be delayed between the source drivers, causing data sampling to fail.

In this context, a display device and a multi-level messaging method are described which are capable of improving electromagnetic interference characteristics and clock sampling.

According to one aspect, a liquid crystal display device includes a display panel and a timing controller that generates a timing control signal having a plurality of states, each state simultaneously representing data information and clock information, and a source The driver is configured to receive and decode the timing control signal to recover the data information and the clock information for generating a clock signal and a data signal to drive the display panel.

According to another aspect, a method for communication between a timing controller and a source driver of a display device includes generating a timing control signal having a plurality of states, each state simultaneously representing data Information and clock information, and receiving and decoding the timing control signal to recover the data information and clock information for generating a clock signal and a data signal.

According to another aspect, a display device includes a display panel and a timing controller that generates a timing control signal having a plurality of states, each state indicating one of the data signals supplied to the display panel a logic value of one of a high logic value and a low logic value, and a logic value corresponding to one of a high logic value and a low logic of a clock signal supplied to the display panel, and each state system has at least one a voltage level different from the other states, the plurality of comparators configured to compare the at least one voltage level of the timing signal with the at least one predetermined voltage to generate a data signal, a thyristor, according to the plurality of comparators The output generates a clock signal, and a delay logic unit configured to delay one of the data signal generated by the comparators or the clock signal generated by the gate.

The above and other features, aspects, and embodiments are described in the following embodiments.

4A and 4B are schematic views of an exemplary display device in accordance with an embodiment. In FIGS. 3A and 4B, the display device 400 can be configured to include a timing controller 410, source drivers 420_1 to 420_m, gate drivers 430_1 to 430_m, and multi-information signal lines LM_1 to LM_m (m is a non-zero integer). .

The timing controller 410 can be configured to transmit the timing control signals SCTRL_1 through SCTRL_m to the corresponding source drivers 420_1 through 420_m through the corresponding multi-information signal lines LM_1 through LM_m. Source drivers 420_1 to 420_m can be grouped The state switches the received timing control signals SCTRL_1 to SCTRL_m and provides the data signals SD_1 to SD_m to the panel 440.

The gate driver 430 is configurable to provide scan signals SS_1 through SS_n to the panel 440. The panel 440, such as an LCD panel, an OLED panel, and a PDP panel, is configurable to provide an image frame based on the above-described data signals SD_1 to SD_m and scan signals SS_1 to SS_n.

For example, each of the timing control signals SCTRL_i (i is an integer between 1 and m) carried on a corresponding multi-information signal line LM_i may contain a plurality of types of information, such as clock information and data information. . In this way, the clock information can be embedded in the timing control signal SCTRL_i. Specifically, each timing control signal SCTRL_i may have a plurality of states STATE_i, 1, STATE_i, 2, ..., STATE_i, p (p is defined as the total number of states and is a non-zero integer), wherein each state STATE_i , j (j is the state number and is an integer between 1 and p) can represent multiple kinds of information, not a single kind of information. In a preferred embodiment, each state STATE_i,j represents at least the clock information and the data information at the same time. The timing control signal SCTRL_i can be switched between different states STATE_i, 1, STATE_i, 2, ..., STATE_i, p over time to transmit the clock information and data information respectively represented by these states.

For example, each state STATE_i,j in this embodiment may represent a timed pulse signal value CLOCK_i,j and a predetermined data signal value DATA_i,j. The timing control signal can be converted between different states STATE_i, 1, STATE_i, 2, ..., STATE_i, p to different clock values and different resources corresponding to these different states. The signal value is supplied to the source driver 420_i at the same time. In the preferred case, the total number of states is equal to 4, and the four states correspond to (DATA, CLOCK) = (1, 1), (1, 0), (0, 0), and (0, 1), respectively. The invention is not limited to this as an example only).

In FIG. 4B, each source driver 420_i can be configured to include a further decoder 450_i to decode the respective timing control signal SCTRL_i to obtain the data information transmitted from the timing controller 410. Pulse information. For example, the decoder 450_i can be configured to detect the state of the timing control signal SCTRL_i to obtain individual data information and clock information of the detected state.

In the 4A and 4B diagrams, only a single type of signal line, that is, the above-described multi-information line LM_i, may be disposed between the timing controller 410 and the corresponding source driver 420_i. In addition, only a single type of signal, the timing control signal SCTRL_i, can be used to simultaneously transmit clock information and data information, wherein each state corresponds to a clock signal value and a data signal value.

In FIG. 4A, the display device 400 illustratively employs a "point-to-point" structure in which each of the plurality of source drivers 420_1 through 420_m is permeable to a respective multi-information signal line. To connect to the timing controller 410 without sharing the same signal line. However, a "single point to many points" structure can also be used.

Table 1 is a sort of the state code of the timing control signal of FIG. 4A and the corresponding data and time signal value corresponding to FIG. 4A according to one embodiment, and Table 2 According to another embodiment, the state code of the timing control signal of FIG. 4A and the corresponding data and time signal value corresponding thereto are arranged.

In Table 1 and Table 2, the total number of states p is equal to 4, that is, the timing control signal SCTRL_i can be between four states STATE_i, 1 to STATE_i, 4 Convert (i is any integer between 1 and m). Here, the number of each state is numbered by a parameter NUM. In Table 1, the four states are (DATA, CLOCK) = (1, 1), (1, 0), (0, 0), and (0, 1), and in Table 2, four states. The system indicates (DATA, CLOCK) = (0, 1), (1, 1), (1, 0), and (0, 0).

In Table 1, during the period of the enablement period, the valid data information is transmitted at this time, or the source driver 420_i is enabled to receive the data information, and the clock signal value CLOCK can be required to be switched back and forth between 0 and 1. In other words, the conversion is performed in a conversion mode of CLOCK=(1→0→1→0→...). However, during these enablement periods, there is no need to request the data signal value DATA to have any particular conversion mode. As a result, the timing control signal can be required to be converted in a mode of (NUM) = (1 or 4 → 2 or 3 → 1 or 4 → 2 or 3). For example, in a certain period, the timing control signal is converted (NUM)=(1→3→4→2) in the following manner, which represents that the clock and data information received by the corresponding source driver are respectively CLOCK. = (1 → 0 → 1 → 0) and data information DATA = (1 → 0 → 0 → 1).

In Table 2, the timing control signal SCTRL can be converted in a mode of (NUM) = (1 or 2 → 3 or 4 → 1 or 2 → 3 or 4) for similar reasons. Comparing Table 1 and Table 2, Table 1 provides an additional confirmation mechanism for the correctness of the transmission. In Table 1, the state number NUM can vary by only 1 or 2, which allows an error to be detected when a condition with a magnitude of change of 3 occurs. Conversely, the status number in Table 2 can be 1, 2 or 3, and thus no confirmation mechanism can be provided.

During the period of the disabling period, no valid data information is transmitted at this time, or the source driver 420_i, or the source driver 420_i is disabled to stop receiving the data information, and the clock signal value CLOCK may be maintained at zero. In addition, the states of the timing control signals in the 5A and 5B diagrams may be further set to be converted in a specific mode, for example, (NUM)=(...2→3→2→3→.. .) and (...3→4→3→4→...) to enable the decoder 450_i to be configured to determine the end of the disabling period by detecting the state mode of the timing control signal SCTRL_i, It will be explained in detail using 8, 9, 10A, and 10B.

In Figures 4A and 4B, the timing control unit SCTRL_i can be a single-ended signal, or preferably it can also be a pair of differential signals. In addition, various electronic characteristics of the timing control signal, such as voltage level and current level, can be used to set the timing control signal SCTRL_i to different states. Since the timing control signal SCTRL_i is set to a different state with different corresponding current/voltage levels, the individual decoders 450_i in the source driver 420_i can be configured to at least one of the current/voltage levels of the timing control signal SCTRL_i. The current/voltage level is compared to decode the timing control signal SCTRL_i to obtain data information and clock information.

For example, the timing control signal SCTRL_i can be a single-ended signal that can be switched between p different voltage levels V_1 to V_p, where p represents the total number of states. In other words, each state has a voltage level of one of these voltage levels V_1 to V_p. In another example, the timing control signal SCTRL_i can be a pair of differences The signal SCTRL_i(I) and SCTRL_(Q) can be switched between different voltage levels. Specifically, for each state STATE_i,j of the timing control signal SCTRL_i, the differential signal SCTRL_i(I) may have a different level VI_i,j, which may be at the first plurality of voltage levels VI_i_1 to VI_i, The conversion between q1, and the other differential signal SCTRL_i(I) may have a different level VQ_i,j, which can be converted between the second plurality of voltage levels VQ_i_1 to VQ_i, q2 (q1 and q2 are non- Zero integer). In other words, each state has two voltage levels, one of which is one of the first plurality of voltage levels VI_i_1 to VI_i, q1, and the other voltage level criterion is the second plurality of voltage levels. One of the quasi-VQ_i_1 to VQ_i, q2. Preferably, q1 = q2. More preferably, both q1 and q2 are either equal to or equal to three.

Table 3 is a voltage level of a pair of differential signals for timing control signals in different states according to one of the embodiments, wherein q1=q2=4 and p=4.

As shown in Table 3, the voltage levels V(I) and V(Q) of the differential signals SCTRL_i(I) and SCTRL_i(Q) are collectively expressed as (V(I), V(Q)). For the status numbers 1, 2, 3, and 4, it is set to (1.5, 0.9), (1.3, 1.1), (1.1, 1.3), and (0.9, 1.5), respectively.

Figure 5 is a schematic diagram showing the relationship between the voltage level in Table 3 and two predetermined DC voltages in accordance with one of the embodiments. As shown, two DC voltages RH=1.4V and RL=1.0V are plotted along with the four voltage levels of the differential signals SCTRL_i(I) and SCTRL_i(Q) to show their relative sizes. The four voltage levels (V1, V2, V3, V4) = (1.5, 1.3, 1.1, 0.9) and the two DC voltages RH = 1.4V and RL = 1.0V form a symmetrical relationship. The two predetermined voltages RH and RL may be supplied to the source drivers 420_1 to 420_m in the execution of decoding to define the four voltage levels V1 to V4, the details of which will be described below with reference to FIG.

Table 4 is a voltage level of a pair of differential signals for timing control signals in different states according to one of the other embodiments, wherein q1=q2=3 and p=4.

Form 4

As shown in Table 4, the voltage levels V(I) and V(Q) of the differential signals SCTRL_i(I) and SCTRL_i(Q) are collectively expressed as (V(I), V(Q)). For the status numbers 1, 2, 3, and 4, it is set to (1.5, 1.1), (1.3, 1.1), (1.1, 1.3), and (1.1, 1.5), respectively.

Figure 6 is a schematic diagram showing the relationship between the voltage level in Table 4 and a predetermined DC voltage according to one of the embodiments. As shown, the DC voltage RH=1.2VV is plotted along with the three voltage levels of the differential signals SCTRL_i(I) and SCTRL_i(Q) to show their relative sizes. The three voltage levels (V1, V2, V3) = (1.5, 1.3, 1.1) and this DC voltage RH = 1.2V constitute an asymmetrical relationship. This one predetermined voltage RH may be supplied to the source drivers 420_1 to 420_m in the execution of decoding to define the three voltage levels V1 to V3, the details of which will be described below with reference to FIG.

Figure 7 is a schematic diagram of an example decoder of a source driver employing a four-state timing control signal in accordance with one embodiment. In Fig. 7, the source driver 420_i (1) of the 4A and 4B is shown. i m ) decoder 450_i, wherein the source driver 450_i uses a pair of four-bit (q1=q2=4) differential signals SCTRL_i(I) and SCTRL_i(Q) as a four-state (total number of states p= 4) The timing control signal SCTRL_i is as shown in Tables 3 and 5. The decoder 450 is configured to receive the differential signals SCTRL_i(I) and SCTRL_i(Q) and the two predetermined voltages RH and RL to recover clock information and data information.

A comparator 810 compares the differential signal SCTRL_i(I) with the voltage level of SCTRL_i(Q) to obtain an output O1. The decoder 450_i can use the output as a data signal S_DATA, the data signal S_DATA and provide data information; or preferably, as shown in FIG. 7, the decoder 450_i can further include a delay logic unit 850, which outputs the output O1 is delayed by a desired phase (e.g., 180°) to generate a data signal S_DATA.

A comparator 820 compares the voltage level of the differential signal SCTRL_i(I) with a predetermined voltage RH to provide the comparison result as an output O2. Similarly, a comparator 830 compares the predetermined voltage RL with the voltage level of the differential signal SCTRL_i(I) to provide a comparison result as an output O3. A OR gate 840 then produces an output O4 based on the outputs O2 and O3. In the case where the delay logic unit 850 is built, the output O4 can be directly used as a clock signal S_CLOCK to provide clock information, or alternatively, in the case where the delay logic unit 850 is not provided, the decoder 450_i can Further included is a delay logic unit (not shown) that delays the output O4 of the OR gate 840 by a desired phase to produce a clock signal S_CLOCK.

Preferably, the decoder 450_i may further include an Enable Input/Output (EIO) generation logic unit 860 to provide an enable input/output signal S_EIO. The enable input/output signal S_EIO can be used to control the output of the decoder 450_i so that the source driver 420_i receives the data signal S_DATA and the clock signal S_CLOCK after decoding for subsequent processing.

In Figure 7, the EIO generation logic unit can be configured to receive the output O1 described above. The EIO logic generating unit 860 can then detect the state mode of the timing control signal SCTRL_i according to the received output O1 during the process of generating the enable input and output signal S_EIO, which will be described in detail below with reference to FIGS. 9A and 9B.

Figure 8 is a schematic illustration of another example decoder of a source driver employing a four-state timing control signal in accordance with another embodiment. In Fig. 8, the source driver 420_i (1) of the 4A and 4B is shown. i m ) decoder 450_i, wherein the source driver 450_i uses a pair of three-level (q1=q2=3) differential signals SCTRL_i(I) and SCTRL_i(Q) as a four-state (total number of states p= 4) The timing control signal SCTRL_i, as shown in Tables 4 and 6. Here, the difference between FIG. 8 and FIG. 7 is mainly that the comparator 830 can be replaced by the comparator 930, and the voltage level of the differential signal SCTRL_i (Q) is compared with the predetermined voltage RH. For the sake of brevity, details similar to those of Fig. 7 are omitted below.

The figures 9A and 9B are respectively a display diagram of an example signal value of a four-state timing control signal according to an embodiment and a waveform diagram of the corresponding representative signal. Here, FIG. 9A shows the state number NUM of one of the four states (ie, the total number of states p=4) in Table 1, the corresponding clock signal value CLOCK and the data signal value DATA, and an input/output signal value EIO. . FIG. 9B shows four-bit quasi-differential signals SCTRL_i(I) and SCTRL_i(Q), clock signal S_CLOCK, and data signal S_DATA corresponding to FIG. 9A in the construction of decoder 450 as shown in FIG. And the waveform of the enable input/output signal S_EIO. As shown, the difference The motion signals SCTRL_i(I) and SCTRL_i(Q) are switched between different states along time, and the clock signal value and the data signal value can be simultaneously transmitted at any time point.

During the period of the enable periods E1 and E2, the state number NUM is switched in the mode of (NUM)=(1 or 4→2 or 3→1 or 4→2 or 3→...), which reflects The clock signal value CLOCK must be converted back and forth between 1 and 0, as described in the relevant description in Table 1.

On the other hand, during the period of one failure period D1, the state number NUM can be set to be switched in a specific state mode, for example (2→3→2→3→2→...), when it is represented The pulse signal value CLOCK is (0→0→0→0→0→...) and the data signal value DATA is (1→0→1→1→1→...). The state mode of the clock signal value CLOCK reflects that when the source driver 420_i is disabled and stops processing the decoded output signals (S_DATA and S_CLOCK), the clock signal value CLOCK must remain at 0, as shown in Table 1. Said in the description. However, the state mode of the data signal value DATA (1→0→1→1→1) comes from another additional requirement for generating the enable input/output signal S_EIO, which is in view of one such as (2→3→2→ The end of the special mode, such as 3→2), can be detected and thus can be used to provide an indication of the end of a disabling period, i.e., as a prompt to enable the source driver 410_i.

For example, the decoder 450_i can be configured to generate an enable input/output signal S_EIO for enabling the source driver 410_i according to the state mode of the timing control signal SCTRL_i. Specifically, during the period of a disability cycle, For example, the period D1, the timing controller can provide a timing control signal having a status number converted by a specific state mode such as (2→3→2→3→2→...). At the same time, the decoder 450_i detects the state mode of the timing control signal for detecting the end of the disable period and the beginning of a subsequent enable period. If the decoding 450_i detects that the status number NUM stops switching in a particular mode, the decoder 450_i may generate a pulse for the enable input/output signal to enable the source driver 410_i. The corresponding implementation is shown in FIG. 7 , wherein the EIO generation logic unit 860 detects the state mode of the timing control signal SCTROL_i after receiving the output O1 to generate the enable input/output signal S_EIO.

In FIG. 9B, the clock signal S_CLOCK and the data signal S_DATA may have a phase difference of about 180°. An implementation corresponding thereto is shown in FIG. 7, in which delay logic unit 850 delays output O1 by the generated data signal S_DATA. For the sake of brevity, similar descriptions of the 3-bit quasi-differential signals as in Tables 4, 6, and 8 are omitted below.

It should be noted that the source drivers 420_1 to 420_m are connected according to a point-to-point structure. However, the source drivers 420_1 through 420_m may be connected in any single point to multipoint configuration.

10A is a schematic diagram of another exemplary display device according to another embodiment, and FIG. 10B is a schematic diagram of still another exemplary display device according to still another embodiment. Here, the 10A and 10B display display devices 1100 and 1100' each employing a single-point to two-dot structure and a single-point to m-dot structure (m is an integer). The main difference between the 10A and 10B and the 4A and 4B is that the amount of data represented by the clock signals generated by the display devices 1100 and 1100' is increased by two times and m times, respectively, so that the clock signal can be increased to indicate that More information. For the sake of brevity, features similar to those of Figures 4A and 4B are omitted from the following.

In the above embodiment, since only a single signal line is disposed between the timing controller and a corresponding source driver, the total number of signal lines and manufacturing cost can be reduced. In addition, since only a single timing control signal is used to carry both clock information and data information, more accurate data sampling can be achieved without additional offset. In addition, since one or more multi-information signal lines can be separately supplied to the source driver, problems such as large signal load, electromagnetic interference, and data sampling failure due to signal delay can be solved, and the result can be provided. Higher transmission speed.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

11‧‧‧clock signal line

12‧‧‧Information signal line

110_1~110_m‧‧‧Source Driver

32_1~32_m‧‧‧clock signal line

32_1~32_m‧‧‧Information signal line

310_1~310_m‧‧‧Source Driver

410‧‧‧Sequence Controller

420_1~420_m‧‧‧Source Driver

430_1~430_n‧‧‧gate driver

450_1~450_n‧‧‧Decoder

810‧‧‧ comparator

820‧‧‧ comparator

830, 930‧‧‧ comparator

840‧‧‧ or gate

850‧‧‧Delay logic unit

860‧‧‧Enable input/output generation logic unit

LM_1~LM_m‧‧‧Multiple signal line

O1-O4‧‧‧ output

RH‧‧‧established voltage

RL‧‧‧established voltage

SCTRL_1~SCTRL_m‧‧‧ timing control signal

SCTRL (I) ‧ ‧ timing control signal

SCTRL (Q)‧‧‧ timing control signal

SD_1~SD_m‧‧‧Information Signal

SS_1~SS_n‧‧‧ scan signal

S_DATA‧‧‧Information Signal

S_EIO‧‧‧Enable input/output signals

S_CLOCK‧‧‧ clock signal

The various features, functions and embodiments of the present invention are described in the foregoing detailed description, 1 is a schematic diagram of a conventional display device using the RSDS standard; FIG. 2 is a schematic diagram of a conventional display device using the mini-LVDS standard; and FIG. 3 is a schematic view of a conventional display device using the PPDS standard; 4B is a schematic diagram of an exemplary display device according to an embodiment; FIG. 5 is a schematic diagram showing a relationship between a display voltage level and two predetermined DC voltages according to an embodiment; FIG. 6 is a diagram according to another embodiment. Schematic diagram showing the relationship between the voltage level and a predetermined DC voltage; FIG. 7 is a schematic diagram of an example decoder using a source driver of a four-state timing control signal according to an embodiment; FIG. 8 is based on another A schematic diagram of an example decoder using a source driver of a four-state timing control signal; and FIGS. 9A and 9B are diagrams showing an example signal value of a four-state timing control signal according to an embodiment; Corresponding waveform diagram of the representative signal; 10A is a schematic diagram of another exemplary display device in accordance with another embodiment; and FIG. 10B is a schematic diagram of still another exemplary display device in accordance with still another embodiment.

410‧‧‧Sequence Controller

420_1~420_m‧‧‧Source Driver

430_1~430_n‧‧‧gate driver

LM_1~LM_m‧‧‧Multiple signal line

SCTRL_1~SCTRL_m‧‧‧ timing control signal

SD_1~SD_m‧‧‧Information Signal

SS_1~SS_n‧‧‧ scan signal

Claims (23)

A liquid crystal display device includes: a display panel; a timing controller that generates a timing control signal, the timing control signal has a plurality of states, each state simultaneously representing data information and clock information, wherein the timing control signal system a single-ended signal having the states, each state having a voltage level different from the other states; and a source driver for receiving and decoding the timing control signal to recover the data information and time Pulse information for generating a clock signal and a data signal to drive the display panel. The display device of claim 1, wherein each state of the timing control signal represents one of a high logic value and a low logic value of the data signal, and further represents one of the clock signals. A logic value between a high logic value and a low logic. The display device of claim 1, wherein the timing control state has four states, including: a first state, which represents a high logic value of one of the data signals and a high logic value of the one of the clock signals; a second state representing a high logic value of the data signal and the clock One of the signals is a low logic value; a third state representing a low logic value of one of the data signals and a low logic value of the one of the clock signals; and a fourth state representing a low logic value of the data signal and One of the clock signals has a high logic value. The display device of claim 1, wherein the timing control signal is a pair of differential signals, and for each state of the timing control signal, one of the differential signals is located in the first plurality One of the current or voltage levels is an individual level, and the other differential signal is at an individual level of the second plurality of current or voltage levels. The display device of claim 4, wherein the number of the first and second plurality of current or voltage levels is three or four. The display device of claim 4, wherein the source driver compares the current or voltage level of the differential signal with at least one predetermined current or voltage level to recover the data information and the clock information. The display device of claim 1, wherein the source driver further decodes the timing control signal to obtain a uniform input/output signal. The display device of claim 7, wherein the source driver controls a state mode of the signal according to the timing to generate the enable input/output signal. The display device of claim 6, wherein the source driver comprises: a first comparator that compares voltage levels of the pair of differential signals to generate a data signal; and a second comparator that compares the a voltage level of the differential signal and a predetermined voltage; a third comparator that compares one of the pair of differential signals with a predetermined voltage; a gate or a second gate The output of the three comparators generates a clock signal. The display device of claim 9 further includes a delay logic unit for delaying the data signal. The display device of claim 9 further includes a delay logic unit to delay the clock signal. The display device of claim 9, wherein the source driver further comprises a uniform input/output logic unit configured to generate a uniform energy input/output signal according to the output of the first comparator to enable the Source driver. A method of communication between a timing controller and a source driver of a display device, including: Generating a timing control signal, the timing control signal has a plurality of states, each state simultaneously representing data information and clock information, wherein the timing control signal is a single-ended signal, and the single-ended signal has the states, each state Having a voltage level different from the other states; and receiving and decoding the timing control signal to recover the data information and the clock information for generating a clock signal and a data signal. The method of claim 13, wherein each state of the timing control signal represents one of a high logic value and a low logic value of the data signal, and further represents one of the clock signals. A logic value between a high logic value and a low logic. The method of claim 13, wherein the timing control state has four states, including: a first state, which represents a high logic value of one of the data signals and a high logic value of the one of the clock signals; a second state, which represents a high logic value of the data signal and a low logic value of one of the clock signals; a third state, which represents a low logic value of one of the data signals and a logic low of one of the clock signals And a fourth state representing a low logic value of the data signal and a high logic value of the one of the clock signals. The method of claim 13, wherein the timing control signal is a pair of differential signals, and for each state of the timing control signal, one of the differential signals is located in the first plurality One of the current or voltage levels is an individual level, and the other differential signal is at an individual level of the second plurality of current or voltage levels. The method of claim 13, wherein the number of the first and second plurality of current or voltage levels is three or four. The method of claim 16, wherein the step of restoring the data information and the clock information comprises comparing a current or voltage level of the differential signal with at least one predetermined current or voltage level. For example, the method of communication of claim 13 further includes decoding the timing control signal to generate a uniform input/output signal. The method of claim 13, wherein the step of generating the enable input/output signal is performed according to a state mode of the timing control signal. A display device includes: a display panel; a timing controller that generates a timing control signal having a plurality of states, each state indicating a high logic value of a data signal supplied to the display panel Logic with one of the low logic values And a value indicating one of a high logic value and a low logic of one of the clock signals supplied to the display panel, and each state has at least one voltage level different from the other states; a plurality of comparisons Configuring to compare the at least one voltage level of the timing signal with at least one predetermined voltage to generate the data signal; or a gate that generates the clock signal according to the output of the plurality of comparators; and a delay A logic unit configured to delay one of the data signal generated by the comparators or the clock signal generated by the OR gate. The display device of claim 21, wherein the timing control signal is a pair of differential signals, and for each state of the timing control signal, one of the differential signals has a first complex number One of the current or voltage levels is used as one of the at least one voltage level, and the other differential signal has one of the second plurality of current or voltage levels. As another voltage level among the at least one voltage level. The display device of claim 21, wherein the number of the first and second plurality of current or voltage levels is three or four.