KR20050018288A - Liquid Crystal Display - Google Patents

Abstract

PURPOSE: An LCD(Liquid Crystal Display) is provided to minimize ripples generated in gray-level voltage and input voltage caused by waveform output from a source driver circuit during data blank time by allowing the source drive circuit to output an intermediate gray-level voltage having an intermediate value of white voltage and black voltage during the blank time. CONSTITUTION: An LCD includes an LCD panel(400), a timing controller(100), a gate driver(200), and a source driver(300). The LCD panel includes a plurality of gate lines and a plurality of data lines. The timing controller provides a video data signal and a timing signal for controlling display of the LCD panel. The gate driver applies a plurality of gate on/off signals to the gate lines of the LCD panel. The source driver converts the video data signal into a corresponding gray-level voltage, inverts the gray-level voltage at a predetermined period and applies the gray-level voltage to the data lines of the LCD panel. The timing controller generates video data corresponding to a voltage between white voltage and black voltage during a blank time period.

Description

Liquid Crystal Display

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device configured to output an intermediate gray level voltage during a data blank time.

In general, a liquid crystal display device applies an electric field to a liquid crystal material having an anisotropic dielectric constant injected between two substrates, and adjusts the intensity of the electric field to control the amount of light transmitted through the substrate, thereby obtaining a display image. Device.

The liquid crystal display includes a liquid crystal panel for displaying an image, a source and gate drive unit for driving the image, a timing controller for providing a data signal and a timing signal for controlling the display of the liquid crystal panel, to the liquid crystal panel; It comprises a backlight for applying a predetermined light.

The source drive unit is composed of a plurality of source drive circuits, and the source drive circuit is a circuit configuration for transferring an image signal applied from the outside to the liquid crystal panel, and includes a shift register, a D / A converter, and a buffer.

In this case, the image signal is applied as a digital signal from the outside, is converted into an analog signal through the D / A converter of the source drive circuit, amplified in the buffer and applied to the data line of the liquid crystal panel.

When the analog data signal is continuously applied to the liquid crystal panel with the same polarity, ionic impurities in the liquid crystal material are precipitated due to the characteristics of the liquid crystal, thereby causing electrical and chemical changes in the pixel electrode and the counter electrode, resulting in reduced luminance or afterimage. In order to prevent this, a driving scheme for periodically inverting the polarity of the analog data signal is adopted, so that the analog data signal is inverted at a predetermined cycle and outputted.

Meanwhile, in the operation of the source drive circuit, there is a blank time section other than a data valid time section for charging a voltage to the pixel electrode of the liquid crystal panel. The section in which no data is input in the liquid crystal display is called blank time.

1 is a waveform diagram illustrating a blank time of a general liquid crystal display device.

In general, the input of the timing controller of the liquid crystal display (LCD) displays a vertical sync signal (Vsync) input in one frame period, a horizontal sync signal (Hsync) in one line cycle, and data input as shown in FIG. 1. There is a data enable signal DE.

When the liquid crystal display is driven at 60 Hz, the vertical synchronization signal Vsync has a frequency of 60 Hz, and when the liquid crystal display has an XGA-class resolution (1024 * 768), the vertical synchronization signal Vsync is high. There are 768 sections in which the horizontal synchronization signal Vsync and the data enable signal DE are simultaneously output in the level section.

Here, after the data of the 768th gate line, which is the end of the frame, is output, a blank time is generated in the liquid crystal panel for a predetermined period until the data of the first gate line of the next frame is output.

1 is a waveform diagram illustrating a signal of a general liquid crystal display device.

As shown in Fig. 1, there are data lead time and blank time at which real data comes out. In the blank time illustrated in FIG. 1, the first blank period TV1 and the vertical sync signal Vsync between the output of the data enable signal DE and the time point at which the vertical sync signal Vsync is converted to a low level are determined. It is the sum of the second blank period TV2 from the time when converted to the low level to the time applied to the first data line of the next frame.

Meanwhile, the data output during the blank time outputs specific data according to the characteristics of the liquid crystal display. In general, during a blank time when no data is input, the source drive circuit outputs a white voltage or a black voltage, or outputs the last data of the data lead time. Here, the white voltage refers to a voltage displayed on the white screen of the liquid crystal panel, and the black voltage refers to a voltage displayed on the black screen of the liquid crystal panel.

2 and 3 are diagrams for explaining an output waveform of a source drive circuit during a blank time in a general liquid crystal display.

2 is a diagram illustrating a case where a white voltage is output during a blank time in a general liquid crystal display.

As shown in Fig. 2, in a normally white liquid crystal, when the black screen is displayed during the data lead time and the white voltage is output during the blank time, a large load of the load at the data bellow time and the blank time is shown. The change causes ripple in the gradation voltage.

FIG. 3 is a diagram illustrating a case in which the last data of the data bead time is output during a blank time in a general liquid crystal display.

As shown in FIG. 3, when the display screen is close to the black screen in the normally white liquid crystal and the last data is the white screen, the white voltage is output during the blank time. Thus, the load and the blank at the data bead time are output. A large change in the load in time causes ripple in the gradation voltage. Generally, the above ripple occurs when the Windows taskbar is set to auto hide on the black display screen.

Accordingly, it is an object of the present invention to output an intermediate gray scale voltage having a middle value between a white voltage and a black voltage from a source drive circuit during a data blank time, so that the gray scale voltage and the input due to the waveform output from the source drive circuit during the blank time. This is to minimize ripple in voltage.

In order to achieve the above object of the present invention, a liquid crystal display device according to an embodiment of the present invention comprises a liquid crystal panel comprising a plurality of gate lines and a plurality of data lines; A timing controller for providing an image data signal and a timing signal for controlling the display of the liquid crystal panel; A gate driver configured to apply a plurality of gate on / off signals to the gate line of the liquid crystal panel; And a source driver for converting the image data signal into a corresponding gray voltage, inverting the image data signal to a predetermined period, and applying the same to the data line of the liquid crystal panel.

Here, the timing controller may check whether there is a blank time period to which the image data signal is not applied, and generate and output image data corresponding to a voltage between a white voltage and a black voltage in the blank time period.

The timing controller preferably generates and outputs image data corresponding to an intermediate voltage between a white voltage and a black voltage in the blank time period.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily implement the present invention.

Hereinafter, an embodiment of the present invention will be described with reference to FIG. 4 is a diagram for describing a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the liquid crystal display according to the exemplary embodiment includes a timing controller 100, a gate drive unit 200, a source drive unit 300, and a liquid crystal panel 400.

The timing controller 100 provides the gate and source drivers 200 and 300 with a timing signal for controlling the data signal and the display of the liquid crystal panel. In detail, the timing controller 100 may include an RGB data signal DATA, a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal from an external graphic controller (not shown). (DE) is input. The timing controller 100 may include a gate selection signal CPV for controlling the output of the gate on / off signal, a vertical synchronization start signal STV for selecting the first gate line, and an output enable signal OE. 200). In addition, the timing controller 100 may control a source signal to control signals such as the RGB data signal DATA, the data transfer direction control signal SHL, the shift clock CLK1, the data latch signal CLK2, and the start pulse DIO1. Supply to 300.

The gate driver 200 receives a gate selection signal CPV and a vertical synchronization start signal STV provided from the timing controller 100, and outputs a plurality of gate on / off signals to the liquid crystal panel 400. Apply sequentially to the gate line.

The source drive unit 300 receives the RGB data signals DATA provided from the timing controller 100, respectively, and converts the RGB data signals DATA into corresponding gray voltages in an internal D / A converter, thereby converting them into liquid crystals. The data is applied to a plurality of data lines configured in the panel 400. The source drive unit 300 is composed of a plurality of source drive circuits (Source Drive IC). Detailed description of the source driving circuit will be described later.

The liquid crystal panel 400 includes a plurality of gate lines and a plurality of data lines that are insulated from and cross the gate lines. As the gate on / off signal provided from the gate driver 200 is applied, the liquid crystal panel 400 displays an image on a corresponding pixel electrode embedded in response to a data voltage provided from the source driver 300.

Next, a source drive circuit according to an embodiment of the present invention will be described with reference to FIG. 5.

5 is a block diagram illustrating a source drive circuit according to an exemplary embodiment of the present invention.

The source drive circuit includes a shift register 310, a data register 320, a latch 330, a D / A converter 340, and an buffer buffer (Out Buffer 350). ).

The shift register 310 receives a start pulse DIO1 indicating a start of operation from the outside, a data transfer direction control signal SHL, a shift clock CLK1, and the like, and sequentially moves the pulses to match the shift clock CLK1. Input data DATA are sequentially stored one by one in the data register 320. It also delivers the pulse output DIO2 to another source drive circuit connected to the right.

The data register 320 sends down the input data according to the operation of the shift register 310 to the latch unit 330 at once when the data storage of one horizontal line is completed.

The latch unit 330 transfers the input image data information to the D / A converter 340 according to the data latch signal CLK2 to be applied.

The D / A converter 340 receives the gray scale voltage VGMA, which is a gray scale voltage, and converts the data signal transmitted from the latch unit into an analog signal of the gray scale voltage.

The buffer unit 350 amplifies the analog data signal from the D / A converter 340 and applies it to the data line of the liquid crystal panel 400. At this time, the analog data signal is inverted based on the common voltage Vcom and outputted according to the polarity of the polarity inversion signal POL.

Here, the timing controller 100 checks whether there is a blank time section to which the RGB data signal is not applied, and outputs image data displayed on the liquid crystal panel to the source driver unit 300 in the data bead time section to which the RGB data is applied. do.

Meanwhile, the timing controller 100 outputs predetermined new RGB data during the blank time period. That is, when the load at the data bead time and the load at the blank time are severe, ripple occurs in the gray voltage and the input voltage as mentioned above. Therefore, the timing controller 100 outputs the image data corresponding to the voltage between the white voltage and the black voltage to the source driver 300 during the blank time period. Preferably, the timing controller 100 generates and outputs image data corresponding to an intermediate voltage between a white voltage and a black voltage in the blank time period.

Here, the timing controller 100 operates by receiving a signal capable of recognizing the blank time from the outside, or recognizes the blank time using an internal signal in the timing controller 100 to generate the RGB data of the new format. This can be achieved by adding an output logic circuit.

For example, by using the start pulse DIO1 of the source drive unit 300 that does not appear at the blank time, a signal capable of recognizing the blank time with the data latch signal CLK2 and the start pulse DIO1 may be generated. have.

6 is a waveform diagram illustrating an output waveform of the source drive unit 300 according to an exemplary embodiment of the present invention.

In the display method of the liquid crystal display device, a normally white mode in which a white screen is displayed when a voltage between liquid crystals is not applied, and a normally black mode in which a black screen is displayed when a voltage is not applied. There is). In general, a normally white mode in which the contrast ratio can be increased and the control margin of the liquid crystal cell thickness is increased is used. Hereinafter, a description will be given based on the normally white method.

As illustrated in FIG. 6, a black voltage is output from the source drive unit 300 during a data lead time in a normally white liquid crystal, and a black screen is displayed on the liquid crystal panel. During the blank time, the timing controller 100 outputs image data corresponding to the intermediate voltage between the white voltage and the black voltage to the source driver 300, and the source driver 300 transmits the corresponding half gray voltage to the liquid crystal panel. Output

That is, during the blank time, the timing controller 100 outputs image data corresponding to the middle of the white voltage and the black voltage to the data register 320 of the source drive circuit. Here, the data register 320 sends down the input intermediate image data to the latch unit 330 at once when the data storage of one horizontal line is completed.

The latch unit 330 transfers the input intermediate image data information to the D / A converter 340 according to the data latch signal CLK2 to be applied. The D / A converter 340 receives the gray scale voltage VGMA, which is a gray scale voltage, and converts the intermediate image data signal transmitted from the latch unit into an analog signal corresponding to the gray scale voltage to output the gray scale voltage.

The buffer unit 350 amplifies the analog data signal from the D / A converter 340 and applies it to the data line of the liquid crystal panel 400. In this case, as shown in FIG. 6, the analog data signal is inverted based on the common voltage Vcom according to the polarity of the polarity inversion signal POL to output the intermediate gray voltage.

Accordingly, it is possible to minimize the change in the load at the data bead time and the load at the blank time, thereby minimizing ripple in the gray voltage and the input voltage.

In each of the embodiments described above, an example in which the present invention is applied to a liquid crystal display device has been described. However, the present invention can be similarly applied to an EL (Electroluminescence) display device or a PDP (Plasma Display Panel).

As mentioned above, although the present invention has been described with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. .

As described above, according to the liquid crystal display device according to the present invention, the source drive unit receives image data corresponding to the middle of the white voltage and the black voltage from the time controller during the blank time, and outputs the corresponding half gray voltage to the liquid crystal panel. In addition, changes in the load at the data bead time and the load at the blank time can be reduced to minimize ripple in the gradation voltage and the input voltage.

1 is a waveform diagram illustrating a signal of a general liquid crystal display device.

FIG. 2 is a diagram for explaining an output waveform of a source drive circuit during a blank time in a general liquid crystal display.

FIG. 3 is a diagram for describing an output waveform of a source drive circuit during a blank time in a general liquid crystal display.

4 is a diagram for describing a liquid crystal display according to an exemplary embodiment of the present invention.

5 is a block diagram illustrating a source drive circuit according to an exemplary embodiment of the present invention.

6 is a waveform diagram illustrating an output waveform of a source drive unit according to an exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

100: timing controller 200: gate drive unit

300: source drive unit 310: shift register

320: data register 330: latch portion

340: D / A converter 350: buffer unit

400: liquid crystal panel

Claims (2)

A liquid crystal panel including a plurality of gate lines and a plurality of data lines; A timing controller for providing an image data signal and a timing signal for controlling the display of the liquid crystal panel; A gate driver configured to apply a plurality of gate on / off signals to the gate line of the liquid crystal panel; And A source driver for converting the image data signal into a corresponding gray voltage, inverting the image data signal at a predetermined period, and applying the same to the data line of the liquid crystal panel; The timing controller, And checking whether there is a blank time section to which the image data signal is not applied, and generating and outputting image data corresponding to a voltage between a white voltage and a black voltage in the blank time section. The method of claim 1, And the timing controller generates and outputs image data corresponding to an intermediate voltage between a white voltage and a black voltage in the blank time period.