GB2340303A - stacked capacitor - Google Patents
stacked capacitor Download PDFInfo
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- GB2340303A GB2340303A GB9817261A GB9817261A GB2340303A GB 2340303 A GB2340303 A GB 2340303A GB 9817261 A GB9817261 A GB 9817261A GB 9817261 A GB9817261 A GB 9817261A GB 2340303 A GB2340303 A GB 2340303A
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- thin film
- dielectric thin
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- 239000003990 capacitor Substances 0.000 title claims description 38
- 238000000034 method Methods 0.000 claims description 72
- 239000010409 thin film Substances 0.000 claims description 34
- 230000004888 barrier function Effects 0.000 claims description 24
- 239000003292 glue Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 16
- 238000005229 chemical vapour deposition Methods 0.000 claims description 11
- 125000006850 spacer group Chemical group 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000004544 sputter deposition Methods 0.000 claims description 8
- 229910010421 TiNx Inorganic materials 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910019311 (Ba,Sr)TiO Inorganic materials 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims 4
- 229910052707 ruthenium Inorganic materials 0.000 claims 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 3
- 229910052721 tungsten Inorganic materials 0.000 claims 3
- 239000010937 tungsten Substances 0.000 claims 3
- 238000000059 patterning Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 239000000463 material Substances 0.000 description 10
- 238000005530 etching Methods 0.000 description 9
- 230000008569 process Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 6
- 238000000137 annealing Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 2
- 229910000457 iridium oxide Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 241000736839 Chara Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- VNSWULZVUKFJHK-UHFFFAOYSA-N [Sr].[Bi] Chemical compound [Sr].[Bi] VNSWULZVUKFJHK-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
- 230000001404 mediated effect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000012421 spiking Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
2340303 CAPACITOR AND METHOD FOR FABRICATING THE SANE
BACKGROUND OF = INVENTION 1. Field of the Invention.
This invention relates to a fabrication of a capacitor in the semiconductor device, and more particularly to the structure and the fabrication of a capacitor in a dynamic random access memory (DRAM) device.
2. Description of Related Art:
For memory devices with high integration such as DRAM devices with memory capacity of 256 Megabit, their capacitor need a dielectric thin film to be constructed as the three dimensional structures like stacked type or trench type. Thus these memory devices should have a large area of the dielectric thin film to store the charge to avoid the soft error. Utilizing, a method of the low pressure chemical vapor deposition (LPCVD), which is one of applications of the chemical vapor deposition (CVD), to make the dielectric thin film made of Ta,O, is popular for the present because this material produces a dielectric constant about 25, which is far larger than that of oxide, and has a better ability of step coverage. The step coverage means that the covering surface is kept in a step shape without being rounded, In the desian of a very large scale integration circuit (VLSI), to increase the capacitance in the integrated circuits (ICs), it has three effective methods. The first is that the thickness of the dielectric thin film mediated between two electrodes is reduced because the capacitance is inversely proportional to the distance between these two elec- 2 trodes. This method can increase the capacitance effectively but is difficult to be controlled to obtain a uniform and stable dielectric thin film. The second method is that the interfacial area between the dielectric thin film and the electrode is increased because the capacitance is proportional to the size of this area. For the present, to increase the size of the interfacial area, such as a fin type or a hemispheric grain type is applied but has a difficulty for massive production due to the complexity of fabrication. Another option is taking a cylindrical type. The third method is that the dielectric constant is increased such as the materials of TaO,, Lead Zirconium Titanate (PZT) composed of Pb(Zr,TI)O,, and Bismuth Strontium Titanate (BST) composed of (Ba,Sr)TiO,, which have high dielectric constant.
In the conventional method of fabricating a semiconductor device, a polysilicon material is usually to be taken for the electrodes of the capacitors. In this case, the higher the temperature is used in the process of annealing on the dielectric thin film, the lesser the defect exists in the dielectric thin film. This means the quality of the dielectric thin film should be better. But, if the temperatures used in the process of annealing is too high, an native oxide is easily produced around the interface between the dielectric thin film and the lower electrode to reduce the capacitance. Here, it doesn't happen around an interface between the dielectric thin film and an upper electrode because the upper interface has not been formed yet. On the contrary, if the temperatures used in the process of annealing is too low, and then the defect existing in the dielectric thin film would not effectively be removed.
Therefore, so far, to prevent the bad situations as described above, a metal layer, generally, is taken instead for the electrodes, which is usually made of a polysilicon layer in the old method. That is to say a metal insulator metal (NffM) capacitor, which is 3 especially applied in a nonvolatile ferroelectric memory (FeR-AM) and a DRAM with high integration.
The metal layer of the NM4 capacitor is usually made of conductive materials such as Platinum, Irldium, Irldium oxide or Ruthenium oxide. Unfortunately, the conventional MIM capacitor usually has a thick lower electrode, on which the etching is complicate and taking time. Except this, it has another problem that because the profile of the pitted contact window is usually steeper, it causes not only the difficulty of the alianment of a source/drain region but also the bad quality of the ability of the step coverage. It is therefore that the filling of a layer of polysillcon and an glue/barrier layer into the pitted contact window should be done before the material for the lower electrode is filled in. This causes the complexity of the fabrication.
FIG. IA through FIG. 1H illustrate the sectional plots of a capacitor of a DRAM in the conventional fabricating procedure. The like marks represent the like elements in the FIGs.
Referring to FIG. l.A, two gates 102 with an identical structure but only one being, marked are shown in the fi aure over a substrate 100 on a substrate surface 10 1. The FIG.
I "D I A further includes a source/drain region I 10 and a commonly used source/drain region I I Oa between the gates 102 under the substrate surface 10 1. One of gates 102 With marks has a doped polysillcon layer 106 covered by a spacer 104 and a cap layer 108. The source/drain region I 10 and the commonly used source/drain region I I Oa are the doped area with a structure of liahtly doped drain (LDD) and can be formed by doing the ion implantation, in which the structure of the gates 102 is treated as the mask. The lightly doped areas, located on the fringe of the source/drain region I 10 and the commonly used source/drain region I 10a with shallower depth, are formed first before the 4 spacer 104 is formed. A slightly heavier doped areas with deeper depth are formed on the central part of the source/drain region I 10 and the commonly used source/drain region I I Oa after the spacer 104 is formed. The spacer 104 typically is made of silicon oide or silicon nitride. After the source/drain region 110 and the commonly used xi 1 1 source/drain region I I Da are fully formed, an insulating layer 112 is formed over the substrate 100 and the gates 102.
Referring FIG. I A and FIG. I B, by utilizing the etching technology, a contact window I I I is defined on the insulating layer 112 to become an insulating layer 112a. The contact window I I I exposes part of the commonly used source/drain region I I Oa.
Referring FIG. I B and FIG. I C, a polysilicon layer 114 preferably made of doped polysilicon by the method of LPCVD is formed over the insulating, layer 112a with the contact window I I I being, filled.
Referring FIG. IC and FIG. ID, by utilizing a process of etch back, the polysibcon layer 114 is etched gradually until the insulating layer 112a has been exposed 0 Z partly. After this procedure the polysilicon layer 114 becomes a polysilicon layer I 14a.
Referring FIG. ID and FIG. IE, an glue/barrier layer 116 preferably made of TiMAIN, respectively, is formed over the polysilicon layer 114a. Then the process of annealing is operated immediately. This process creates a TISI, layer 117 around the interface between the polysilicon layer I I 4a and the glue/barrier layer 116. This process also can enhance the ohmic contact between the polysilicon layer 114a and a lower electrode to reduce the resistance. The lower electrode is to be seen in the next FIGs.
Referrina FIG. IE and FIG. IF, a conductive layer 118 is formed over the glue/barrier layer 116. The conductive layer acts as the lower electrode and is preferably made of one such as Pt, Iridium, Iridium oxide, or Ruthenium oxide by the preferred methods of CVD or sputtering.
Referring FIG. IF and FIG. IG, the lower electrode composed of a conductive layer 118a and an glue/barrier layer 116a as mentioned above is defined on both the conductive layer 118 and glue/barrier layer 116 by the photolithography etching technology.
Referrincy FIG. IG and FIG. IFL over a surface 120a, a dielectric thin film 120 is formed with a thickness about between 10 and 60 Angstrom. The dielectric thin film 120 is preferably made of one having high dielectric constant such as TaO,, PZT or BST.
Then, a conductive layer 128 is formed over the dielectric thin film 120 to be an upper electrode and preferably is made of one such as Pt, Iridium, Iridium oxide or Ruthenium oxide and by the preferred methods of CVD or sputtering, as done for the lower electrode.
The conventional structure of the MIM capacitor in the DR-AM as described above has a number of drawbacks as follows:
1. If the thickness of the lower electrode is too thick for being able to hold more charaes, the etching can not easily be done and cracks can easily happen around the interface between the lower electrode and the dielectric thin film to cause the leakage current.
2. The wall of the pitted contact window, almost vertical to the substrate surface, glue/barrier layer. Further, because the causes the difficulty of the alignment on the ability of step coverage for the metal material is poor, before the lower electrode is 6 made, the polysilicon layer and the glue/barrier layer should be filled in the pitted contact window. This increases the complexity of the fabricating procedure.
3. The conventional NUM capacitors are formed on the insulating layer so that the IC with high integration can not be effectively improved due to the distance between the capacitors can not be effectively reduced. This is because a micro-loading, which is a micro-conducting-path, can easily happen between the conventional NfIM capacitors if the capacitors are too close.
SUMMARY OF THE INVENTION
It is therefore an objective of this present invention to provide a capacitor having a structure including a number of structured gates, a commonly used source/drain region and a source/drain region on a substrate. Then, applying the fabricating procedure of self align contact (SAC) on an insulating layer, which is over the substrate, to form a pitted self align contact window (PSACW) and allow the commonly used source/drain region to be partly exposed. Next, the PSACW is orderly filled with an lue/barrier 1P 9 layer and a first-conductive-layer. The first-conductive-layer is to be the lower electrode of the capacitor. Next, a dielectric thin film is over the first-conductive-layer. Then a second-conductive-layer, which is to be an upper electrode of the capacitor, is over the dielectric thin film to form an NDM capacitor of the invention, in which the pitted structure results in a concave structure so as to behave as a function of barrier between the adjacent invented MIM capacitors.
In conclusion, the invention has a number of advantages as follows:
1. The invented NUM capacitors are utilizing the structure of the PSACW so that there are barriers between the invented MIM capacitors to solve the mi- 7 cro-loading problem, as mentioned above, and allow the distance between them, possibly, to be reduced.
2. The invention utilizes the procedure of SAC for forming a PSACW so that the etching is easier to be done and the fabricating procedure is simplified. In addition, the invented MIM capacitor has a larger dielectric area due to the PSACW having a slanted side wafl, which has the larger dielectric area than a vertical wall in the conventional NID4 capacitor.
3. The invention utilizes materials of Ti/TiNx for forming the glue/barrier layer, in which the technology is conventional and should not cause the extra difficulty.
4. The invention utilizes a preferred material of one such as WN, Pt, Ru02, or others with the similar properties to make the lower electrode to avoid the oxidation happening on the TiNx at a high temperature environment generally required by the fabricating procedure.
5. The invention has the lower electrode with much thinner than that of a conventional one so that the etching is easier to be operated and the cracks around the interface between the lower electrode and the dielectric thin film are comparatively prevented. The cracks are easily happened in the conventional NffM capacitors and induce the problem of leakage current.
6. The invention utilizes the metal layer preferably made of Ti to contact with the source/drain region in the process of Self Aligned Silicide (Salicide) so that a SiNx layer is formed automatically around the contact place to enhance the ohmic contact and reduce the resistance.
8 7. The invention utilizes the fabricating procedure which is compatible with currently available fabricating procedure butTor constructing the MIM capacitor of the invention. Therefore, it is easy to modify the conventional fabricating procedure to achieve the production the N41M capacitor of the invention. That is to say that the investors, based on the old available fabricating equipment, need not much effort to achieve the production of the invented MIM capacitor.
BRIEF DESCRIPTION OF DRAWINGS
The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
FIG. IA through FIG. IH illustrate the sectional plots of a capacitor of a DR-AM in the conventional fabricating procedure; and FIG. 2A throuah FIG. 2F illustrate the sectional plots of a capacitor of a DRAM 01 in the fabricating procedure according to the preferred embodiments of the invention.
DETAMED DESCRIPTION OF PREFERRED EN[BODITVMNT
FIG. 2A through FIG. IF illustrate the sectional plots of a capacitor of a DRAM in the fabricating procedure according to the preferred embodiments of the invention. The like marks represent the like elements in the FIGs.
Referring., to 2A, two gates 202 with an identical structure but only one being marked are shown in the figure over a substrate 200 on a substrate surface 201. The FIG. 2A further includes a source/drain region 210 and a commonly used source/drain 9 region 210a between the gates 202 under the substrate surface 201. One of gates 202 with marks has a doped polysilicon layer 206 covered by a spacer 204 and a cap layer 208. The source/drain region 210 and commonly used source/drain region 210a are the doped area with a structure of lightly doped drain (LDD) and can be formed by doing the ion implantation, in which the structure of the gates 202 is treated as the mask. A number of lightly doped areas, located on the fringe of the source/drain region 210 and the commonly used source/drain region 210a with shallower depth, are formed first before the spacer 204 is formed. The slightly heavier doped areas with deeper depth are formed on the central part of the source/drain region 210 and the commonly used source/drain region 210a after the spacer 204 is formed. The spacer 204 typically is made of silicon oxide or silicon nitride. After the source/drain region 210 and the commonly used source/drain region 21 Oa are fully formed, an insulating layer 212 is formed over the substrate 200 and the gates 202. The insulating layer 212 can be made by the method of APCVD to include Boron-Phosphpho-Silicate-Glass (BPSG) or Tera-EthlyOrtho-Silicate (TEOS) silicon dioxide.
Referring to FIG. 2A and FIG. 2B, by utilizing a technology of self align contact (SAC), a PSACW 211 is defined on the insulating layer 212, which becomes an insu- lating layer 212a. The advantages of using the technolo y of SAC to make the PSACW 9 211 are that the etching can be done more easily and fabricating procedure is more simplified. In addition, the slanted side wall, which is to be seen in the next FIGs, of the PSACW 211 has a larger area than the area in the conventional one, which is the periphery of the contact window I I I as shown in FIG. IH. Thus, the PSACW can store more charges.
Referring to FIG. 2B and FIG. 2C, a metal layer of Ti 215 is formed over the insulating layer 212a including the slanted side wall 213 of the PSACW 211, and the commonly used source/drain region 210a. Then a TiNx layer 216 is formed over the metal layer of Ti 215, The method of sputtering is the preferred to deposit and form these two layers 215, 216. Thus, the glue/barrier layer can improve the contact quality with a conductive layer. The conductive layer is to be formed in the next procedure. These two layers can avoid the spiking. The materials of Ti/TiNx for forming the glue/barrier layer are the conventional technology so that it should not cause the extra difficulty.
Referring to FIG. 2C and FIG. 2D, the FIG. 2D is the subsequent procedure. The conductive layer 218, as mentioned in the previous FIG., is formed over the SiNx layer 216 to be the lower electrode. The preferred method to form the conductive layer 218 is using sputtering method to deposit a material such as WN, Pt, Ru02, or others with the similar properties. This is because the oxidation of the SiNx layer 216 can happen when the temperature is higher than 400'C, which is generally environment during the fabricating procedure. Moreover, the PSACW has much more surface area for the slanted side wall 213 than the conventional one, the surface 120a on the lower electrode I I 8a as shown in FIG. lH. Thus, the thickness of the conductive layer 218 is not necessary to be kept thick so that the etching is easier to be done and the cracks around the interface between the conductive layer 218 and a dielectric thin film are effectively prevented to reduce the leakage current. The dielectric thin film is to be introduced in FIG. 2F.
Referrina to FIG. 2D and FIG. 2E, the FIG. 2E is the subsequent procedure. Using the technology of etching to define the glue/barrier layer 215a/216a and the conductive C) layer 218a on the Crlue/barrier layer 215/216 and the conductive layer 218 to be treated as the lower electrode of the MIM capacitcr of the invention.
Referring to FIG. 2E and FIG. 2F, a dielectric thin film 220 is formed over a Surface 220a with a thickness about between 10 and 60 Angstrom. The dielectric thin film 220 preferably includes a material with high dielectric constant such as Ta,,0,, PZT, BST or others with similar properties by using the preferred method of CVD. The temperature during the operation of the CVD is usually high enough to produce a silicide such as a TISI, layer 217, which is around the interface between the commonly used source/drain region 210a and the glue/barrier layer 215a to increase the ohmic contact and reduce the resistance on the PSACW 211. Then a conductive layer 228 is formed over the dielectric thin film 220 to be an upper electrode of the Nffm capacitor of the invention. The preferred method to form the conductive layer 228 is using sputtering method to deposit a material such as WN, Pt, Ru02, or others with the similar properties.
The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims (1)
12 CLAIMS
1. A method of fabricating a capacitor, comprising:
providing a substrate, wherein at least a gate and at least a source/drain region is formed on the substrate, and wherein a spacer is formed at a periphery of the gate and a cap layer is formed at a top of the gate-, forming an insulating layer over the substrate to at least cover the gate and the source/drain region; patterning the insulating layer to form an opening which expose the source/drain region, wherein the opening has a side wall, forming an gluelbarrier layer on the side wall and coupled to the source/drain region; forming a first conductive layer on the glue/barrier layer to act as a lower electrode; forming a dielectric thin film on the first conductive layer; and forming a second conductive layer on the dielectric thin film to act as an upper electrode.
2. The fabricating procedure of claim 1, wherein the spacer of said step of forming the gates includes a method of chemical vapor deposition (CVD).
The fabricating procedure of claim 1, wherein the spacer of said step of forming the gates include silicon nitride.
4. The fabricating procedure of claim 1, wherein the opening is defined by a technolozv of self alicrn contact (SAC).
5. The fabricating procedure of claim 1, wherein the cap layers of said step of forming the gates are formed including a method of CVD.
01 0 13 6. The fabricating procedure of claim 1, wherein the cap layers of said step of forming the gates include silicon nitride.
7. The fabricatin'c, procedure of claim 1, wherein the insulating layer is formed in- Z., cludinc, the method of CVD.
8. The fabricating, procedure of claim 1, wherein the insulating layer includes sill- Z con oxide.
9. The fabricating procedure of claim 1, wherein the clue/barrier layer is formed including, a method of sputtering.
10. The fabricating procedure of claim 1, wherein the glue/barrier layer includes Ti/TiNx.
11. The fabricating procedure of claim 1, wherein the first conductive layer is formed including a method of sputtering.
12. The fabricating procedure of claim 1, wherein the first conductive layer includes Tungsten (W).
13. The fabricating procedure of claim 1, wherein the first conductive layer in- Z.) cludes Platinum (Pt).
14. The fabricating, procedure of claim 1, wherein the first conductive layer includes Ruthenium (Ru).
15. The fabricating procedure of claim 1, wherein during the dielectric thin film beinc, formed, a TISI, layer is formed around an interface between the at least a commonly used source/drain region and the glue/barrier layer.
16. The fabricating procedure of claim 1, wherein the dielectric thin film is formed including, the method of CVD.
I 14 17. The fabricating procedure of claim 1, wherein the dielectric thin film includes Ta,05.
18. The fabricating procedure of claim 1, wherein the dielectric thin film includes Pb(Zr,T1)03 (PZT).
19. The fabricating procedure of claim 1, wherein the dielectric thin film includes (Ba,Sr)TiO, (BST).
20. The fabricating procedure of claim 1, wherein the second conductive layer is formed including the method of sputtering.
21. The fabricating procedure of claim 1, wherein the second conductive layer includes Tungsten.
22. The fabricating, procedure of claim 1, wherein the second conductive layer includes Platinum.
2'). The fabricating, procedure of claim 1, wherein the second conductive layer includes Ruthenium, 24. A capacitor, comprising:
a substrate, wherein a transistor having at least a gate and a source/drain layer is formed on the substrate; an insulating layer over at least the transistor, wherein there is an opening through the insulating layer exposing the source/drain region and wherein the opening has a side wall-, a first metal layer covering the side wall of the opening and coupled to the ID 0 source/drain region, wherein the first metal layer serves as a lower electrode of the capacitor', a dielectric layer covering the first metal layer; and a second metal layer covering the dielectric layer, wherein the second dielectric layer serves as an upper electrode of the capacitor.
25. The structure of claim 24, wherein the insulating layer includes silicon oxide.
26. The structure of claim 24, wherein the opening includes a self align contact (SAC) window.
27. The structure of claim 24, wherein the first metal layer includes Tungsten (W).
28. The structure of claim 24, wherein the first metal layer includes Platinum (Pt).
29. The structure of claim 24, wherein the first metal layer includes Ruthenium (Ru).
30. The structure of claim 24, wherein the dielectric thin film includes TaO,.
31. The structure of claim 24, wherein the dielectric thin film includes Pb(Zr,TI)03 (PZT).
32. The structure of claim 24, wherein the dielectric thin film includes (Ba,Sr)T'03 (BST).
33. The structure of claim 24, wherein the second metal layer includes Tunasten.
34. The structure of claim 24, wherein the second metal layer includes Platinum.
35. The structure of claim 24, wherein the second metal layer includes Ruthenium.
36. The structure of claim 24, wherein an glue/barrier layer is included between the first metal layer and the slanted side wall of the opening.
37. The fabricating procedure of claim 36, wherein the glue/barrier layer includes Ti/TiNx.
_38. The fabricating procedure of claim 36, wherein a TISI, layer is formed around the interface between the commonly used source/drain region and the glue/barrier layer.
16 39. A method of fabricating a capacitor, substantially as hereinbef ore described with reference to and/or substantially as illustrated in any one of or any combination of Figs. 2A to 2F of the accompanying drawings.
40. A capacitor substantially as hereinbefore described with reference to and/or substantially as illustrated in any one of or any combination of Figs. 2A to 2F of the accompanying drawings.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9817261A GB2340303B (en) | 1998-08-07 | 1998-08-07 | Capacitor and method for fabricating the same |
| NL1009940A NL1009940C2 (en) | 1998-08-07 | 1998-08-25 | Capacitor and method for its manufacture. |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9817261A GB2340303B (en) | 1998-08-07 | 1998-08-07 | Capacitor and method for fabricating the same |
| NL1009940A NL1009940C2 (en) | 1998-08-07 | 1998-08-25 | Capacitor and method for its manufacture. |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9817261D0 GB9817261D0 (en) | 1998-10-07 |
| GB2340303A true GB2340303A (en) | 2000-02-16 |
| GB2340303B GB2340303B (en) | 2000-12-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9817261A Expired - Fee Related GB2340303B (en) | 1998-08-07 | 1998-08-07 | Capacitor and method for fabricating the same |
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| Country | Link |
|---|---|
| GB (1) | GB2340303B (en) |
| NL (1) | NL1009940C2 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0494313A1 (en) * | 1990-07-24 | 1992-07-15 | Seiko Epson Corporation | Semiconductor device provided with ferroelectric material |
| US5142438A (en) * | 1991-11-15 | 1992-08-25 | Micron Technology, Inc. | Dram cell having a stacked capacitor with a tantalum lower plate, a tantalum oxide dielectric layer, and a silicide buried contact |
| US5391511A (en) * | 1992-02-19 | 1995-02-21 | Micron Technology, Inc. | Semiconductor processing method of producing an isolated polysilicon lined cavity and a method of forming a capacitor |
| US5396094A (en) * | 1990-11-09 | 1995-03-07 | Matsushita Electric Industrial Co. Ltd. | Semiconductor memory device with a capacitor having a protection layer |
| US5501998A (en) * | 1994-04-26 | 1996-03-26 | Industrial Technology Research Institution | Method for fabricating dynamic random access memory cells having vertical sidewall stacked storage capacitors |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6089970A (en) * | 1983-10-21 | 1985-05-20 | Nec Kansai Ltd | Semiconductor device |
| JP2897631B2 (en) * | 1993-12-28 | 1999-05-31 | 日本電気株式会社 | Semiconductor integrated circuit device and manufacturing method |
| US5691219A (en) * | 1994-09-17 | 1997-11-25 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor memory device |
| US5686337A (en) * | 1996-01-11 | 1997-11-11 | Vanguard International Semiconductor Corporation | Method for fabricating stacked capacitors in a DRAM cell |
| KR100215867B1 (en) * | 1996-04-12 | 1999-08-16 | 구본준 | Capacitor of semiconductor device and its fabrication method |
-
1998
- 1998-08-07 GB GB9817261A patent/GB2340303B/en not_active Expired - Fee Related
- 1998-08-25 NL NL1009940A patent/NL1009940C2/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0494313A1 (en) * | 1990-07-24 | 1992-07-15 | Seiko Epson Corporation | Semiconductor device provided with ferroelectric material |
| US5396094A (en) * | 1990-11-09 | 1995-03-07 | Matsushita Electric Industrial Co. Ltd. | Semiconductor memory device with a capacitor having a protection layer |
| US5142438A (en) * | 1991-11-15 | 1992-08-25 | Micron Technology, Inc. | Dram cell having a stacked capacitor with a tantalum lower plate, a tantalum oxide dielectric layer, and a silicide buried contact |
| US5391511A (en) * | 1992-02-19 | 1995-02-21 | Micron Technology, Inc. | Semiconductor processing method of producing an isolated polysilicon lined cavity and a method of forming a capacitor |
| US5501998A (en) * | 1994-04-26 | 1996-03-26 | Industrial Technology Research Institution | Method for fabricating dynamic random access memory cells having vertical sidewall stacked storage capacitors |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2340303B (en) | 2000-12-27 |
| NL1009940C2 (en) | 2000-02-29 |
| GB9817261D0 (en) | 1998-10-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20060807 |