GB2339337A - Semiconductor device mounting in recesses in a circuit board - Google Patents

Semiconductor device mounting in recesses in a circuit board Download PDF

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Publication number
GB2339337A
GB2339337A GB9924164A GB9924164A GB2339337A GB 2339337 A GB2339337 A GB 2339337A GB 9924164 A GB9924164 A GB 9924164A GB 9924164 A GB9924164 A GB 9924164A GB 2339337 A GB2339337 A GB 2339337A
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United Kingdom
Prior art keywords
recesses
chip module
wiring board
semiconductor device
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9924164A
Other versions
GB9924164D0 (en
GB2339337B (en
Inventor
Hirotsugu Shirakawa
Yasunori Tanaka
Tsunenobu Kouda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
Priority claimed from JP7150467A external-priority patent/JP3014029B2/en
Application filed by NEC Corp filed Critical NEC Corp
Publication of GB9924164D0 publication Critical patent/GB9924164D0/en
Publication of GB2339337A publication Critical patent/GB2339337A/en
Application granted granted Critical
Publication of GB2339337B publication Critical patent/GB2339337B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2224/45001—Core members of the connector
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H01L2224/4805—Shape
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    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/181—Encapsulation

Description

I 2339337 SENfICONDUCTOR DEVICE MOUNTING M=OD AND MULTI-= MODULE PRODUCED
BY THE SANE The present invention 'relates to a method of mounting a semiconductor. device, and a multi-chip module produced by the same.
A laminate wiring board. formed with recesses has been proposed in various forms in the past- For example, Japanese Patent Laid-Open PubUcatlorj2 No. 64-57653 teaches a laminate wining board formed with recesses such that the electrodes of each part and the conductor pattern of the, 1 0 wiring board are flush with each other. This Idnd of configuration minimizes the distance of connection and is adapted for composite IC (InEegrated Circuit) parts.
Japanese Patent Laid-Open Publication No. 1-258446 discloses a laminate thick film wiring board formed - vviE 1 5 recesses for receiving chips. This kind of coafigur-ation is adapted for composite ICs.
Japanese Patent Laid-Open Publication No. 4-359462 discloses a composite IC device formed with recesses in order to protect semiconductor devices fro m contamination and deterioration due to flux. The recesses are sealed with sealing members.
Japanese Patent Laid-Open Publication No. 7-30059 prcrposes a multi-chip module having semiconductor devices mounted in the recesses of a laminate, wiring board, and packaged semiconductor devices each being mounted over the respective semiconductor device. With this configuration, it is possible to implement a dease and miniature multi-chip module. The recesses and bare-chip semiconductor devices 1 0 buried in the recesses promote high integration and miniaturization because the area of the wiring board is determined by the area and number of surface mounting parts a.s represented by packaged semiconductor devices, However, this document does not show or describe how it produces such 1 5 a module or how it reduces the thickness of the module specific-ally.
The conventional laminate wiring boards of the kind described above have the following problems left unsolved.
The recesses are formed in the wiring board in order to 2 0 reduce the mounting area, and the bare-chip semiconductor devices are received in the recesses. The prerequisite with this scheme is that resin sealing the recesses should be previented.
from protruding frorn the top of the wiring board. This requires - the recesses to have a substantial depth and thereby 2 5 obstr-ucts the reduction of the thickness of the wiring board.
Furthermore, to allow each packaged semiconductor device to be mounted while straddling the respective recess, it is necessary to reduce the area of each recess.
It is therefore an object of at least the preferred embodiments of the present invention to provide a highly integrated, diin and lightweight multi-chip module, and a method of mounting a semiconductor device for producing such a module.
A first aspect of the present invention provides a method of mounting a semiconductor device on a laminate wiring board, comprising the steps of:
(a) forming a recess or a through hole in said laminate wiring board, said recess or said through hole being formed with a stepped configuration; (b) mounting said device in said recess or through hole; (c) performing wire bonding of said device to said wiring board; and, (d) sealing said recess or said through hole with sealing resin.
Preferably, the recess or through hole is sealed using a screen printing technique employing a mesh screen. The mesh screen preferably has a relatively large aperture ratio and a relatively small thickness. Preferably, electrodes are formed on the wiring board using a non-electrolytic gold plating technique. The stepped recess or through hole preferably comprises a relatively wider portion and a relatively narrower portion, the electrodes being formed in the relatively wider portion. The electrodes are preferably spaced from the side walls of the relatively narrower portion of the recess or through hole. The stepped recess or through hole preferably comprises a relatively wider portion and a relatively narrower portion, and said relatively narrower portion is preferably formed with a depth greater than a thickness of the semiconductor device.
In a preferred embodiment of the first aspect of the present invention, a method of mounting a semiconductor device on a laminate wiring board has the steps of (a) forming a recess or a through hole in the laminate wiring board, and (b) sealing the recess or the through hole with sealing resin. The step (b) has the steps of (c) providing the recess or the through hole with a stepped configuration, and performing screen printing using a mesh screen having a relatively great aperture ratio and a relatively small thickness, and (d) performing wire bonding as short in distance and as low in loop as possible.
A second aspect of the present invention provides a multi-chip module comprising:
a plurality of semiconductor devices; and, a laminate wiring board; wherein said laminate wiring board has a plurality of recesses or through holes having a stepped configuration, and wherein each of said plurality of semiconductor devices is mounted in a respective recess or through hole and sealed therein.
Preferably, each of the plurality of stepped recesses or through holes comprises a relatively wider portion and a relatively narrower portion, and the relatively narrower portion has a depth greater than a thickness of the semicon ductor device. Each of said plurality of stepped recesses or through holes preferably comprises a relatively wider portion and a relatively narrower portion, said module preferably further comprising electrodes disposed in the relatively wider portion of each of the plurality of recesses or through holes. The electrodes are preferably spaced from the side walls of the relatively narrow portion.
The multi-chip module preferably also comprises a plurality of devices mounted on the surface of the module. The recesses or through holes are preferably sealed with resin.
A third aspect of the present invention provides a multi-chip module comprising:
a plurality of surface mounting parts; a plurality of bare-chip semiconductor devices; and a laminate wiring board; wherein said wiring board has a plurality of recesses or through holes, and wherein each of saidplurality of semiconductor devices is mounted in a respective recess or through hole and sealed therein.
Each of the recesses or through holes preferably has a stepped configuration, each of said plurality of stepped recesses or through holes comprising a relatively wider portion and a relatively narrower portion, said relatively narrower portion having a depth greater than a thickness of the semiconductor device.
In a preferred embodiment of the third aspect of the present invention, a multi-chip module has a plurality of surface mounting parts as represented by packaged semiconductor devices, a plurality of bare-chip semiconductor devices, and a laminate wiring board. The laminate wiring board is formed with a plurality of recesses. The plurality of bare-chip semiconductor devices are each mounted in the respective recess and sealed by resin.
In another preferred embodiment of the third aspect of the present invention, a multi-chip module has a plurality of surface mounting parts as represented by packaged semiconductor devices, a plurality of bare-chip semiconductor devices, and a laminate wiring board. The wiring board is formed with a plurality of through holes. The plurality of bare chips are each mounted in the respective recess and sealed therein.
Preferred features of the present invention will now be described, purely by way of example only, with reference to the accompanying drawings, in which:
FIG. I is a vertical section showing a multi-chip module embodying the present invention; FIG. 2 is a vertical section showing an alternative embodiment of the present invention; and FIG. 3 is a vertical section showing another alternative embodiment of the present invention.
Referring to FIG. 1 of the drawings, a multi-chip module embodying the present invention is shown. In FIG. 1, a packaged semiconductor device I is shown as being spaced above a laminate wiring board 3 in a Particular assembly stage. The wiring board 3 is formed with a plurality of stepped recesses 8 (only one is shown). The stepped recesses 9 each has a lower layer afid an upper layer. A bare-chip semiconductor device 2 is affixed to the wiring board 3 by adhesive 7 in the lower layer of each recess S. Electrodes 5 provided on the upper layer of the recess 8 of the wiring board 3 are connected to the electrodes of the semiconductor device 2.
The electrodes 5. of the wiring board 3 are subjected to acn-electrolytic gold plating for the following reasons.
Electrolytic plating would cause the electrodes 5 to protrude fram. the side walls of the recess 8 and might cause them to contact the side edges of the semiconductor device 2, resulting in short-circuiting. If sufficient distaaces were providcd between the side walls of the recess 8 and those of the semiconductor device 2 in order to avoid the above short-circuitina, the area of the recess 8 would be ur) desirably increas.ed.
The method--by which this preferred arbodiment of, the present invention mounts the seTdcaxJuctor devices 1 and 2 will be described with reference to FIG. 1. FIrst, the bare-chip semiconductor device 2 is mamted in the lower layer of the recess S. Then, the electrodes of the semiconductor device 2 and the electrodes 5 of the wi-rina 0 board 3 are connected together by wire bonding using gold, co.pper or aluminum wires 6.
The semiconductor device 2 mounted in the recess 8 is sealed by insulating resin 4. For example, assume that the packaged semiconductor device I is a TSOP or a TQFP package whose mounting height is limited to 1.27 mm. Then, the distance between the bottom of the semi-conductor device I and the top of the wiring board 3 is limited to 0.05 0.05 mra.
In this condition, it is quite likely that the bottom of the semiconductor device I contacts the top of the wiring board 3.
If the insulating resin 4 sealing the recess 8 protrudes from the top of the wiring board 3, it will contact the bottom of the semiconductor device I and will thereby raise leads 1 5 away ftom lands provided an the wiring board 3, resulting in defective solderiag. In light of this, the illustr-ative crnbodicaear uses screen printing for the purpose of feeding the resin 4 in a presclected constant amount. To promote the smooth delivery of the resin 4, use is made of a screen mesh having a large aperture ratio. The mesh screen should preferably be as thin as possible in order to realize a sealtrig height of less than 50 wm.
To effectively use the wiring board 3, the packaged semiconductor device I or similar comparatively large sized 2 5 part is mounted on the wiring board 3 in such a manner as to straddle the recess 8. In this sense, the area of the recess 8 should preferably be smail, as s tate-d earlier. Becausethe area of the recess 8 cannot be decreased below the area of the semiconductor device 2, implementing short distan ce, low loop banding is irnpor=t. In the illustrative embodiment, t h e Jayer of the %iring board 3 in which the electrodes 5 are formed is, positioned about 10 gm. higher in level than the electrode plane of the semiconductor device 2. This successfully reduces the distance of connection.
1 0 Fl Cr. 3 shows a second embodiment of the present invention. As shown, with the state-of-the-art bonding technologies, lower loop bonding is achievable when the electrode plane of the semiconductor device 2 is increased -in height. The rest of the configuration is identical with the 1 5 embodiment shown in FIG. 1.
FIG. 2 shows another alternative embodiment of the present invention similar to the foregoing embodiments except for the following. As shown, when the laminate wiring board 3 is too thin to form the stepped recess, the stepped 2 0 recess is replaced with a through hole 9. In this embodiment, the adhesive 7 of the previous embodiments is replaced with vacuum sucrion. Specifically, to affix the semiconductor device 2 to the wiring boazd 3, the device is sucked fro rn below. The rest of the coafiguradon is identical with the 2 5 embodL"Merlt shown in FIG. 1.
8 In summary, in accordance with the present invention, a laminate wiring board is formed with stepped recesses. Electrodes to be connected to the electrodes of a bare-chip semiconductor device are subjected to non-electrolytic gold plating. This realizes wire bonding which is as short in distance and as low in loop as possible.
To seal each recess with insulating resin, use is made of the screen printing using a 0 C2 mesh screen which has a large aperture ratio and a small thickness. Therefore, each recess can have its depth and size respectively limited to about +200 gm and about +4 mm which are the thickness and size of the chip. That is, dimensions for mountin a packaaed semiconductor device, whith is one of surface mounting parts occupying comparatively broad areas, in a laminated wiring board as a bare-chip semiconductor device can be defined. As a result, the laminate wiring board is reduced in size and thickness.
- It will be understood that the present invention has been described above purely by way of example, and modifications of detail can be made within the scope of the invention.
Each feature disclosed in the description, and (where appropriate) the claims and drawings may be provided independently or in any appropriate combination.
t

Claims (11)

-9CLAIMS:
1. A multi-chip module comprising: a plurality of surface mounting parts; a plurality of bare-chip semiconductor devices; and, a laminate wiring board; wherein said wiring board has a plurality of recesses or through holes, and wherein each of said plurality of semiconductor devices is mounted in a respective recess or through hole and sealed therein.
2. A multi-chip module according to Claim 1, wherein each of said recesses or through holes has a stepped configuration.
3. A multi-chip module according to Claim I or Claim 2, wherein each of said recesses or through holes has a stepped configuration, each of said plurality of stepped recesses or through holes comprising a relatively wider portion and a relatively narrower portion, said relatively narrower portion having a depth greater than a thickness of said semiconductor device.
4. A multi-chip module according to any one of the preceding claims, wherein each of said recesses or through holes comprises a relatively wider portion and a relatively narrower portion, and wherein said module hirther comprises electrodes disposed in said relatively wider portion of each of said recesses or through holes.
5. A multi-chip module according to Claim 4, wherein said electrodes are spaced from the side walls of said relatively narrower portion.
6. A multi-chip module according to a:ny one of the preceding claims, wherein each of said plurality of bare-chip semiconductor devices is sealed in a respective recess or through hole with sealing resin.
7. A multi-chip module according to Claim 6, wherein the height of sealing resin protruding from above the board is less than 50 /irn.
8. A multi-chip module according to any one of Claims 4 to 7, wherein each said relatively narrower portion of the recesses or through holes is formed with a depth greater than a thickness of said semiconductor devices.
9. A multi-chip module according to any one of the preceding claims, wherein said recess or through hole has its depth and size limited to about 200 gm. and about 4 mm, respectively.
10. A multi-chip module substantially as herein described with reference to and as shown in the accompanying drawings.
11. A method of mounting a semiconductor device on a laminate wiring i board substantially as herein described with reference to the accompanying drawings.
GB9924164A 1995-06-16 1996-06-17 Semiconductor device mounting method and multi-chip module produced by the same Expired - Fee Related GB2339337B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7150467A JP3014029B2 (en) 1995-06-16 1995-06-16 Semiconductor element mounting method
GB9612613A GB2302451B (en) 1995-06-16 1996-06-17 Semiconductor device mounting method and multi-chip module produced by the same

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GB9924164D0 GB9924164D0 (en) 1999-12-15
GB2339337A true GB2339337A (en) 2000-01-19
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2370421A (en) * 2000-12-22 2002-06-26 Ubinetics Printed circuit board with recessed component

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JPS57143848A (en) * 1981-02-27 1982-09-06 Nec Corp Semiconductor device
GB2199182A (en) * 1986-12-18 1988-06-29 Marconi Electronic Devices Multilayer circuit arrangement
US4943844A (en) * 1985-11-22 1990-07-24 Texas Instruments Incorporated High-density package
JPH04359462A (en) * 1991-06-05 1992-12-11 Toyota Motor Corp Hybrid integrated circuit device
JPH0730059A (en) * 1993-06-24 1995-01-31 Nec Corp Multichip module
WO1995003683A1 (en) * 1993-07-19 1995-02-02 Oakleigh Systems, Inc. Space-saving memory module
JPH0778935A (en) * 1993-09-08 1995-03-20 Toyota Autom Loom Works Ltd Hybrid integrated circuit device
EP0645953A1 (en) * 1993-09-29 1995-03-29 Siemens NV Method of producing a two or multilayer wiring structure and two or multilayer structure made thereof
WO1996004681A1 (en) * 1994-07-29 1996-02-15 Havant International Limited Direct chip attach

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Publication number Priority date Publication date Assignee Title
JPS57143848A (en) * 1981-02-27 1982-09-06 Nec Corp Semiconductor device
US4943844A (en) * 1985-11-22 1990-07-24 Texas Instruments Incorporated High-density package
GB2199182A (en) * 1986-12-18 1988-06-29 Marconi Electronic Devices Multilayer circuit arrangement
JPH04359462A (en) * 1991-06-05 1992-12-11 Toyota Motor Corp Hybrid integrated circuit device
JPH0730059A (en) * 1993-06-24 1995-01-31 Nec Corp Multichip module
WO1995003683A1 (en) * 1993-07-19 1995-02-02 Oakleigh Systems, Inc. Space-saving memory module
JPH0778935A (en) * 1993-09-08 1995-03-20 Toyota Autom Loom Works Ltd Hybrid integrated circuit device
EP0645953A1 (en) * 1993-09-29 1995-03-29 Siemens NV Method of producing a two or multilayer wiring structure and two or multilayer structure made thereof
WO1996004681A1 (en) * 1994-07-29 1996-02-15 Havant International Limited Direct chip attach

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2370421A (en) * 2000-12-22 2002-06-26 Ubinetics Printed circuit board with recessed component

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GB9924164D0 (en) 1999-12-15
GB2339337B (en) 2000-03-01

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