GB2320130A - Self-aligned silicide manufacturing method - Google Patents
Self-aligned silicide manufacturing method Download PDFInfo
- Publication number
- GB2320130A GB2320130A GB9625173A GB9625173A GB2320130A GB 2320130 A GB2320130 A GB 2320130A GB 9625173 A GB9625173 A GB 9625173A GB 9625173 A GB9625173 A GB 9625173A GB 2320130 A GB2320130 A GB 2320130A
- Authority
- GB
- United Kingdom
- Prior art keywords
- heat resistant
- layer
- rapid thermal
- resistant metallic
- silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 26
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 238000009792 diffusion process Methods 0.000 claims abstract description 15
- 238000002425 crystallisation Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 230000008025 crystallization Effects 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 230000003746 surface roughness Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 33
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 20
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 19
- 229910052719 titanium Inorganic materials 0.000 claims description 19
- 239000010936 titanium Substances 0.000 claims description 19
- 238000004151 rapid thermal annealing Methods 0.000 claims description 13
- 238000001039 wet etching Methods 0.000 claims description 12
- 229910052786 argon Inorganic materials 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 9
- 238000004381 surface treatment Methods 0.000 claims description 7
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims 4
- 238000005530 etching Methods 0.000 claims 4
- 238000000151 deposition Methods 0.000 claims 3
- 238000010438 heat treatment Methods 0.000 claims 3
- 238000007788 roughening Methods 0.000 claims 3
- 229910021529 ammonia Inorganic materials 0.000 claims 2
- 235000011149 sulphuric acid Nutrition 0.000 claims 2
- 239000001117 sulphuric acid Substances 0.000 claims 2
- 230000003247 decreasing effect Effects 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 150000002978 peroxides Chemical class 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 101000579226 Homo sapiens Renin receptor Proteins 0.000 description 1
- 102100028254 Renin receptor Human genes 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Prior to the formation of a heat resistant metallic Titanium silicide layer on top of a silicon substrate, a treatment of exposed surfaces of a gate terminal 16 and source/drain diffusion regions 20 is performed to increase surface roughness enabling an increase in the crystallization nucleus number, as well as lowering the crystallization temperature of the silicide.
Description
2320130 IMPROVED SELF-ALIGNED SILICIDE MANUFACTURING METHOD
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to a semiconductor manufacturing method, and more particularly to a self-aligned silicide (salicide) manufacturing method.
2. Description of the Related Art
In accordance with the increase in the level of semiconductor component integration, designed dimensions of components gradually become smaller and smaller, which raises the resistance of the source and drain terminals of a MOS component to a level comparable to the MOS channel. To adjust the sheet resistance of both the drain and the source, as well as to keep a shallow contact surface between the metal and MOS layer intact a so-called self-aligned silicide (salicide) manufacturing process is employed, and has gradually become a part of the VLSI manufacturing process at line widths of 0.5[im or below.
Titanium is one of the most commonly used heat resistant metallic materials for using in salicide processing (others include metals such as platinum. and cobalt). The conventional manufacturing process includes forming a thin titanium layer above the gate defined silicon chip by a sputtering method, and using a high temperature to make the titanium react with polysilicon layers above the gate and sourceldrain terminals, thus forming titanium silicide. After the unreacted titanium is removed by a wet etching method, a thin titanium silicide layer on each of the three MOS terminals (gate, source, drain) is left behind. Because the self-aligned silicide manufacturing process can form a low resistance metallic silicide (such as titaniwn silicide) on the surface of silicon and polysilicon, which is formed withou t photolithographic processing, the manufacturing process is rather simple, except that the operating conditions for rapid thermal annealing in the silicide processing need to be monitored carefully.
A conventional self-aligned silicide manufacturing method is now described as an example illustrating the manufacturing process. Referring to Figure 1 A, a - 1 Ref.:0465-US-PA/Final File:0465USF.DOC/Liang/HWC semiconductor silicon substrate 10 is provided, and a field oxide layer 12, a transistor with a gate made from an oxide layer 14 and a polysilicon gate terminal electrode 16 together with source/drain diffusion regions 20 are formed on the substrate 10. Sidewall spacers 18 are also formed on two sidewalls of the gate.
Then, referring to Figure IB, a heat resistant metallic layer 22 (for example, titanium, cobalt or platinum) is formed above the substrate 10 by a DC sputtering method. For this example and in this illustration, a titanium layer 22 is formed... ' Finally, referring to Figure IC, at a high temperature and using rapid thermal processing, titanium in contact with the gate and sourceldrain diffusion regions reacts to io form thin titanium silicide layers 24 and 26 on the surface of the gate and the sourceldrain terminals. In other areas, the titanium layer 22 remains unreacted and is removed by a subsequent wet etching method.
For component dimensions having a line width of less than 0Agm, using self aligned titanium silicide has become a necessary part in the processing because the lower sheet resistance and contact resistance provided by the process is very important for achieving high speed/low energy components.
In conventional processing methods, plating a thicker layer of metallic titanium usually can form a better titanium silicide layer accompanied by a better sheet resistance and contact resistance, however the resulting junction depth is shallower which can disadvantageously result in a higher leakage current. Moreover, the high temperature needed in the silicide formation step is difficult to control. Although rapid thermal processing (RTP) techniques have been widely applied in this processing step, the relative newness of RTP, along with other processing factors makes the yield from self aligned silicide processing still much lower than in conventional processing.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide an improved selfaligned silicide manufacturing method in which, prior to the formation of the heat resistant metallic layer on top of the silicon substrate, a treatment of the exposed surfaces of the gate terminal and source/drain diffusion regions is performed, to increase the surface roughness thereby enabling an increase in the crystallization nucleus number, as well as Ref.:0465-US-PA/Final File:0465USF.DOC/Liang/HWC lowering the crystallization temperature. Such a treatment can lower not only the sheet resistance and contact resistance, but also reduce leakage current as well. The processing in an exemplary embodiment includes the following steps:
(a) forming a transistor which includes a gate terminal having two sidewalls, and source/drain diffusion regions, on a silicon substrate, and forming sidewall spacers on the two sidewalls of the gate terminal; (b) performing a surface treatment of exposed surfaces of the gate terminal and the sourceldrain diffusion regions thereby increasing surface roughness and increasing the crystallization nucleus number as well as lowering crystallization temperature; (c) forming a heat resistant metallic layer above the silicon substrate; (d) performing a first rapid thermal annealing letting the heat resistant metallic layer, which is in contact with the gate terminal and the source/drain diffusion regions, react to form a heat resistant metallic silicide layer, the heat resistant metallic layer in contact with the sidewall spacers remaining unreacted; (e) removing the unreacted heat resistant metallic layer; and (f) performing a second rapid thermal annealing letting the heat resistant metallic silicide layer recrystallize, thereby lowering sheet resistance and contact resistance.
BRIEF DESCRIPTION OF THE DRAWINGS
Other objects, features, and advantages of the invention will become apparent from the following detailed description of the exemplary preferred but non-limiting embodiment. lle description is made with reference to the accompanying drawings in which:
Figures 1A to IC are cross-sectional views showing the manufacturing process in a conventional self-aligned silicide processing; Figures 2A to 2D are cross-sectional views showing the manufacturing process in a self-aligned silicide processing according to an exemplary embodiment of this invention.
Ref.:0465-US-PA/Final File:046SUSF.DOC/Liang/HWC DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
First, referring to Figure 2A, a semiconductor component, such as that shown in Figure IA, is provided, similar elements being labelled similarly. The semiconductor component includes a field oxide area 12, a transistor with a gate made from an oxide layer 14 and a polysilicon gate electrode terminal 16 together with source/drain diffusion regions 20, formed above semiconductor substrate 10. Sidewall spacers 18 are formed on the two sidewalls of the gate.
Then, referring to Figure 2B, a surface treatment is performed on the exposed surfaces of the gate terminal and the source/drain diffusion regions to form rough io surfaces 23 as shown in the enlarged area to increase the crystallization nucleus number and to lower the crystallization temperature. Argon plasma or wet etching methods, for example, can be used in the surface treatment process, once or twice consecutively to increase the roughness in the polysilicon surfaces. The argon plasma reaction can be conducted, for example, under an argon gas flow rate of 60 sccm and a pressure of about 100 mTorr, with the electrode plate power supply set to about 80OW; and the etchant solution used in the wet etching method is, for example, MSDS-PME, which is manufactured by an American company, and comprises N14F/NIA4H2P04M20.
Next, referring to Figure 2C, a heat resistant metallic layer, for example, platinum, cobalt or titanium, is deposited above the silicon substrate by a DC sputtering method, and in this exemplary preferred embodiment, a layer of titanium 25 with a thickness between about 400 500A is deposited. Then a first rapid thermal annealing is performed to let the gate terminal and the sourceldrain diffusion regions in contact with the titanium layer react to form titanium silicide. Annealing is, for example, first conducted in a nitrogen atmosphere at a temperature of about 65WC for about 30 seconds, and then the temperature is set to about 750T to perform another annealing for 30 seconds.
Finally, referring to Figure 21), after the first annealing, titanium silicide layers 27 and 29 are formed in the gate terminal and source/drain diffusion regions, and the unreacted metallic titanium layer elsewhere is removed by a selective wet etching method. In selective wet etching, ammonia water/hydrogen peroxide/DI water, having a volumetric ration of 1: L5, for example, at a temperature of about 75C, is first used for Ref.:0465-US-PA/Final File:0465USF.DOC/Liang/HWC minutes to remove the unreactive metallic titanium layer, and then a sulfuric acid/water solution, having a volumetric ratio of 1A, for example, is used to remove the residual metallic titanium layer. Thereafter, a second rapid thermal annealing is performed to let the titanium silicide layer recrystallize (phase transformation) to lower its sheet resistance and contact resistance. The second annealing is conducted, for example, under a nitrogen atmosphere with a temperature of about 825'C, and is continuous for 20 seconds.
A low sheet resistance and low contact resistance self-aligned titanium silicide layer manufactured according to this invention is thus formed. It overcomes the defect io of a high leakage current in the conventional manufacturing method, and is suitable for component designs having small dimensions and/or a high speedllow power characteristic.
While the invention has been described by way of example and terms of an exemplary preferred embodiment, it is to be understood that the invention not be limited thereto. On the contrary, it is intended that the invention covers various modifications and similar arrangements included within the scope of the appended claims, which should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Ref.:0465-US-PA/Final File:046SUSF.DOC/Liang/HWC
Claims (11)
1 7. A method according to claim 1, wherein the first rapid thermal annealing step (d) comprises annealing in a nitrogen atmosphere at a temperature of about 650,C for 30 seconds and subsequently annealing at a temperature of about 75TC for 30 seconds.
2 3 1 8. A method according to claim 1, wherein the second rapid thermal annealing step (f) comprises continuous annealing in a nitrogen atmosphere at a temperature of about 825'C for 30 seconds.
2 3 1 9. A method according to claim 1, wherein step (e) comprises etching the unreacted heat resistant metallic layer with a solution of ammonia waterlhydrogen peroxide/water having a volumetric ratio of L1:5 at a temperature of about 750C, and subsequently etching the heat resistant metallic layer remaining with a solution of sulphuric acid/water having volumetric ratio of I.A.
2 3 4 5 1 10. A method according to claim 5, wherein the thickness of the metallic titanium layer is formed a range of about 400 - 500A.
Amendments to the claims have been filed as follows Claims 1. A method of forming a self-aligned silicide layer of a terminal structure, comprising a gate terminal, a drain diffusion region or a source diffusion region of a transistor, the method including exposing a surface of the terminal structure, roughening the exposed surface, depositing and annealing a metal on the roughened exposed surface to produce a metal silicide layer, wherein the exposed surface is roughened such that the number of crystallisation nuclei available is increased and the crystallisation temperature of the metal silicide is decreased.
2. A method according to claim 1, wherein the roughening is carried out using an argon plasma with reaction conditions including an argon gas flow rate of about 60 sccm, a pressure of about 100 mTorr and an electrode plate power of about 80OW.
3. A method according to claim 1, wherein the roughening is carried out using a wet etching method with a wet etching solution comprising MSDSPME.
4. A method according to claims 2 and 3.
5. A method according to any preceding claim, wherein the metal comprises titanium.
6. A method according to any preceding claim, wherein said annealing comprises a first rapid thermal annealing step for forming the metal silicide layer and a second rapid thermal annealing step for recrystalizing the metal silicide layer to thereby lower the sheet and contact resistance of the terminal structure.
7. A method according to claim 6, wherein the first rapid thermal annealing step comprises heating to about 650C in a nitrogen atmosphere for 30 seconds and subsequently heating to about 7SO'C for 30 seconds.
9
8. A method according to claim 6 or 7, wherein the second rapid thermal annealing comprises heating to about 825'C in a nitrogen atmosphere for 30 seconds.
9. A method according to any preceding claim, including etching unreacted deposited metal using a 1:1:5 by volume ammonia/hydrogen peroxide/water solution at a temperature of about 75Q and subsequently with a 1:4 by volume sulphuric acid/water solution.
10. A method according to any preceding claim, wherein the deposition of the lo metal comprises depositing a layer of titanium having a thickness in the range of about 400 - 500A.
11. A method substantially as hereinbefore described.
9
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9625173A GB2320130B (en) | 1996-08-09 | 1996-12-04 | Improved self-ligned silicide manufacturing method |
| FR9616293A FR2752331B1 (en) | 1996-08-09 | 1996-12-31 | IMPROVED SELF-ALIGNED SILICIDE PROCESS |
| DE19705342A DE19705342A1 (en) | 1996-08-09 | 1997-02-12 | Silicide process for MOS transistor |
| JP15047497A JP3258934B2 (en) | 1996-08-09 | 1997-05-23 | Improved method for producing self-aligned silicides |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW085109703A TW328153B (en) | 1996-08-09 | 1996-08-09 | The manufacturing method for improving property of salicide |
| GB9625173A GB2320130B (en) | 1996-08-09 | 1996-12-04 | Improved self-ligned silicide manufacturing method |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9625173D0 GB9625173D0 (en) | 1997-01-22 |
| GB2320130A true GB2320130A (en) | 1998-06-10 |
| GB2320130B GB2320130B (en) | 2001-11-07 |
Family
ID=26310543
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9625173A Expired - Fee Related GB2320130B (en) | 1996-08-09 | 1996-12-04 | Improved self-ligned silicide manufacturing method |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP3258934B2 (en) |
| DE (1) | DE19705342A1 (en) |
| FR (1) | FR2752331B1 (en) |
| GB (1) | GB2320130B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3295931B2 (en) * | 1999-04-28 | 2002-06-24 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| GB0024648D0 (en) | 2000-10-07 | 2000-11-22 | Bae Systems Plc | A method and apparatus for assembling an aircraft wheel or brake component on an axle of an undercarriage |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0325328A1 (en) * | 1988-01-20 | 1989-07-26 | Koninklijke Philips Electronics N.V. | A method of manufacturing a semiconductor device using sputter etching |
| JPH02297939A (en) * | 1989-05-12 | 1990-12-10 | Matsushita Electron Corp | Manufacture of semiconductor integrated circuit device |
| US4983544A (en) * | 1986-10-20 | 1991-01-08 | International Business Machines Corporation | Silicide bridge contact process |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3497407A (en) * | 1966-12-28 | 1970-02-24 | Ibm | Etching of semiconductor coatings of sio2 |
| US4545116A (en) * | 1983-05-06 | 1985-10-08 | Texas Instruments Incorporated | Method of forming a titanium disilicide |
| JPH0260126A (en) * | 1988-08-26 | 1990-02-28 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPH04107920A (en) * | 1990-08-29 | 1992-04-09 | Fujitsu Ltd | Manufacture of semiconductor device |
| JP3285934B2 (en) * | 1991-07-16 | 2002-05-27 | 株式会社東芝 | Method for manufacturing semiconductor device |
| US5344793A (en) * | 1993-03-05 | 1994-09-06 | Siemens Aktiengesellschaft | Formation of silicided junctions in deep sub-micron MOSFETs by defect enhanced CoSi2 formation |
| JP2611726B2 (en) * | 1993-10-07 | 1997-05-21 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JP3046208B2 (en) * | 1994-08-05 | 2000-05-29 | 新日本製鐵株式会社 | Cleaning liquid for silicon wafer and silicon oxide |
| JP3329128B2 (en) * | 1995-03-28 | 2002-09-30 | ソニー株式会社 | Method for manufacturing semiconductor device |
-
1996
- 1996-12-04 GB GB9625173A patent/GB2320130B/en not_active Expired - Fee Related
- 1996-12-31 FR FR9616293A patent/FR2752331B1/en not_active Expired - Fee Related
-
1997
- 1997-02-12 DE DE19705342A patent/DE19705342A1/en not_active Ceased
- 1997-05-23 JP JP15047497A patent/JP3258934B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4983544A (en) * | 1986-10-20 | 1991-01-08 | International Business Machines Corporation | Silicide bridge contact process |
| EP0325328A1 (en) * | 1988-01-20 | 1989-07-26 | Koninklijke Philips Electronics N.V. | A method of manufacturing a semiconductor device using sputter etching |
| GB2214708A (en) * | 1988-01-20 | 1989-09-06 | Philips Nv | A method of manufacturing a semiconductor device |
| JPH02297939A (en) * | 1989-05-12 | 1990-12-10 | Matsushita Electron Corp | Manufacture of semiconductor integrated circuit device |
Non-Patent Citations (1)
| Title |
|---|
| Patent Abstracts of Japan, Section E, Section No 1037, Vol 15, No 78, Pg 118, 22/2/91 & JP 02 297939 A * |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2752331B1 (en) | 1998-11-06 |
| GB9625173D0 (en) | 1997-01-22 |
| JP3258934B2 (en) | 2002-02-18 |
| DE19705342A1 (en) | 1998-02-12 |
| FR2752331A1 (en) | 1998-02-13 |
| GB2320130B (en) | 2001-11-07 |
| JPH1079508A (en) | 1998-03-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |