GB2317500A - Semiconductor device manufacture - Google Patents

Semiconductor device manufacture Download PDF

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Publication number
GB2317500A
GB2317500A GB9725665A GB9725665A GB2317500A GB 2317500 A GB2317500 A GB 2317500A GB 9725665 A GB9725665 A GB 9725665A GB 9725665 A GB9725665 A GB 9725665A GB 2317500 A GB2317500 A GB 2317500A
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Prior art keywords
layer
semiconductor
resist pattern
wiring layer
semiconductor device
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GB9725665A
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GB2317500B (en
GB9725665D0 (en
Inventor
Naoto Andoh
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority claimed from JP8072216A external-priority patent/JPH09260405A/en
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of GB9725665D0 publication Critical patent/GB9725665D0/en
Publication of GB2317500A publication Critical patent/GB2317500A/en
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Publication of GB2317500B publication Critical patent/GB2317500B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/765—Making of isolation regions between components by field effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A semiconductor device is manufactured by a method comprising: (a) successively forming semiconductor layers 61,62 of opposite conductivity types on a semiconductor substrate 60; (b) forming a semiconductor element in a region 36 of the upper layer 62; (c) forming a first resist pattern (63) covering the region 36; (d) implanting ions into the remaining portion 41 of the layers 61,62, using the first resist pattern (63) as a mask; (e) forming a first wiring layer 45 on the remaining portion 41 and a second wiring layer 46 extending from it to a portion of the semiconductor element; (f) forming a second resist pattern 66 on the reverse side with an aperture opposite the first wiring layer 45; (g) wet etching a hole 42 to the first wiring layer 45; (h) depositing an insulating layer 70, using the second resist pattern 66 as a mask; (I) exposing the first wiring layer 45 by reactive ion etching, using the second resist pattern 66 as a mask; (j) removing the pattern 66; and (k) providing an electrically conductive layer (43) on the exposed area of the first wiring layer 45 and on the insulating layer on the inner wall 421 of the hole 42. Alternatively, steps (h) and (I) may be replaced by: (h') enlarging the aperture in the second resist pattern 66 to the end opening of the hole 42 and (I') depositing an insulating layer on the inner wall 421 of the hole but not on an exposed area of the first wiring layer 45.

Description

SEMICONDUCTOR DEVICE i-r== The present invention relates to methods for manufacturing a semiconductor device, more particularly, a field effect semiconductor integrated circuit device having a via hole in an epitaxial layer in which leakage current from the epitaxial layer to the via hole is positively prevented, as well as to a method of manufacturing such a device.
In power amplifiers dealing with high-frequency signals such as high power amplifiers, amplifiers provided at antenna portions of satellite communications equipment, pocket telephones and the like, there have been employed field effect transistors using compound semiconductors capable of providing high power and high speed response.
Fig. 16 illustrates a typical example of such a semiconductor device which is known to the applicant. In this figure, a semiconductor device 1 comprises a semiconductor element 2 in the form of a field effect transistor 2, a compound semiconductor substrate 3 formed of a compound material having a semi-insulation property such as gallium arsenide (GaAs), indium phosphide (InP), etc., a ptype buffer layer 4 formed on the substrate 3, an n-type semiconductor layer 5 formed on the wtype buffer layer 4, and a semiconductor element forming region 6 provided in the n-type semiconductor layer 5, the region 6 acting as an active layer of the field effect transistor. The active layer 6 is formed with a recess 7 in which a gate electrode 8 is provided. A drain electrode 9 and a source electrode 10 are provided on the n-type semiconductor layer 5 on the opposite sides of the gate electrode 8.
In the n-type semiconductor layer 5 there is provided an isolation region 11 which is formed by an ion implantation or doping using an ion source formed, for example, of boron, for the purpose of performing area division of the active layer 6.
A via hole 12 is formed through the substrate 3, the buffer layer 4 and the semiconductor layer 5 so that a backside electrode 13 on the surface of the substrate 3 is electrically connected to a via hole upper electrode 14 in the form of a wiring layer formed on the surface of the semiconductor device 1, the via hole upper electrode 14 being further electrically connected to the source electrode 10.
The semiconductor device 1 is substantially constructed as follows.
The ptype buffer layer 4 and the n-type semiconductor layer 5 are deposited in succession on the substrate 3 and boron ions are implanted or doped into the thus deposited layers while leaving the active layer 6 intact to thereby make the n-type semiconductor layer 5 non-conductive, thus performing regional division between the active layer 6 in the form of a semiconductor element forming region and the isolation region 11.
Subsequently, the drain electrode 9 and the source electrode 10 are formed on the active layer 6 by means of a vapor-deposition and lift-off method, and then the recess 7 is formed by etching and the gate electrode 8 is provided by the vapor-deposition and lift-off method while adjusting a current supplied thereto.
The via hole upper electrode 14 is provided by the vapor-deposition and lift-off method in such a manner that it is electrically connected to the source electrode 10. Thereafter, the via hole 12 is formed through the deposited layers from the substrate side by, for example, sulfur etching, and then the backside electrode 13 is formed by means of, for example, an electrolytic plating method.
In this type of semiconductor device used with a high power amplifier, power amplification is carried out by maintaining the gate voltage at a constant value ranging from 0 V to -1.5 V with the source electrode 10 being connected to ground through the backside electrode 13 and by changing the voltage of the drain electrode 9 between zero volts and a voltage in the range of 3 - 10 V.
With the conventional semiconductor device as constructed above, boron ions are implanted or doped into the n-type semiconductor 5 to make it nonconductive. In this case, however, in order to perform ion implantation or doping through acceleration of an element having a large atomic weight such as boron so as to make regional division between the active layer 6 of the semiconductor element and the isolation region 11, a high power accelerator is required and it is rather difficult to perform ion implantation or doping to a required depth for providing nonconductivity.
In this type of semiconductor device 1, a depth from the surface of the n-type semiconductor layer 5 through the p-type buffer layer 4 is about 2,000 angstroms to 10,000 angstroms so there is the possibility that the p-type buffer layer can not be rendered nonconductive to a satisfactory extent by means of the ion implantation or doping of boron.
In cases where the type buffer layer 4 in the lower portion of the isolation region 11 is not rendered nonconductive to any satisfactory extent, the gate electrode 8 of the field effect transistor 2 is supplied with a negative voltage the absolute value of which is less than a pinch-off voltage therefor, so that a forward direction current flows between the depleted active layer 6 and the p-type buffer layer 4, and further from the buffer layer 4 to the source electrode 10 through the backside electrode 11 and the via hole upper electrode 13. Thus, there develops a leakage current between the gate electrode 8 and the source electrode 10, posing the problem that the gate-source dielectric resistance is reduced.
An example of coping with such a problem of leakage current occurring in the inner surface of a via hole is described in Patent Laid-Open No 4-39968. In this example, essential portions of the inner surface of the via hole are doped with ions such as proton, oxygen, etc., to partially isolate the via hole inner surface to thereby provide an isolation layer of a thickness in the range of from about 2 micrometers to about 50 micrometers. Thereafter, a via hole wiring layer is formed on the isolation layer whereby a source electrode and a backside electrode are connected to each other, thus preventing leakage current through a buffer layer.
In this case, the active layer, the buffer layer and the substrate, through which the via hole is to be formed, are subjected to ion implantation or doping to first provide the isolation layer or region of semi-insulation, and thereafter the via hole is subsequently formed through these layers while leaving the isolation region.
Here, it is to be noted that if proton is used with this method, electric properties of a field effect transistor, a heterojunction bipolar transistor (HBT) and the like having a high mobility transistor (HEMT) type structure may adversely be affected by proton. Therefore, it is rather difficult to employ this method in general as a versatile technology.
Another example is disclosed in Patent Laid-Open No. 3-153057 in which an insulating film such as a silicon nitride film, a silicon oxide film and the like is formed on the inner surface of a via hole by means of a chemical vapor deposition (CVD) method, and a via hole wiring layer is then formed on the insulating film to thereby provide electrical connection between a source electrode and a backside electrode. In this manner, leakage current through a buffer layer is prevented.
In this case, however, an etching process is required in which formation of a master pattem and etching are performed for removing the insulating film which is disposed on the backside surface of the source electrode and directed toward the inside of the via hole prior to the processes in which the via hole is formed through the deposited layers from the side of the semiconductor substrate, with the insulating film being then formed on the inner surface of the via hole and the via hole wiring layer being formed thereon to provide electrical connection between the source electrode and the backside electrode.
An object of the present invention is to provide a method of manufacturing a semiconductor device in which an isolation layer can be formed on an inner wall of a via hole through a simple process to provide electrical isolation between the buffer electrode and the source electrode.
In accordance with one aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method comprising the steps of: successively forming a first semiconductor layer and a second semiconductor layer on a first surface of a semiconductor substrate, the first and second semiconductor layers having opposite polarities in electrical conduction with respect to each other; selectively forming a semiconductor element on the second semiconductor layer; forming a first resist pattern on the surface of the second semiconductor layer so as to cover a semiconductor element forming region thereof at which the semiconductor element is formed; performing ion implantation into the first and second semiconductor layers so as to electrically isolate the semiconductor element forming region from a remaining portion of the second semiconductor layer with the first resist pattem used as a mask; forming a first wiring layer selectively on the remaining portion of the second semiconductor layer and a second wiring layer extending from the first wiring layer to a portion of the semiconductor element on the second semiconductor layer; forming a second resist pattem having an aperture on a second surface of the semiconductor substrate in such a manner that the aperture is disposed in opposition to the first wiring layer; removing, by means of wet etching, a part of the semiconductor substrate from the second surface thereof to such a depth as to expose the first wiring layer to thereby define a hole; depositing an insulating layer on the inner wall of the hole from the surface of the second resist pattern with the second resist pattem used as a mask; removing, by means of a reactive ion etching, the insulating layer to such an extent as to expose the first wiring layer from the surface of the second resist pattern with the second resist pattern used as a mask; removing the second resist pattem from the second surface of the semiconductor substrate; and providing an electrically conductive layer on the exposed surface of the first wiring layer at the side of the hole and on the inner wall of the hole.
With the semiconductor device manufacturing method as constructed above, the insulating layer can be provided while leaving the resist pattem which is used for forming the hole, and the insulating film in contact with the via hole upper electrode is removed by a reactive ion etching (RIE) method from the rear surface of the wafer by utilizing the aperture in the resist pattern, so it is possible to omit a mask patten forming step for partially removing the insulating film which is provided after formation of the hole, thus simplifying the entire process steps.
In accordance with a further aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method comprising the steps of: successively forming a first semiconductor layer and a second semiconductor layer on a first surface of a semiconductor substrate, the first and second semiconductor layers having opposite polarities in electrical conduction with respect to each other; selectively forming a semiconductor element on the second semiconductor layer; forming a first resist pattem on the surface of the second semiconductor layer so as to cover a semiconductor element forming region thereof at which the semiconductor element is formed; performing ion implantation into the first and second semiconductor layers so as to electrically isolate the semiconductor element forming region from a remaining portion of the second semiconductor layer with the first resist pattern used as a mask; forming a first wiring layer selectively on the remaining portion of the second semiconductor layer and a second wiring layer extending from the first wiring layer to a portion of the semiconductor element on the second semiconductor layer; forming a second resist pattem having an aperture on a second surface of the semiconductor substrate in such a manner that the aperture is disposed in opposition to the first wiring layer; removing, by means of wet etching, a part of the semiconductor substrate from the second surface thereof to such a depth as to expose the first wiring layer to thereby define a hole; enlarging the aperture in the second resist pattem to an end opening of the hole at the second surface of the semiconductor substrate; depositing an insulating layer on the inner wall of the hole other than the exposed surface of the first wiring layer from the surface of the second resist pattem with the second resist pattem having the thus enlarged aperture used as a mask; removing, by means of a reactive ion etching, the insulating layer to such an extent as to expose the first wiring layer from the surface of the second resist pattern in an oblique direction thereof with the second resist pattern used as a mask; removing the second resist pattern from the second surface of the semiconductor substrate; and providing an electrically conductive layer on the exposed surface of the first wiring layer at the side of the hole and on the inner wall of the hole.
With the semiconductor element manufacturing method as defined above, a master pattern forming step for partially removing the insulating film which is provided after the formation of the hole is omitted, thus simplifying the entire process steps.
The invention will be described further, by way of example, with reference to the accompanying drawings.
Fig. lisa plan view of a semiconductor device; Fig. 2 is a cross sectional view taken along line ll-ll of Fig. 1; Fig. 3 is a cross sectional view showing a process step for manufacturing the semiconductor device; Fig. 4 is a cross sectional view showing another process step for manufacturing the semiconductor device; Fig. 5 is a cross sectional view showing a further process step for manufacturing the semiconductor device Fig. 6 is a cross sectional view showing a further process step for manufacturing the semiconductor device; Fig. 7 is a cross sectional view showing a further process step for manufacturing the semiconductor device Fig. 8 is a cross sectional view showing a further process step for manufacturing the semiconductor device; Fig. 9 is a cross-sectional view showing a further process step for manufacturing the semiconductor device; Fig. 10 is a partially broken view showing a process step of a method for manufacturing a semiconductor device according to a first example of the invention; Fig. 11 is a partially broken view showing another process step of the semiconductor device manufacturing method according to the first example; Fig. 12 is a partially broken view showing a further process step of the semiconductor device manufacturing method according to the first example; Fig. 13 is a partially broken view showing a process step of a method for manufacturing a semiconductor device according to a second example of the invention; Fig. 14 is a partially broken view showing another process step of the semiconductor device manufacturing method according to the second example; Fig. 15 is a partially broken view showing a further process step of the semiconductor device manufacturing method according to the second example; and Fig. 16 is a cross sectional view of a conventional semiconductor device. Referring to the drawings, Figs. 1 and 2 illustrate a semiconductor device including a field effect transistor in accordance with the invention claimed in our cpending application 9626387.6 (2 311 652).
In Figs. 1 and 2, a semiconductor device, generally designated at reference numeral 31, comprises a semiconductor element in the form of a field effect transistor 32, a semiconductor substrate in the form of a compound semiconductor substrate 33 formed of a semi-insulating compound having a partially insulating property such as gallium arsenate (GaAs), indium phosphide (InP) and the like, a first semiconductor layer in the form of a p-type buffer layer 34 formed on a first or front surface 331 of the compound semiconductor substrate 33, a second semiconductor layer in the form of an n-type semiconductor layer 35 formed on the p-type buffer layer 34, and a semiconductor element forming region in the form of an active layer 36 of the field effect transistor 32 provided in the n-type semiconductor layer 35.
The active layer 36 is provided on the surface thereof with a recess 37 in which a gate electrode 38 is disposed with a drain electrode 39 and a source electrode 40 being respectively provided on the surface of the active layer 36 on the opposite sides of the gate electrode 38.
The active layer 36 is divided into some regions by means of an electrically isolating region or isolation region 41 in the form of an ion implantation or doping region which is formed by an ion implantation or doping technique using boron as an ion source.
A via hole 42 is formed through the semiconductor substrate 33, the p-type buffer layer 34 and the n-type semiconductor layer 36, which have a common inner wall or surface 421 defining the via hole 42 and extending over these layers.
A conductive layer in the form of a backside electrode 43 is formed on and along a second or rear surface 332 of the compound semiconductor substrate 33 and the via hole inner wall 421 in intimate contact therewith.
A groove 44 is provided in the isolation region 41 with its depth extending from the surface of the n-type semiconductor layer 35 to the compound semiconductor substrate 33 through the p-type buffer layer 34.
A first wiring layer in the form of a via hole upper electrode 45 is formed on the surface of the semiconductor device 31 at a location over the via hole 42 in electrical contact with the backside electrode 43. The via hole upper electrode 45 is electrically connected to the source electrode 40 through a second wiring layer in the form of a bridging wire 46 which extends across the groove 44.
Next, a method of manufacturing the semiconductor device 31 as constructed above will be described while referring to Figs. 3 through 9 which illustrate respective process steps in the manufacture of the semiconductor device 31 not in accordance with the present invention.
First, a GaAs layer 61 constituting the buffer layer 34 and an n-type GaAs layer 62 constituting the active layer 36 are successively deposited on one surface 601 of the n-type GaAs substrate 60 by means of a Metalorganic Chemical Vapor Deposition (MOCVD) method. For example, the thicknesses of these layers are as follows: the GaAs substrate 60 is about 600 micrometers thick; the p-type GaAs layer 61 is in the range of from about 4,000 angstroms to 5,000 angstroms thick; the n-type GaAs layer 62 is about 6,000 angstroms thick. Fig. 3 shows the semiconductor device produced in this process step. Though the MOCVD method is employed herein, a Molecular Beam Epitaxial method can instead be used.
Subsequently, as shown in Fig. 4, a resist pattem 63 masking only a portion of the surface of the n-type GaAs layer 62 at which the FET 32 is provided is formed by means of a lithography process. With the resist pattern 63 used as a mask, boron ions are implanted into the n-type GaAs layer 62 to provide the isolation region 41. In this regard, since the atomic weight of boron is large, a special high-power ion doping apparatus is required in order to dope boron ions into the n-type GaAs layer 62 to a satisfactory depth. Thus, with the ordinary ion doping apparatus, a sufficient acceleration voltage is not obtained so that the p-type GaAs layer 61 can not sometimes be rendered nonconductive to any satisfactory extent. One example of doping conditions for two dopings are as follows: For the first doping: Acceleration Voltage: 300 keV; Dose Quantity: 4.0 x 10" /cm2 For the second doping: Acceleration Voltage: 80 keV; Dose Quantity: 4.0 x 10"/cm2 Fig. 4 shows, in cross section, the semiconductor device as produced in this process step.
Thereafter, the resist pattem 63 is removed, and on the surface of the active layer 36 surrounded by the isolation region 41, there is formed a resist pattern having apertures at locations corresponding to the source electrode 40 and the drain electrode 39 by using a lithography process. Then, with the resist pattem used as a mask, the source electrode 40 and the drain electrode 39 are formed with aluminum by means of a doping technique such as a deposition and lift-off method. Fig. 5 shows the semiconductor device thus formed in this process step.
As shown in Fig. 6, a recess 37 is then formed in the isolation region 41 by an etching process in order to perform current regulation, and the gate electrode 38 is formed in the recess 37 by the deposition and lift-off method.
Subsequently, as shown in Fig. 7, using the lithography, a resist pattern 65 is formed which has ax aperture 64 at a 1 * tD * P e 44 in the isolation region 41. With the resist pattem 65 used as a mask, portions of the semiconductor layers are removed by etching to a depth extending from the surface of the isolation region 41 of the n-type GaAs layer 62 to the p-type GaAs layer 61 through the p-type buffer layer 34. An etching liquid employed in this process is a tartaric acid liquid, for example.
Thereafter, the resist pattem65 is removed and, by means of the deposition and lift-off method, the via hole upper electrode 45 is formed on the surface of the isolation region 41 in intimate contact therewith at a location at which the via hole 42 is to be later provided. The bridging wire layer 46 is formed for bridging the via hole upper electrode 45 and the source electrode 40 in electrical connection to each other by means of electrolytic plating. Fig. 8 shows, in cross section, the semiconductor device thus formed in this process step.
Further, a resist is coated on the second or rear surface 602 of the GaAs substrate 60 opposite the first surface 601 thereof to form a resist pattem 66 having an aperture at a location opposing the via hole upper electrode 45 by means of lithography. Then, using the resist patter 66 as a mask, the GaAs substrate 60, the p-type GaAs layer 61 and the n-type GaAs layer 62 are partially removed through etching to such an extent to expose the backside of the via hole upper electrode 45 to thereby define the via hole 42 surrounded by the inner wall 421. In this etching process, sulfuric acid is employed as an etching liquid, for example. Fig. 9 shows the semiconductor device as produced in this process step.
Thereafter, the resist pattern 66 is removed, and then the backside electrode 43 is formed, for example, by electrolytic plating on the second surface of the GaAs substrate 60, the inner wall 421 of the via hole 42 and the exposed backside surface of the via hole upper electrode 45. The semiconductor device thus formed in this process step is shown in Figs. 1 and 2.
The operation of the semiconductor device 31 as constructed above will now be described below while referring to Figs. 1 and 2.
With this kind of semiconductor device 31 used for example with a high power amplifier, power amplification is effected by maintaining the gate electrode 38 at a voltage ranging from 0 V to -1.5 V, with the source electrode 40 being connected to ground through the backside electrode 43, and by switching over the drain electrode 39 between 0 V and a voltage of 3 V to -1.5 V to thereby maintain the gate-drain dielectric resistance. In this case, a negative voltage less than a pinch-off voltage is applied to the gate electrode 38 of the field effect transistor 32, resulting in a situation that a forward direct current flows between the depleted active layer 36 and the p-type buffer layer 34. Thus, even though the p-type buffer layer 34 is not made conductive due to insufficient doping of B ions, the p-type buffer layer 34 beneath the FET 32 is isolated by the groove 44 to break electrical conduction between the p-type buffer layer 34 and the backside electrode 43, thereby preventing leakage current from flowing between the gate electrode 38 and the source electrode 40 and hence degradation of the gate-source dielectric resistance.
In this manner, the above arrangement that the groove 44 is disposed so as to surround the FET 32 is suitable for application to a semiconductor device having a high frequency band, e.g., higher than 4 to 5 GHz. This is because the semiconductor device with such a high frequency band generates a greater amount of heat so that the number of via holes has to be increased for effective cooling. Another reason for increasing the number of via holes is to reduce the impedance of the semiconductor device. As a result, the arrangement of the groove 44 surrounding the FET 32 serves to reduce the surface area thereof required and hence the specific surface area of the groove 44 relative to the entire semiconductor device, thereby enhancing area efficiency of the semiconductor element as well as serving for miniaturization of the semiconductor device.
EX 1 A method of manufacturing a semiconductor device, in accordance with the present invention, will now be described.
A ptype GaAs layer 61 constituting the buffer layer 34 and an n-type GaAs layer 62 in which an active layer 36 is to be formed are successively provided on a first or front surface of a semiconductor substrate 60 such as a GaAs substrate by means of the Metalorganic Chemical Vapor Deposition method.
For example1 the thicknesses of these layers are designed as follows: the GaAs substrate 60 is about 600 micrometers thick; the p-type GaAs layer 61 is in the range of about 4,000 angstroms to about 5,000 angstroms thick; the ntype GaAs layer 62 is about 6,000 angstroms thick. Here, it is to be noted that the semiconductor device as produced in this process step corresponds to that of Fig.
3.
Although in this embodiment, the MOCVD method is employed, the Molecular Beam Epitaxial method may also be used for the same purpose.
Subsequently, a resist pattem 63 masking only a surface region of the n-type GaAs layer 62 at which the FET 32 is to be provided is formed by means of lithography, and by the use of the thus formed resist pattern 63 as a mask, doping of boron ions (B ions) are carried out to form the isolation region 41. The conditions for ion implantation or doping are the same as those for the aforementioned first embodiment. The semiconductor device as produced in this process step corresponds to that of the embodiment shown in Fig. 4.
Thereafter, the resist pattern 63 is removed, and a new resist pattem having apertures at locations corresponding to those portions at which the source electrode 40 and the drain electrode 39 are to be provided is formed at a portion of the surface of the active layer 36 surrounded by the isolation region 41. With the thus formed resist pattern used as a mask, the source electrode 40 and the drain electrode 39 are formed with aluminum by virtue of the deposition and lift-off method. The semiconductor device thus formed in this process step corresponds to that of Fig. 5.
A recess 37 is then formed in the active layer 36 or in the n-type semiconductor layer 35 by an etching process, and the gate electrode 38 is formed in the recess 37 by virtue of the vapor deposition and lift-off method.
Subsequently, the resist pattem 65 is removed1 and the via hole upper electrode 45 connected to the source electrode 40 is formed by means of the vapor deposition and lift-off method on a surface of the isolation region 41 at which the via hole 42 is later to be formed in contact therewith. Further, a resist is coated on the backside surface 602 of the GaAs substrate 60 opposite the first or front surface 601 thereof, and a resist pattern is formed which has an aperture at a location opposing the via hole upper electrode 45 by virtue of lithography. With the use of the thus formed resist pattem as a mask, portions of the GaAs substrate 60, the p-type GaAs layer 61 and the n-type GaAs layer 62 are removed by etching to such an extent as to expose the backside of the via hole upper electrode 45 to provide the via hole 42 surrounded by the inner wall 421. The etching liquid used here is sulfuric acid, for example.
Fig. 10 shows a partial cross section of a semiconductor device after such a via hole forming step has been finished.
After the formation of the via hole, an insulating film 70 formed of an electrically insulating material such as SiON is provided, by means of the CVD method for example, on the surface of the resist pattem 66 with a thickness of 500 angstroms and therearound, as shown in Fig. 11.
A part of the insulating film 70, which is in contact with the via hole upper electrode 45 , is selectively removed by means of the RIE method, after which the resist pattern 66 is also removed, and the backside a semiconductor device having a superior gate-source dielectric resistance which is less subject to degradation. In the manufacture of such a semiconductor device, the insulating layer 70 is formed with the resist pattern 66 left for formation of the via hole 42, and that part of the insulating layer 70 which is in contact with the via hole upper electrode 451 is removed from the backside of the wafer by the RIE method while taking advantage of the aperture in the resist pattern 66, so that a master pattern forming process step can be omitted, which would otherwise be required for partially removing an insulating layer to be formed after formation of the via hole. This serves to further simplify the entire manufacturing steps.
EXAMPLE 2 Figs. 13, 14 and 15 show respective process steps of a semiconductor manufacturing method in accordance with a second example of the present invention. In the manufacturing process of this example the process steps up to a step of forming a via hole 42 defined by an inner wall 421 are substantially the same as those in the first example.
After formation of the via hole 42, resist protruding from the periphery of the inner wall 421 of the via hole 42 is removed so as to coincide with the periphery of the via hole inner wall 421, whereby an aperture in the resist pattern 66 is rendered in consistence with the via hole 42. An insulating layer 70 of SiO or the like having a thickness of about 500 angstroms is formed from above the resist pattern 66 by means of a skewed or angled vapor deposition method on the inner wall 421 of the via hole 42 and on the p-type GaAs layer 61 excluding the exposed backside surface of the via hole upper electrode 45 while rotating the wafer, as shown in Figs. 14 and 15.
Subsequently, the resist pattem 66 is removed while leaving the insulating film 70 on the inner wall 421 of the via hole 42, and a backside electrode 43 is formed. by the electrolytic plating for example, on the second surface 602 of the GaAs substrate 60, the insulating film 70 remaining on the inner wall 421 of the via hole 42, and the exposed rear surface of the via hole upper electrode 45, as shown in Fig. 15.
According to the semiconductor manufacturing method of this exam p I e, the insulating film 70 is provided between the backside electrode 43 contacting the via hole upper electrode 45 and the p-type GaAs layer 61 constituting the buffer layer 34, so that no leakage current develops between the gate electrode 38 and the source electrode 40. Therefore, an excellent semiconductor device can be provided which has a never-degrading gate-source dielectric resistance characteristic. In the manufacture of such a semiconductor device, the aperture in the resist pattern 66 and the via hole 42 are made in coincidence with each other while leaving the resist pattern 66 for forming the via hole 42, and the insulating film 70 is then formed from above the resist pattern 66 by virtue of the skewed or angled vapor deposition method while rotating the wafer. With these process steps, the master pattern forming process for partially removing the insulating film to be formed after the formation of the via hole can be omitted, thus simplifying the entire manufacturing method.
Although in the above examples, the present invention is applied mainly to the FETs, it can also be applied to the GaAs-type or InP-type HEMTs which have a buffer layer composed of an electrically conductive semiconductor layer such as a p-type InGaAs layer, with the substantially same advantages.
Attention is directed to our co-pending application No. 9626387.6 (GB-A-2 311 652), from which the present application has been divided and which claims a semiconductor device comprising: a semiconductor substrate having a first surface and a second surface; a first semiconductor layer disposed on the first surface of the semiconductor substrate; a second semiconductor layer disposed on the first semiconductor layer and having a conductivity type opposite to that of the first semiconductor layer, the second semiconductor layer having a semiconductor element forming region and a remaining portion; a semiconductor element disposed in the semiconductor element forming region of the second semiconductor layer; an ion implanted region disposed in the remaining portion of the second semiconductor layer and isolating the semiconductor element forming region from the remaining portion of the second semiconductor layer; a via hole disposed in the remaining portion of the second semiconductor layer and extending from the second surface of the semiconductor substrate to a surface opposed to the second surface; isolation means interrupting the first and second semiconductor layers between the semiconductor element forming region and the via hole and having a depth extending from the second semiconductor layer through the first semiconductor layer, for isolating the via hole from the semiconductor element forming region; a conductive layer disposed on the inner wall of the via hole; and a wiring layer disposed on the said opposed surface and electrically connected to the conductive layer, the wiring layer being electrically connected to a portion of the semiconductor element across the isolation means.

Claims (3)

Claims:
1. A method of manufacturing a semiconductor device, comprising: (a) successively forming a first semiconductor layer and a second semiconductor layer on a first surface of a semiconductor substrate, the first and second semiconductor layers having opposite conductivity types; (b) forming a semiconductor element in a semiconductor element forming region of the second semiconductor layer; (c) forming a first resist pattern on the second semiconductor layer, the resist pattern covering the semiconductor element forming region; (d) implanting ions into the first and second semiconductor layers to electrically isolate the semiconductor element forming region from a remaining portion of the second semiconductor layer, using the first resist pattern as a mask; (e) forming a first wiring layer on the remaining portion of the second semiconductor layer and a second wiring layer extending from the first wiring layer to a portion of the semiconductor element; (f) forming a second resist pattern having an aperture on a second surface of the semiconductor substrate opposite to the first wiring layer; (g) removing by wet etching, a part of the semiconductor substrate from the second surface to the first wiring layer, thereby defining a hole; (h) depositing an insulating layer on the inner wall of the said hole from the second resist pattern, using the second resist pattern as a mask; (i) removing, by reactive ion etching, the insulating layer to expose the first wiring layer, using the second resist pattern as a mask; (j) removing the second resist pattern from the second surface of the semiconductor substrate; and (14 providing an electrically conductive layer on the exposed surface area of the first wiring layer at the side facing the said hole and on the insulating layer on the inner wall of the said hole.
2. A method as claimed in claim 1, wherein steps (h) and (i) are replaced by: (h') enlarging the said aperture in the second resist pattem to the end opening of the said hole at the second surface of the semiconductor substrate; and (i') depositing an insulating layer on the inner wall of the said hole, but not on an exposed surface area of the first wiring layer, from the second resist pattern, using the second resist pattern as a mask.
3. A method of manufacturing a semiconductor device substantially as hereinbefore described with reference to Example 1 or Example 2.
GB9725665A 1996-03-27 1996-12-19 Semiconductor device manufacture Expired - Fee Related GB2317500B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8072216A JPH09260405A (en) 1996-03-27 1996-03-27 Semiconductor device and manufacture thereof
GB9626387A GB2311652B (en) 1996-03-27 1996-12-19 Semiconductor device and method for manufacturing the same

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GB2317500A true GB2317500A (en) 1998-03-25
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03153057A (en) * 1989-11-10 1991-07-01 Mitsubishi Electric Corp Semiconductor device
GB2245424A (en) * 1990-06-05 1992-01-02 Mitsubishi Electric Corp Insulated via hole structure for semiconductor devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03153057A (en) * 1989-11-10 1991-07-01 Mitsubishi Electric Corp Semiconductor device
GB2245424A (en) * 1990-06-05 1992-01-02 Mitsubishi Electric Corp Insulated via hole structure for semiconductor devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Patent Abstracts of Japan, Vol 15, No 383 [E-1116] & JP 03 153 057 A *

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