CN117476749A - Pseudo-matched high electron mobility transistor and forming method thereof - Google Patents

Pseudo-matched high electron mobility transistor and forming method thereof Download PDF

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Publication number
CN117476749A
CN117476749A CN202311421171.7A CN202311421171A CN117476749A CN 117476749 A CN117476749 A CN 117476749A CN 202311421171 A CN202311421171 A CN 202311421171A CN 117476749 A CN117476749 A CN 117476749A
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layer
source
forming
drain metal
metal layer
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丁帼君
李新宇
赵亚楠
姜清华
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Changzhou Chengxin Semiconductor Co Ltd
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Changzhou Chengxin Semiconductor Co Ltd
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Priority to CN202311421171.7A priority Critical patent/CN117476749A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

A pseudomorphic high electron mobility transistor and method of forming the same, wherein the transistor comprises: an epitaxial structure comprising a substrate, a channel layer, a barrier layer, and a cap layer, the channel layer having opposite first and second sides; the first source drain metal layer is positioned on the cap layer and is positioned on the second side; a gate opening in the cap layer, the gate opening exposing a portion of a surface of the barrier layer; a gate metal layer within the gate opening; source and drain openings in the epitaxial structure, the source and drain openings exposing a portion of the surface of the channel layer; and the second source-drain metal layer is positioned in the source-drain opening and positioned on the first side. The first source drain metal layer and the second source drain metal layer are respectively formed on different sides of the channel layer, and the second source drain metal layer and the substrate are located on the same side of the channel layer, so that extra wiring of the second source drain metal layer to the ground can be effectively reduced, and parasitic parameters are further reduced.

Description

Pseudo-matched high electron mobility transistor and forming method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a pseudo-matched high electron mobility transistor and a forming method thereof.
Background
Pseudomorphic high electron mobility transistors (Pseudomorphic High Electron Transistor, pHEMT) are an improved structure for High Electron Mobility Transistors (HEMTs). That is, gallium arsenide (GaAs) channel layers in high electron mobility transistors are replaced by indium gallium arsenide (InGaAs), and there is about 1% lattice mismatch at the indium gallium arsenide interface, and such a thin film having lattice mismatch is called a pseudomorphic film. Such a high electron mobility transistor is therefore referred to as a pseudomorphic high electron mobility transistor.
The working principle of the pseudo-high electron mobility transistor is that the concentration of the two-dimensional electron gas (2-DEG) is controlled by voltage, so that the purpose of controlling drain current is achieved, and the most sensitive position of the control effect is located at the position of the two-dimensional electron gas. The electron mobility of a pseudomorphic high electron mobility transistor is very high because the electrons of the two-dimensional electron gas are spatially separated from the original donor impurity ions. At room temperature, the electron mobility of two-dimensional electron gas is 20 to 30% higher than that of gallium arsenic, while at low temperature, the former is 5 to 6 times higher than the latter. High electron mobility transistors and pseudomorphic high electron mobility transistors have superior performance to gallium arsenide Metal-semiconductor field effect transistors (MESFETs), exhibiting high saturation currents and high characteristic frequencies. Compared with a transistor with high electron mobility, the transistor with high electron mobility is pseudomorphic, and the InGaAs layer is used for replacing the GaAs layer, so that the conduction band discontinuity at the heterojunction InGaAs/AlGaAs (AlGaAs) interface is larger, the aggregation effect of two-dimensional electron gas in a heterojunction potential well is greatly improved, and higher two-dimensional electron gas concentration can be obtained, so that the electron mobility is higher.
However, there are still problems with pseudomorphic high electron mobility transistors.
Disclosure of Invention
The invention solves the problem of providing a pseudo-matched high electron mobility transistor and a forming method thereof, so as to reduce the generation and loss of parasitic parameters.
In order to solve the above problems, the present invention provides a pseudo-matching high electron mobility transistor, including: an epitaxial structure comprising a substrate, a channel layer, a barrier layer, and a cap layer, the channel layer having opposite first and second sides, the substrate being on the first side, the barrier layer and the cap layer being on the second side; the first source-drain metal layer is positioned on the cap layer, the first source-drain metal layer is positioned on the second side, and the first source-drain metal layer is in contact with the cap layer; a gate opening in the cap layer, the gate opening exposing a portion of a surface of the barrier layer; a gate metal layer within the gate opening, the gate metal layer in contact with the barrier layer; source and drain openings in the epitaxial structure, the source and drain openings exposing a portion of the surface of the channel layer; and the second source-drain metal layer is positioned in the source-drain opening, is positioned on the first side and is in contact with the channel layer.
Optionally, the method further comprises: and the protective layer is positioned on the side wall of the source drain opening.
Optionally, the material of the protective layer includes: one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, aluminum oxide, and aluminum nitride.
Optionally, the second source drain metal layer includes a single-layer structure or a multi-layer structure.
Optionally, when the second source drain metal layer has a single layer structure, the material of the second source drain metal layer includes: gold; when the second source drain metal layer is of a multi-layer structure, the materials of the second source drain metal layer include sequentially stacked: gold-germanium alloy, nickel, gold.
Optionally, the epitaxial structure further includes: the substrate, the buffer layer, the first isolation layer, the channel layer, the second isolation layer, the barrier layer and the cap layer are sequentially stacked, the buffer layer and the first isolation layer are located on the first side, and the second isolation layer is located on the second side; the source-drain opening is located in the substrate, the buffer layer and the first isolation layer.
Correspondingly, the invention also provides a method for forming the pseudo-matched high electron mobility transistor, which comprises the following steps: forming an epitaxial structure, the forming the epitaxial structure comprising: forming a substrate, a channel layer, a barrier layer, and a cap layer, the channel layer having opposite first and second sides, the substrate being formed on the first side, the barrier layer and the cap layer being formed on the second side; forming a first source drain metal layer on the cap layer, wherein the first source drain metal layer is positioned on the second side, and the first source drain metal layer is in contact with the cap layer; etching part of the cap layer from the second side to the first side until the surface of the barrier layer is exposed, and forming a gate opening in the cap layer; forming a gate metal layer in the gate opening, the gate metal layer being in contact with the barrier layer; etching the epitaxial structure from the first side to the second side until the surface of the channel layer is exposed, and forming a source drain opening in the epitaxial structure; and forming a second source-drain metal layer in the source-drain opening, wherein the second source-drain metal layer is positioned on the first side, and the second source-drain metal layer is in contact with the channel layer.
Optionally, after forming the source-drain openings and before forming the second source-drain metal layer, the method further includes: and forming a protective layer on the side wall of the source drain opening.
Optionally, the forming method of the protective layer includes: forming a protective material layer on the side wall and the bottom surface of the source drain opening and the surface of the substrate; and etching the protective material layer until the surface of the substrate and the bottom surface of the source drain opening are exposed, so as to form the protective layer.
Optionally, the material of the protective layer includes: one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, aluminum oxide, and aluminum nitride.
Optionally, the forming method of the second source drain metal layer includes: forming a third photoresist layer on the substrate, wherein the third photoresist layer exposes the source drain openings; forming a second source drain metal material layer on the surface of the third photoresist layer and in the source drain opening; and removing the third photoresist layer and the second source drain metal material layer positioned on the surface of the third photoresist layer to form the second source drain metal layer.
Optionally, the second source drain metal layer includes a single-layer structure or a multi-layer structure.
Optionally, when the second source drain metal layer has a single layer structure, the material of the second source drain metal layer includes: gold; when the second source drain metal layer is of a multi-layer structure, the materials of the second source drain metal layer include sequentially stacked: gold-germanium alloy, nickel, gold.
Optionally, forming the epitaxial structure further includes: forming a buffer layer, a first isolation layer and a second isolation layer, wherein the formed substrate, the buffer layer, the first isolation layer, the channel layer, the second isolation layer, the barrier layer and the cap layer are sequentially stacked, the buffer layer and the first isolation layer are formed on the first side, and the second isolation layer is formed on the second side; the method for forming the source drain opening comprises the following steps: and etching the substrate, the buffer layer and the first isolation layer in sequence from the first side to the second side until the surface of the channel layer is exposed, and forming source and drain openings in the substrate, the buffer layer and the first isolation layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the pseudo-matching high electron mobility transistor of the technical scheme of the invention, the pseudo-matching high electron mobility transistor comprises: a second source-drain metal layer located within the source-drain opening, the second source-drain metal layer located on the first side, and the second source-drain metal layer in contact with the channel layer; the first source drain metal layer is located on the second side. By forming the first source drain metal layer and the second source drain metal layer on different sides of the channel layer respectively, and the second source drain metal layer and the substrate are located on the same side of the channel layer, additional routing of the second source drain metal layer to the ground can be effectively reduced, and parasitic parameters are further reduced.
In the method for forming the pseudo-matching high electron mobility transistor, a second source-drain metal layer is formed in the source-drain opening, the second source-drain metal layer is located on the first side, and the second source-drain metal layer is in contact with the channel layer; the first source drain metal layer is formed on the second side. By forming the first source drain metal layer and the second source drain metal layer on different sides of the channel layer respectively, and the second source drain metal layer and the substrate are located on the same side of the channel layer, additional routing of the second source drain metal layer to the ground can be effectively reduced, and parasitic parameters are further reduced.
Drawings
FIG. 1 is a schematic diagram of a structure of a pseudomorphic HEMT;
fig. 2 to 8 are schematic structural diagrams illustrating steps of a method for forming a pseudo-configured hemt according to an embodiment of the present invention.
Detailed Description
As described in the background, there are still problems with pseudomorphic high electron mobility transistors. The following will make a detailed description with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a structure of a pseudomorphic high electron mobility transistor.
Referring to fig. 1, a pseudo-matching hemt, comprising: an epitaxial structure comprising a substrate 100, a buffer layer 101, a first isolation layer 102, a channel layer 103, a second isolation layer 104, a barrier layer 105, and a cap layer 106 stacked in this order, the channel layer 103 having opposite first and second sides 103a, 103b, the substrate 100, the buffer layer 101, and the first isolation layer 102 being located on the first side 103a, the second isolation layer 104, the barrier layer 105, and the cap layer 106 being located on the second side 103b; a first source drain metal layer 107 and a second source drain metal layer 108 on the cap layer 106, the first source drain metal layer 107 and the second source drain metal layer 108 being on the second side 103b, and the first source drain metal layer 107 and the second source drain metal layer 108 being in contact with the cap layer 106, respectively; a gate opening (not shown) in the cap layer 106, the gate opening being located between the first source drain metal layer 107 and the second source drain metal layer 108, the gate opening exposing a portion of the surface of the barrier layer 105; a gate metal layer 109 located within the gate opening, the gate metal layer 109 being in contact with the barrier layer 105.
With continued reference to fig. 1, in this embodiment, the gate metal layer 109 applies a voltage to turn on the channel layer 103, and current needs to be connected from the first source-drain metal layer 107, then flows to the second source-drain metal layer 108 through the channel layer 103, and finally the second source-drain metal layer 108 is grounded. However, the grounded position is located in the substrate 100 on the first side 103a, and the second source-drain metal layer 108 is located on the second side 103b, so that an additional metal wiring is required to reach the current flow, i.e. the second source-drain metal layer 108 needs an additional wiring for grounding, thereby generating parasitic parameters and increasing the loss.
On the basis, the invention provides a pseudo-matched high electron mobility transistor and a forming method thereof, wherein the first source drain metal layer and the second source drain metal layer are respectively formed on different sides of the channel layer, and the second source drain metal layer and the substrate are positioned on the same side of the channel layer, so that extra wiring of the second source drain metal layer to the ground can be effectively reduced, and generation and loss of parasitic parameters are further reduced.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than as described herein, and therefore the present invention is not limited to the specific embodiments disclosed below.
Fig. 2 to 8 are schematic structural diagrams illustrating steps of a method for forming a pseudo-configured hemt according to an embodiment of the present invention.
Referring to fig. 2, forming an epitaxial structure includes: a substrate 200, a channel layer 203, a barrier layer 205, and a cap layer 206 are formed, the channel layer 203 having opposite first and second sides 203a, 203b, the substrate 200 being formed on the first side 203a, the barrier layer 205 and the cap layer 206 being formed on the second side 203b.
Forming the epitaxial structure further includes: forming a buffer layer 201, a first isolation layer 202, and a second isolation layer 204; the substrate 200, the buffer layer 201, the first isolation layer 202, the channel layer 203, the second isolation layer 204, the barrier layer 205, and the cap layer 206 are sequentially stacked, the buffer layer 201 and the first isolation layer 202 are formed on the first side 203a, and the second isolation layer 204 is formed on the second side 203b.
The materials of the substrate 200 include: gallium arsenide (GaAs).
The materials of the buffer layer 201 include: aluminum gallium arsenide (AlGaAs) or gallium arsenide.
The materials of the first isolation layer 202 include: aluminum gallium arsenic.
The materials of the channel layer 203 include: indium gallium arsenic.
The materials of the second isolation layer 204 include: aluminum gallium arsenic.
The materials of the barrier layer 205 include: indium gallium phosphorus (AlGaP).
The materials of the cap layer 206 include: gallium arsenide.
Ions of the same electrical type (e.g., N-type ions) are doped in the channel layer 203, the second isolation layer 204, the barrier layer 205, and the cap layer 206; while the substrate 200, the buffer layer 201 and the first isolation layer 202 are not doped with ions.
Referring to fig. 3, a first source-drain metal layer 207 is formed on the cap layer 206, the first source-drain metal layer 207 is located on the second side 203b, and the first source-drain metal layer 207 is in contact with the cap layer 206.
The method for forming the first source drain metal layer 207 includes: forming a first photoresist layer (not shown) on the cap layer 206, the first photoresist layer exposing a portion of a surface of the cap layer 206; forming a first source-drain metal material layer (not shown) on the surface of the first photoresist layer and the exposed surface of the cap layer 206 by adopting an evaporation process; the first photoresist layer and the first source drain metal material layer on the surface of the first photoresist layer are removed, so as to form the first source drain metal layer 207.
The first source drain metal layer 207 includes a single layer structure or a multi-layer structure.
In this embodiment, the first source-drain metal layer 207 is a multi-layer structure, and the materials of the first source-drain metal layer 207 include sequentially stacked: gold-germanium alloy, nickel, gold.
In other embodiments, when the first source drain metal layer has a single layer structure, the material of the first source drain metal layer includes: gold.
In this embodiment, the first source drain metal layer 207 will serve as the source of the transistor structure; in other embodiments, the first source drain metal layer may also serve as a drain for a transistor structure.
Referring to fig. 4, a portion of the cap layer 206 is etched from the second side 203b to the first side 203a until the surface of the barrier layer 205 is exposed, and a gate opening 208 is formed in the cap layer 206.
In this embodiment, the gate opening 208 is formed after the first source-drain metal layer 207 is formed, and the corresponding forming method of the gate opening 208 includes: forming a first mask layer (not shown) on the cap layer 206, the first mask layer covering the first source drain metal layer 207 and exposing a portion of the surface of the cap layer 206; the cap layer 206 is etched using the first mask layer as a mask until the barrier layer 205 is exposed, forming the gate opening 208.
In other embodiments, the gate opening may be formed first, and then the first source-drain metal layer may be formed, where the corresponding method for forming the gate opening includes: forming a first mask layer (not shown) on the cap layer, the first mask layer exposing a portion of a surface of the cap layer; and etching the cap layer by taking the first mask layer as a mask until the barrier layer is exposed, so as to form the grid electrode opening.
Referring to fig. 5, a gate metal layer 209 is formed in the gate opening 208, and the gate metal layer 209 is in contact with the barrier layer 205.
In this embodiment, the gate metal layer 209 is formed after the first source-drain metal layer 207 is formed, and the corresponding method for forming the gate metal layer 209 includes: forming a second photoresist layer (not shown) on the cap layer 206, the second photoresist layer covering the first source drain metal layer 207 and exposing the gate opening 208; forming a gate metal material layer (not shown) on the surface of the second photoresist layer and in the gate opening 208 by an evaporation process; and removing the second photoresist layer and the gate metal material layer on the surface of the second photoresist layer to form the gate metal layer 209.
In other embodiments, the gate metal layer may be formed first, and then the first source-drain metal layer may be formed, where the corresponding method for forming the gate metal layer includes: forming a second photoresist layer (not shown) on the cap layer, the second photoresist layer exposing the gate opening; forming a gate metal material layer (not shown) on the surface of the second photoresist layer and in the gate opening by adopting an evaporation process; and removing the second photoresist layer and the gate metal material layer positioned on the surface of the second photoresist layer to form the gate metal layer.
The gate metal layer 209 has a multilayer structure; the gate metal layer 209 comprises materials stacked in sequence: platinum, titanium and gold.
Referring to fig. 6, the epitaxial structure is etched from the first side 203a to the second side 203b until the surface of the channel layer 203 is exposed, and source-drain openings 210 are formed in the epitaxial structure.
The source-drain openings 210 are formed in the substrate 200, the buffer layer 201 and the first isolation layer 202; the method for forming the source drain opening 210 includes: the substrate 200, the buffer layer 201 and the first isolation layer 202 are etched in sequence from the first side 203a to the second side 203b until the surface of the channel layer 203 is exposed, and the source-drain openings 210 are formed in the substrate 200, the buffer layer 201 and the first isolation layer 202.
The method for forming the source-drain openings 210 includes: forming a second mask layer on the substrate 200, wherein the second mask layer exposes a part of the surface of the substrate 200; the second mask layer is used as a mask to etch the substrate 200, the buffer layer 201 and the first isolation layer 202 until the channel layer 203 is exposed, so as to form the source-drain openings 210.
Referring to fig. 7, a passivation layer 211 is formed on the sidewall of the source/drain opening 210.
The method for forming the protective layer 211 includes: forming a protective material layer (not shown) on the sidewall and bottom surfaces of the source drain opening 210 and the surface of the substrate 200; the protective material layer is etched back until the surface of the substrate 200 and the bottom surface of the source drain opening 210 are exposed, so as to form the protective layer 211.
The material of the protective layer 211 includes: one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, aluminum oxide, and aluminum nitride.
The protective layer 211 is used for electrically isolating the second source-drain metal layer formed later from the substrate 200, the buffer layer 201 and the first isolation layer 202, respectively.
Referring to fig. 8, a second source-drain metal layer 212 is formed in the source-drain opening 210, the second source-drain metal layer 212 is located on the first side 203a, and the second source-drain metal layer 212 contacts the channel layer 203.
By forming the first source-drain metal layer 207 and the second source-drain metal layer 212 on different sides of the channel layer 203, respectively, and forming the second source-drain metal layer 212 on the same side of the channel layer 203 as the substrate 200, additional routing of the second source-drain metal layer 212 to ground can be reduced, thereby reducing parasitic parameter generation and loss.
The forming method of the second source drain metal layer 212 includes: forming a third photoresist layer (not shown) on the substrate 200, the third photoresist layer exposing the source drain openings 210; forming a second source drain metal material layer (not shown) on the surface of the third photoresist layer and in the source drain openings 210 by adopting an evaporation process; and removing the third photoresist layer and the second source drain metal material layer on the surface of the third photoresist layer to form the second source drain metal layer 212.
The second source drain metal layer 212 includes a single layer structure or a multi-layer structure.
In this embodiment, the second source-drain metal layer 212 has a multi-layer structure, and the materials of the second source-drain metal layer 212 include sequentially stacked: gold-germanium alloy, nickel, gold.
In other embodiments, when the second source drain metal layer has a single layer structure, the material of the second source drain metal layer includes: gold.
In this embodiment, the second source drain metal layer 212 will be the drain of the transistor structure; in other embodiments, if the first source-drain metal layer is used as the drain of the transistor structure, the second source-drain metal layer will be used as the source of the transistor structure.
Accordingly, in an embodiment of the present invention, a pseudo-configured hemt is further provided, please continue to refer to fig. 8, including: an epitaxial structure comprising a substrate 200, a channel layer 203, a barrier layer 205, and a cap layer 206, the channel layer 203 having opposite first and second sides 203a, 203b, the substrate 200, the buffer layer 201, and the first isolation layer 202 being located on the first side 203a, the second isolation layer 204, the barrier layer 205, and the cap layer 206 being located on the second side 203b; a first source drain metal layer 207 on the cap layer 206, the first source drain metal layer 207 being on the second side 203b, and the first source drain metal layer 207 being in contact with the cap layer 206; a gate opening 208 located within the cap layer 206, the gate opening 208 exposing a portion of the surface of the barrier layer 205; a gate metal layer 209 located within the gate opening 208, the gate metal layer 209 being in contact with the barrier layer 205; a source-drain opening 210 located in the epitaxial structure, wherein the source-drain opening 210 exposes a portion of the surface of the channel layer 203; a second source-drain metal layer 212 located within the source-drain opening 210, the second source-drain metal layer 212 being located on the first side 203a, and the second source-drain metal layer 212 being in contact with the channel layer 203.
By forming the first source-drain metal layer 207 and the second source-drain metal layer 212 on different sides of the channel layer 203, respectively, and forming the second source-drain metal layer 212 on the same side of the channel layer 203 as the substrate 200, additional routing of the second source-drain metal layer 212 to ground can be reduced, thereby reducing parasitic parameter generation and loss.
The first source drain metal layer 207 includes a single layer structure or a multi-layer structure.
In this embodiment, the first source-drain metal layer 207 is a multi-layer structure, and the materials of the first source-drain metal layer 207 include sequentially stacked: gold-germanium alloy, nickel, gold.
In other embodiments, when the first source drain metal layer has a single layer structure, the material of the first source drain metal layer includes: gold.
The gate metal layer 209 has a multilayer structure; the gate metal layer 209 comprises materials stacked in sequence: platinum, titanium and gold.
The pseudomorphic high electron mobility transistor further comprises: and a protection layer 211 located on the side wall of the source drain opening 210.
The material of the protective layer 211 includes: one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, aluminum oxide, and aluminum nitride.
The second source drain metal layer 212 includes a single layer structure or a multi-layer structure.
In this embodiment, the second source-drain metal layer 212 has a multi-layer structure, and the materials of the second source-drain metal layer 212 include sequentially stacked: gold-germanium alloy, nickel, gold.
In other embodiments, when the second source drain metal layer has a single layer structure, the material of the second source drain metal layer includes: gold.
The epitaxial structure further includes: the substrate 200, the buffer layer 201, the first isolation layer 202, the channel layer 203, the second isolation layer 204, the barrier layer 205, and the cap layer 206 are stacked in this order, the buffer layer 201 and the first isolation layer 202 being located at the first side 203a, and the second isolation layer 204 being located at the second side 203b.
The source-drain openings 210 are located in the substrate 200, the buffer layer 201 and the first isolation layer 202.
It should be understood that the examples and embodiments herein are illustrative only and that various modifications and changes can be made by one skilled in the art without departing from the spirit and scope of the invention as defined by the application and the appended claims.

Claims (14)

1. A pseudomorphic high electron mobility transistor, comprising:
an epitaxial structure comprising a substrate, a channel layer, a barrier layer, and a cap layer, the channel layer having opposite first and second sides, the substrate being on the first side, the barrier layer and the cap layer being on the second side;
the first source-drain metal layer is positioned on the cap layer, the first source-drain metal layer is positioned on the second side, and the first source-drain metal layer is in contact with the cap layer;
a gate opening in the cap layer, the gate opening exposing a portion of a surface of the barrier layer;
a gate metal layer within the gate opening, the gate metal layer in contact with the barrier layer;
source and drain openings in the epitaxial structure, the source and drain openings exposing a portion of the surface of the channel layer;
and the second source-drain metal layer is positioned in the source-drain opening, is positioned on the first side and is in contact with the channel layer.
2. The pseudomorphic high electron mobility transistor of claim 1 further comprising: and the protective layer is positioned on the side wall of the source drain opening.
3. The pseudomorphic high electron mobility transistor of claim 2 wherein the material of the protective layer comprises: one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, aluminum oxide, and aluminum nitride.
4. The pseudomorphic high electron mobility transistor of claim 1 wherein the second source drain metal layer comprises a single layer structure or a multi-layer structure.
5. The pseudomorphic high electron mobility transistor of claim 4 wherein when the second source drain metal layer is of single layer construction, the material of the second source drain metal layer comprises: gold; when the second source drain metal layer is of a multi-layer structure, the materials of the second source drain metal layer include sequentially stacked: gold-germanium alloy, nickel, gold.
6. The pseudomorphic high electron mobility transistor of claim 1 wherein said epitaxial structure further comprises: the substrate, the buffer layer, the first isolation layer, the channel layer, the second isolation layer, the barrier layer and the cap layer are sequentially stacked, the buffer layer and the first isolation layer are located on the first side, and the second isolation layer is located on the second side; the source-drain opening is located in the substrate, the buffer layer and the first isolation layer.
7. A method of forming a pseudomorphic high electron mobility transistor, comprising:
forming an epitaxial structure, the forming the epitaxial structure comprising: forming a substrate, a channel layer, a barrier layer, and a cap layer, the channel layer having opposite first and second sides, the substrate being formed on the first side, the barrier layer and the cap layer being formed on the second side;
forming a first source drain metal layer on the cap layer, wherein the first source drain metal layer is positioned on the second side, and the first source drain metal layer is in contact with the cap layer;
etching part of the cap layer from the second side to the first side until the surface of the barrier layer is exposed, and forming a gate opening in the cap layer;
forming a gate metal layer in the gate opening, the gate metal layer being in contact with the barrier layer;
etching the epitaxial structure from the first side to the second side until the surface of the channel layer is exposed, and forming a source drain opening in the epitaxial structure;
and forming a second source-drain metal layer in the source-drain opening, wherein the second source-drain metal layer is positioned on the first side, and the second source-drain metal layer is in contact with the channel layer.
8. The method of forming a pseudomorphic high electron mobility transistor of claim 7 wherein after forming the source drain openings and before forming the second source drain metal layer further comprises:
and forming a protective layer on the side wall of the source drain opening.
9. The method of forming a pseudomorphic high electron mobility transistor of claim 8 wherein the method of forming a protective layer comprises: forming a protective material layer on the side wall and the bottom surface of the source drain opening and the surface of the substrate; and etching the protective material layer until the surface of the substrate and the bottom surface of the source drain opening are exposed, so as to form the protective layer.
10. The method of forming a pseudomorphic high electron mobility transistor of claim 8 wherein the material of the protective layer comprises: one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, aluminum oxide, and aluminum nitride.
11. The method of forming a pseudomorphic high electron mobility transistor of claim 8 wherein the second source drain metal layer forming method comprises: forming a third photoresist layer on the substrate, wherein the third photoresist layer exposes the source drain openings; forming a second source drain metal material layer on the surface of the third photoresist layer and in the source drain opening; and removing the third photoresist layer and the second source drain metal material layer positioned on the surface of the third photoresist layer to form the second source drain metal layer.
12. The method of forming a pseudomorphic high electron mobility transistor of claim 11 wherein the second source drain metal layer comprises a single layer structure or a multi-layer structure.
13. The method of forming a pseudomorphic high electron mobility transistor of claim 12 wherein when the second source drain metal layer is of a single layer structure, the material of the second source drain metal layer comprises: gold; when the second source drain metal layer is of a multi-layer structure, the materials of the second source drain metal layer include sequentially stacked: gold-germanium alloy, nickel, gold.
14. The method of forming a pseudomorphic high electron mobility transistor of claim 7 wherein forming the epitaxial structure further comprises: forming a buffer layer, a first isolation layer and a second isolation layer, wherein the formed substrate, the buffer layer, the first isolation layer, the channel layer, the second isolation layer, the barrier layer and the cap layer are sequentially stacked, the buffer layer and the first isolation layer are formed on the first side, and the second isolation layer is formed on the second side; the method for forming the source drain opening comprises the following steps: and etching the substrate, the buffer layer and the first isolation layer in sequence from the first side to the second side until the surface of the channel layer is exposed, and forming source and drain openings in the substrate, the buffer layer and the first isolation layer.
CN202311421171.7A 2023-10-27 2023-10-27 Pseudo-matched high electron mobility transistor and forming method thereof Pending CN117476749A (en)

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