GB2304942A - Indirect decoding and control device - Google Patents

Abstract

An indirect decoding and control device used in a microprocessor system uses control registers 4 as a buffer to separate a processor 3 and peripheral equipment 2, , thereby allowing the microprocessor to indirectly control the peripheral equipment. Re-definition of individual bits in the registers 4 allows changes in the processor 3 or peripheral equipment 2 to be accommodated readily.

Description

TITLE: INDIRECT-DECODING CONTROL DEVICE BACKGROUND OF THE INVENTION The present invention relates to an indirectdecoding control device, and in particular, to a decoding control device whereby the operations of the microprocessor and the peripheral equipments can be controlled separately.

The conventional microprocessor control manner is as shown in Fig. 11 which utilizes an instruction decoding circuit 1 to generate decoded control signals to control the peripheral equipment 2. Each of the contra activities of the peripheral equipment 2 has a corresponding control signal, or a corresponding instruction code. Therefore, through the instructions, the control signals received by the peripheral equipment can be ascertained, and the execution of the corresponding instructions will control specific functions. The instructions, however, must necessarily be adjusted with the changes of the controlled functions of the peripheral equipments. This means that not only the peripheral circuits will change, but the instruction table must also be rearranged accordingly.Also, the decoding circuits must be re-designed and the the arrangement of the timing diagram should be reassessed.

Without question, this increases the designer's burden, and at the same time, increases the risks of mistakes.

SUMMARY OF THE PRESENT INVENTION The object of the present invention is to provide an indirect-decoding control device to solve the above shortcomings of the known technology.

In accordance with the present invention, the decoding control device is divided into two parts: one is for controlling the microprocessor and the other is for controlling the peripheral functions. Therefore, the microprocessor only manages the controls of the microprocessor itself and the I/O, set, clear, compare, etc., control of the register. The microprocessor does not concern itself with the type of the peripheral equipments controlled by the control registers.

Therefore, it is no more necessary to amend the instructions for controlling the peripheral equipments when the control functions of the peripheral equipment are changed.

Brief DescriPtion of the Drains Fig. 1 shows a schematic diagram of an indirectdecoding control device in accordance with the present invention; Fig. 2 shows the block diagram of the indirectdecoding control device of Fig. 1; Fig. 3 shows the structural diagram for the implementation of the present invention; Fig. 4 is a core view of the implementation for the present invention; Fig. 5 is the schematic diagram of the peripherals for the implementation of the present invention; Fig.s 6A-6B to 10 show the circuit diagrams of the embodiments of the present invention, respectively; Fig. 11 shows a schematic diagram of a conventional decoding control device; and Fig. 12 shows the adjustments made on logic circuits after timer function is added to the known technology.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT As shown in Fig. 1, the indirect-decoding control device of the present invention mainly comprises an instruction decoding circuit 1. Instruction codes are input to the instruction decoding circuit 1 for processing. Then the instruction decoding circuit 1 outputs a plurality of control signals. In accordance with the present invention, the control signals are divided into two parts: one part is for controlling a microprocessor 3, while the other part is for controlling peripheral equipments 2.

In Fig. 1, the control signals of the microprocessor 3 and the peripheral equipment 2 are separately positioned. The instruction decoding circuit 1 and peripheral equipment 2 are further separated by a control register 4, as shown in Fig. 2.

According to the arrangement of the control signals, the microprocessor 3 only manages the controls of the microprocessor itself and controls the I/O, set, clear, compare, etc., of the control register 4, but not concerns with what type the peripheral equipment 2 controlled by the control registers 4 is. The Peripheral equipments 2 receive the control of the control registers 4 and functions according to the meaning represented by the individual bits of the control registers 4. The results are reported back to the control register 4.

According to the manner as disclosed above, once the peripheral equipment 2 is changed, only the definitions represented by the individual bits of the control register 4 need to be re-defined. These re-defined bits may then be used to control the peripheral equipment 2.

Since none of the components in the microprocessor part is changed, changes are not needed. If the micropmcessor needs to be changed, this does not influence the peripheral equipment 2. Therefore, the factors that must be considered have decreased, and furthermore, by not changing the peripheral equipment 2 at all, the likelihood of a mistake is greatly decreased.

Furthermore, the peripheral equipment 2 may function independently, which greatly increases the ability for implantation.

The special characteristics and attributes of the present invention are more clearly shown in the following implementations and explanations.

Please refer to tables I-IV, when peripheral functions need to be changed, for example, the addition of a timer function, then the instructions must accordingly be changed. Table I discloses the four instruction definitions if a timer function is to be added.

Table I

41 STRTT START TIMER COURT 42 STOPT STOP TIMER COUNT 43 LTMRL LOAD TIMER LOWER 4-BIT TO ACC ACC -- TMR LOWER 4-BIT 44 LTMRH LOAD TIMER HIGHER 4-BIT TO AC ACT THOR HIGHER 4-BIT Table II provides definitions to the ON/OFF of the timer.

Table II

TIMER ON STRTTB(OT1) - STRTT(2T) TIMER OFF STOPTB(OT1) ----- STOPT(2T) Table III is an instruction table, showing the positions in the instruction table for the instructions to be added. In conventional technologies, an instruction table must be re-arranged (adjusted or even deletion of the original instructions) in order to accommodate the addition of the new instructions.

Table III Le 0 1 2 3 4 5 6 7 8 9 A B C D E F H1 0 ADCM SPEO SPE1 OPER++ SPE2 STOPT STRTT CPE3 SPE3 IPE OPE CPE2 TPD CPE1 CPEO DEC 1 ADDM SPG0 SPG1 AND SPG2 SR0 SR1 CPG3 SPG3 IPG OPG CPG2 TPE CPG1 CPG0 DR0 2 ADC SPD0 SPD1 OR SPD2 LTMRL LROM CPD3 SPD3 IPD OPD CPD2 IPF CPD1 CPD0 3 ADD SM0 SM1 XOR SM2 HLT+ LTMRH CM3 SM3 LDA STA CM2 OPA CM1 CM0 CPLA 4 LR0@ 5 6 LAI 7 ADDI 8 LDAM 9 A STAM B C ANDM INC JA0++ JA1++ JA2++ JA3++ JZ++ JPE0++ JPE1++ JPE2++ JPE3++ D ROM IPO JNA0++ JNA1++ JNA2++ JNA3++ JNZ++ JPG0++ JPG1++ JPG2++ JPG3++ E XORM CLRWD RCF SCF JMO++ JM1++ MJ2++ JM3++ JC++ TBMA+ F NOP BRLRI STRWD STOPWD JNMO++ JNM1++ JNM2++ JNM3++ JNC++ JMP++ The dotted block in Fig. 12 depicts the changes in logic circuitry for the addition of the timer function in the conventional decoding control device.

Table IV is the definition for the timer function after re-designing the decoding circuitry as shown in Fig. 12 and Tables I-III.

Table IV

TIMER ON Set TIMER start count 1 1 TIMER OFF Set TIMER stop count 1 1 MOV A,TMRL Move (TIMER) lower 4 bits to accumulator I I Ace --- (TIMER) bit 3-0 MOV A,TNRH Move(TIMER) higher 4 bits to accumulator I 1 Ace --- (TIMER) bit 7-4 Please note that for the above changes, the adjustments to the decoding circuitry as shown in Fig. 12 are most susceptible to mistakes.This is because the decoding circuitry is the core of the microprocessor.

Once changed, the timing and layout must be re-evaluated, or the IC will function abnormally. For known technologies, once the peripheral equipment is changed, the above adjusting procedures must be repeated, and thereby taking the same risk of abnormal IC performance.

In contrary, in accordance with the indirect decoding control manner of the present invention, as shown in Fig.s 2 and 3, the microprocessor 3 does not directly control the peripheral equipment 2 but instead uses a set of registers 4 as buffer means. The buffer means divide the entire microprocessor into two parts: core and peripheral.

Please refer to Fig. 4, within the core part, the microprocessor only reads from and writes to the registers 4, and the constancy of which decreases the likelihood of a mistake.

Please also refer to Fig. 5, within the peripheral part, the peripheral equipment is only controlled by the registers 4. The peripherals are not affected by the types of microprocessors used to read from or write to the registers. Therefore, applications to various microprocessors are possible without re-designs.

The core part only comes in contact with the set of registers. When the peripherals are different, the definitions of the corresponding bits will also be different. During program designs, only definitions need to be given to the R/W of the registers. As far as the hardware circuitry is concerned, regardless of which peripheral is used, the core can remain unchanged.

Therefore, once the core has proven to be functioning properly, no adjustments are needed, and thereby decreasing the possibility of a mistake.

For the peripheral part, the control signals originate from the control registers, and how the register signals are defined, read and written are completely unrelated to the peripheral equipment. All that is required of the peripheral equipment is for it to function according to the corresponding control signals from the registers 4. Thus, the capability of implantation may be increased. Re-designs are not needed for different applications of the same peripheral equipment. Not only does this save time and cost of designs, but decrease the number of mistakes.

Fig.s 6A and 6B are the detailed circuit diagram of the indirect-decoding control device of the present invention. This circuitry is responsible for decoding all R/W signals in the registers. In order to control TMRCKT after it is added to the microprocessor circuit, two sets of decoding circuits of R/W signals of the register circuits as described above are added to the REGDEC. In fact, these decoding circuits may be distributed all over the peripheral circuits. Therefore, all the address lines of the registers must reach each peripheral. Fig. 7 is the block distribution circuit of the REGD of Figs. 6A and 6B.

Fig. 8 shows the upper view of the timer circuit.

In order to control the timer, the R/W signals (Rl3R23TB, R14R23TB, R13W234T, R14W234T) of R13 and Rl4 are pulled out.

Fig. 9 shows the circuitry of the timer. The circuit includes two sets of registers; one is for the timer (TMR) and the other one is for the control register (the row of latches shown on the right upper portion of the circuit), and the register addresses are R13 and R14.

Fig. 10 shows the block diagram of the TMR shown in the timer circuitry of Fig. 9.

It will be understood that persons skilled in the art, after reading the explanations of the above instances of implementations and drawings, will be able to make changes but will be within the spirit and scope of this invention. The scope of the claims is as follows:

Claims (3)

I CLAIM

1. An indirect-decoding control device used in a microprocessor system, said decoding control device comprising: an instruction decoding circuit being used to decode input instructions which outputs a plurality of control signals to a microprocessor and a number of peripheral equipments, respectively; said microprocessor for managing said control signals output from said instruction decoding circuit and providing instructions to said instruction decoding circuit; and a number of registers each being positioned between said instruction decoding circuit and one of said peripheral equipments; said register being functioning as a buffer between said microprocessor and said peripheral equipment thereby resulting in mutual independence of said microprocessor controls and peripheral functions.

2. An indirect decoding control device as claimed in Claim 1, wherein the functions of said peripheral equipments are represented by individual bytes from said register.

3. An indirect decoding control device as claimed in Claim 1, wherein said microprocessor only manages the controls of said microprocessor and the I/O, set, clear, compare, etc., controls of said register.