GB2300496A

GB2300496A - Data processing system

Info

Publication number: GB2300496A
Application number: GB9508814A
Authority: GB
Inventors: Michael Ellerbrock
Original assignee: Motorola GmbH
Current assignee: Motorola Solutions Germany GmbH
Priority date: 1995-05-01
Filing date: 1995-05-01
Publication date: 1996-11-06
Also published as: GB9508814D0

Abstract

A data processing system includes a processor 140 arranged to execute a set of instructions, and to provide output data which indicates the execution of each instruction and a history memory 100 having first and second memory portions 110, 120, The history memory sequentially receives and stores the output data. A control arrangement selects one of the memory portions to store the output data, and is also arranged to identify the occurrence of an error in the execution of the instructions. If an error occurs, the control arrangement selects the other memory portion.

Description

DATA PROCESSING SYSTEM Field of the Invention This invention relates to data processing systems and particularly but not exclusively to error detection in data processing systems.

Background of the Invention In data processing systems, such as microprocessor based systems, sets of instructions or tasks (programs) are performed by a microprocessor of the system according to a program or routine. Errors such as hardware related errors or memory errors, which may occur during execution of the program are often hard to find, especially in extensive and complicated programs.

Furthermore, where such errors cause the program to crash, and it is not apparent at which stage of the program execution the crash has occurred, the task of finding the error or errors is compounded.

Known methods of detecting errors include the storing of instruction related data in a history buffer, such that if an error arises, the buffer may be subsequently interrogated to determine whereabouts in the program the error occurred.

A problem with this arrangement is that in many applications, the program restarts after an error, and immediately overwrites the history buffer.

This invention seeks to provide a data processing system which mitigates the above mentioned disadvantages.

Summarv of the Invention According to the present invention there is provided a data processing system, for processing data according to a set of instructions, comprising: a processor arranged to execute each instruction of the set of instructions, and to provide output data which indicates the execution of each instruction; a history memory comprising first and second memory portions, coupled to the processor for sequentially receiving and storing the output data; and control means for selecting one of the first and second memory portions to store the output data; wherein the control means is adapted to identify the occurrence of an error in the processing of the data, and is further adapted to select the other one of the first and second memory portions upon the occurrence of the error.

Preferably the history memory further comprises at least one further memory portion coupled to the processor for sequentially receiving and storing the output data, and the control means is further arranged for selecting one of the first, second, and at least one further memory portion.

Each memory portion preferably comprises a number of memory locations.

Preferably the number of memory locations is ten.

In this way a brief protocol of the last tasks performed by the program is generated and the error or errors are more easily found.

Brief Description of the Drawings An exemplary embodiment of the invention will now be described with reference to the drawing in which: FIG. 1 shows a flow chart of an exemplary program to be executed in accordance with the invention.

FIG.2 shows a block diagram of a history memory of the preferred embodiment in accordance with the invention.

Detailed Description of a Preferred Embodiment Referring to FIG. 1, there is shown a flow chart 10 of a typical software program, to be performed by a microprocessor (not shown in FIG.1). A Start/Init. block 20 represents the initialisation procedure for the program.

One of the functions of this procedure is to set aside an area of programmable memory as a history memory, to be further described below.

Blocks 30, 40, 50, 60 and 70 denote tasks A, B, C, D, and E respectively of the program. The arrangement of the blocks gives rise to the following possibilities of task execution order. Task A always follows the Start/Init.

procedure. Execution of one of the tasks B, C or D follows task A. If task B or C occurs, then task E is executed before returning to task A. If task D occurs, the program proceeds directly back to task A.

During the execution of the program, interrupts may occur (denoted by interrupt blocks 80 (I1) and 90 (I2). Such interrupts may be caused by external hardware.

Referring now also to FIG.2, the history memory 100 comprises two separate sets of memory addresses, arranged as task lists 110 and 120 respectively, and a single memory address, arranged as a current list byte 130. Each of the task lists 110 and 120 has ten sequential memory locations. The history memory 100 connects with a microprocessor 140, but may of course, be integrated with the microprocessor 140.

The current list byte 130 indicates which of the task lists 110 and 120 is active, and is arranged to be toggled by the microprocessor 140 during the Start/Init. procedure.

In operation, the program starts with the Start/Init. procedure, which includes the initialisation of the history memory 100. The current list byte 130 is read by the microprocessor 140, and toggled. In this way the previous active task list now becomes inactive, and the previously inactive task list is now active.

At the start of the execution of each task or interrupt within the program, data indicating the task or interrupt is sent by the microprocessor 140 to the history memory 100. The history memory 100 stores the incoming data sequentially, in the active task list, as denoted by the current list byte 130.

When the last memory address in the active list is written to, the next incoming data is written to the first memory address in the active list, thus overwriting earlier data. In this way the ten most recent tasks or interrupt routines, are recorded in the active task list of the history memory 100.

If an error occurs during the program execution, the microprocessor 140 resets the program and continues. During the reset, the Start/Init. procedure is performed, and the current list byte 130 is toggled. Therefore the previously active task list, containing the ten most recent tasks or interrupts executed immediately before the error occurred, becomes inactive, and is not overwritten by the incoming data.

In this way the inactive task list forms a brief protocol of the program flow, and may be subsequently analysed to determine the ten tasks or interrupts which were executed at the time of the error. Such information will be of use to the programmer in finding and debugging the error.

It will be appreciated by a person skilled in the art that the number and arrangement of tasks A, B, C, D, and E are purely exemplary. Additionally, the task lists 110 and 120 may have a different number of memory addresses than described above.

Furthermore, the history memory 100 could be arranged with three or more task lists.

Claims

1. A data processing system, for processing data according to a set of instructions, comprising: a processor arranged to execute each instruction of the set of instructions, and to provide output data which indicates the execution of each instruction; a history memory comprising first and second memory portions, coupled to the processor for sequentially receiving and storing the output data; and, control means for selecting one of the first and second memory portions to store the output data; wherein the control means is adapted to identify the occurrence of an error in the processing of the data, and is further adapted to select the other one of the first and second memory portions upon the occurrence of the error.

2. The system of claim 1, wherein the history memory further comprises at least one further memory portion coupled to the processor for sequentially receiving and storing the output data, and the control means is further arranged for selecting one of the first, second, and at least one further memory portion.

3. The system of any preceding claim, wherein each memory portion comprises a number of memory locations.

4. The system of claim 3, wherein the number of memory locations is ten.

5. A data processing system substantially as hereinbefore described, with reference to the drawings.