GB2294342A

GB2294342A - Expandable memory cassettes

Info

Publication number: GB2294342A
Application number: GB9521049A
Authority: GB
Inventors: Susumu Nishikita
Original assignee: Sega Enterprises Ltd
Current assignee: Sega Corp
Priority date: 1994-10-14
Filing date: 1995-10-13
Publication date: 1996-04-24
Anticipated expiration: 2015-10-13
Also published as: GB2294342B; KR0184931B1; CN1139240A; GB9521049D0; JPH08115592A; KR960015272A; BR9504405A; HK1012741A1

Abstract

A secondary memory cassette 31 includes a connector 32 which can be connected to both a primary memory cassette 21 or a processing device body, an address transfer circuit 39 which judges whether the connector has been connected to the primary memory cassette 21 based upon the connection state of the connector and outputs an address transfer signal, and a memory 38 which outputs data corresponding to the address transfer signal and the address signal supplied from connector 32. The primary memory cassette 21 includes a mask ROM 28, a connector 22 for connection with the processing device body, and a connector 24 which can be connected with the secondary memory cassette 31. A predetermined pin of connector 24 is connected to a ground. When primary memory cassette 21 is connected with secondary memory cassette 31, signal Sa becomes level L, so that address transfer circuit 39 changes the memory allocation of ROM 38. <IMAGE>

Description

Data Processing System, Method thereof and Memory Cassette Background of the Invention Field of the Invention The present invention relates to a data processing system comprising a processing apparatus which conducts the processing of information such as the execution of programs and the use of data by installing a memory cassette therein with programs and data stored thereon, a memory cassette structure used for this system and the data processing method of this system.

Description of the Prior Art These types of data processing systems are known as comprising a memory cassette with programs and data stored thereon, and an operator (processing device) having a connector for connection to this memory cassette, and executing the cassette programs by connection of such memory cassette to this connector. A typical data processing system of this kind is a system for game machines. As is well known, game machines execute game programs by installation of a memory cassette therein with programs and data for various games stored thereon. Generally provided game machines further comprise a game machine body for using such data, and a controller giving various operating commands (operating signals) to the game machine body, which enables indication of the processed matter inside the game machine body on television receivers and the like.

These kinds of memory cassettes are constructed so as to have a connector on one side of the box-shaped cassette body and to comprise a ROM and its peripheral circuits inside the cassette body. A memory cassette with this kind of structure has a substantially constant cassette body volume, thereby inevitably determining the storage capacity of the ROM. This determines the capacity of programs storable in the ROM, leading to demand for greater program capacity.

Therefore, a compact connector provided on the body of the memory cassette offers a game machine which enables the installation of a new compact ROM cassette on this compact connector. This game machine is constructed such as to enable the installation of a memory cassette with a compact connector provided thereon in the game machine body. By installing a compact ROM on the compact connector of the memory cassette, it is possible to use the data stored in the compact ROM with the game machine body.

However, these game machines merely use the data in the compact ROM cassette without any change in the development of the game itself, which would not completely satisfy demands for development of a variety of games.

The development of various games and realization of other various processes require a large amount of programs and a great memory capacity for storing a great amount of programs.

However, conventional game machines had the disadvantage that the memory capacity of the cassette body was inevitably limited in consideration of transportation, handling or price, etc.

Further, conventional game machines could not re-use games developed in the past inside new game programs, so that the non-use of old programs led to the waste of development steps, the ROM and other resources spent for the development of such program.

Therefore, the present invention aims at solving these problems by providing a data processing system which can realize a variety of processes and which can effectively use resources. Another purpose is to provide a novel memory cassette structure for use with this system.

Summary of the Invention In order to overcome these problems, the data processing system according to Claim 1 is a data processing system comprising a processing device body for performing the process based on the stored contents of memory cassettes, a primary memory cassette which is connectable to said processing device body, and, a secondary memory cassette which is connectable to either said primary memory cassette or said processing device body, wherein when either the primary memory cassette or the secondary memory cassette is connected to the processing device body, data is read from such memory cassette in a first address range, and wherein when the processing device body is connected to the primary memory cassette which is then connected to the secondary memory cassette, data is read in a wider address range, which includes a second address range which does not overlap with the first address range.

The memory cassette according to Claim 2 is a memory cassette which is said secondary memory cassette used for said data processing system according to claim 1, comprising a connector which is electrically connectable to either a connector of said primary memory cassette or said processing device body, a connection state judging circuit which judges by the connection state of the connector whether the connector has been connected to the primary memory cassette and outputs an address transfer signal corresponding to such connection state, and, a memory for outputting data corresponding to the address transfer signal supplied from the connection state judging circuit and to the address signal supplied from the connector.

The memory cassette according to Claim 3 is a memory cassette according to claim 2, wherein when said connection state judging circuit judges that said connector has been connected to said primary memory cassette, the connection state judging circuit outputs said address transfer signal in order to transfer the address range for reading data from the memory to said second address range which does not overlap with said first address range for reading the data from the memory of the primary memory cassette.

The memory cassette according to Claim 4 is a memory cassette according to claim 2, wherein when the signal logic of one predetermined pin of a plurality of pins constituting said connector becomes a predetermined signal logic, said connection state judging circuit judges that the connector has been connected to another memory cassette.

The memory cassette according to Claim 5 is a memory cassette which is said primary memory cassette used for said data processing system according to claim 1 and which is connectable to the memory cassette according to claims 2, 3 and 4 as said secondary memory cassette, comprising a first connector which is electrically connectable to said processing device body, a memory for outputting data corresponding to an address signal supplied from the processing device body when connected to the processing device body via the first connector, and, a second connector which is connectable to the secondary memory cassette and which is provided so that the address signal supplied from the processing device body via the first connector is transmittable, wherein one predetermined pin of a plurality of pins constituting the second connector is retained at a predetermined signal logic.

The memory cassette according to Claim 6 is a memory cassette which is said secondary memory cassette used for said data processing system according to claim 1, comprising a connector which is eledtrically connectable to a connector of said primary memory cassette, and a memory for outputting data corresponding to an address signal supplied from the connector, wherein one predetermined pin of a plurality of pins constituting the connector is retained at a predetermined signal logic.

The memory cassette according to Claim 7 is a memory cassette which is said primary memory cassette used for said data processing system according to claim 1, and which is connectable to said memory cassette according to claim 6 as said secondary memory cassette, comprising a first connector which is electrically connectable to said processing device body a second connector which is connectable to the secondary memory cassette and which is provided so that an address signal supplied from the processing device body via the first connector is transmittable a connection state judging circuit which judges by the connection state of the second connector whether the secondary memory cassette has been connected to the second connector and outputs an address transfer signal corresponding to such connection state, and a memory for outputting data corresponding to the address transfer signal supplied from the connection state judging circuit and to the address signal supplied from the first connector.

The memory cassette according to Claim 8 is a memory cassette according to claim 7, wherein when said connection state judging circuit judges that said second connector has been connected to said secondary memory cassette, said connection state judging circuit outputs said address transfer signal in order to transfer the address range for reading data from the memory of such primary memory cassette to said second address range which does not overlap with said first address range for reading data from the memory of the secondary memory cassette.

The memory cassette according to Claim 9 is a memory cassette according to claim 7, wherein when the signal logic of one predetermined pin of a plurality of pins constituting said second connector becomes a predetermined signal logic, said connection state judging circuit judges that the connector has been connected to said secondary memory cassette.

The memory cassette according to Claim 10 is a memory cassette which is said secondary memory cassette used for said data processing system according to claim 1, comprising a connector which is electrically connectable to said primary connector, and a memory for outputting data corresponding to said address signal supplied from the connector, wherein a lead extending from one predetermined pin of a plurality of pins constituting the connector is connected to a chip elect terminal of the memory.

The memory cassette according to Claim 11 is a memory cassette which is said primary memory cassette used for said data processing system according to claim 1, and which is connectable to the memory cassette according to claim 10 as said secondary memory cassette, comprising a first connector which is electrically connectable to said processing device body, a second connector which is connectable to the secondary memory cassette and which is provided such that said address signal supplied from the processing device body via the first connector is transmittable, a connection state judging circuit which, based on a certain address signal supplied from the first connector, outputs a first chip select signal which becomes effective when the address signal is within said first address range, and outputs a second chip select signal which becomes effective when the address signal is within said second address range to a predetermined pin of the second connector, and a memory for outputting data corresponding to the first chip select signal supplied from the connection state judging circuit and to the address signal supplied from the first connector.

The memory cassette according to Claim 12 is a memory cassette according to one of claims 5, 7, 8, 9 or 11, wherein the memory cassette has a three-dimensional construction comprising two opposing faces, and said first connector and said second connector are provided on the opposing faces, respectively.

The data processing method according to Claim 13 is a data processing method employing a processing device body performing the process based on the stored contents of memory cassettes, a primary memory cassette which is connectable to said processing device body, and a secondary memory cassette which is connectable to either the primary memory cassette or the processing device body, wherein when it is judged that either the primary memory cassette or the secondary memory cassette is connected to the processing device body, data is read from such memory cassette in said first address range, and wherein when it is judged that the processing device body is connected to the primary memory cassette which is then connected to the secondary memory cassette, data is read in a wider address range, which includes said second address range which does not overlap with the first address range.

Therefore, as it is possible to use the primary and secondary memory cassettes alone or jointly, the demands for a variety of game developments are satisfied. Further, by the use of two memory cassettes, it is possible to use programs using a large amount of memory capacity. Moreover, as it is possible to re-use old games, the effect is achieved that the steps of development, ROM and other resources for such game are effectively utilized.

Brief Description of the Figures Fig. 1 A perspective view of the structure of an embodiment of the data processing system according to the present invention and the memory cassette used for this system.

Fig. 2 A block diagram of the circuits of a primary memory cassette and a secondary memory cassette to be used in such embodiment.

Fig. 3 A block diagram of the address transfer circuit of such embodiment.

Fig. 4 A view describing the relation between the address values of the primary and secondary memory cassette according to such embodiment, respectively, and the address value when both cassettes are fitted together.

Fig. 5 A flow chart describing the operation of the game machine body according to such embodiment.

Fig. 6 A view describing the memory map when both cassettes according to such embodiment are fitted together.

Fig. 7 A view of another construction of the primary and secondary memory cassettes according to such embodiment.

Fig. 8 A view describing the memory map when both cassettes according to such embodiment are fitted together.

Fig. 9 A view describing the primary and secondary memory cassette according to such embodiment.

Fig. 10 A block view of the decoder circuit according to such embodiment.

Fig. 11 A view describing the memory map of each of the memory cassettes according to such embodiment.

Fig. 12 A view describing the operation of the embodiment according to the present invention.

Detailed Description of the Invention Now, embodiments of the present invention will be described with reference to the drawings.

Fig. 1 is a perspective view of an embodiment of the data processing system according to the present invention and the memory cassette structure used for this system.

The data processing system indicated in Fig. 1 has as its composing elements a game machine body 11, a primary memory cassette 21 and a secondary memory cassette 31. On connector 12 of game machine body 11, a connector 22 of primary cassette 21 may be installed as shown by arrow X, and a connector 32 of secondary cassette 31 may be installed as shown by arrow Y.

Further, on the surface of body 23 of primary memory cassette 21 which is opposite to connector 22 (shown as the upper surface), connector 24 is arranged which is identical to connector 12 provided on game machine body 11, and enables the installation of connector 32 of secondary cassette 31 on connector 24 as shown by arrow Z.

When connector 22 of primary memory cassette 21 is installed on connector 12 of game machine body 11 as shown by arrow X, and connector 32 of secondary memory cassette 31 is installed on connector 24 of primary cassette 21 as shown by arrow Z, game machine body 11 is in a state to be able to use the game programs of both the primary cassette 21 and the secondary cassette 31.

For enabling use of the programs of both memory cassettes 21, 31 with game machine body 11, a structure is provided on the interior of such primary memory cassette 21 or secondary memory cassette 31 for sharing addresses. This structure becomes operative when connector 22 of primary cassette 21 is installed on connector 12 of such game machine body 11 and connector 32 of secondary cassette 31 is installed on connector 24 of primary cassette 21. In this way, one of the addresses of the memory address ranges of memory cassettes 21, 31 is transferred and used.

Now, each element of such data processing system will be described in detail. As shown in the drawings, game machine body 11 of the present embodiment has a parallelepiped shape wherein the length is somewhat smaller than the width and the height is around 1/20 of the length. Connector 12 is provided on the upper surface of this 3-dimensional body, and switch 13 is provided on the left lower side of the upper surface, as shown.

Primary memory cassette 21 comprises a thin parallelepiped housing 23. Connector 22 is provided on bottom 26 of this housing 25, and on the upper surface 27 (the face opposite to said bottom face) of this housing 25, connector 24 is provided which has the same structure as connector 12 of game machine body 11 is provided.

Further, secondary cassette 31 comprises a thin parallelepiped housing 35, and connector 32 is provided on bottom 36 of housing 35. This structure enables the installation of connector 32 of secondary cassette 31 on connector 12 of game machine body 11 and to connector 24 of the primary cassette 21, too.

Fig. 2 is a circuit diagram of the primary and the secondary memory cassette used in an embodiment of the system relating to the present invention.

In Fig. 2, the circuit system of primary memory cassette 21 comprises a connector 22, a connector 24 and a mask ROM 28.

Those connectors 22 and connectors 24 which have the same pin numbers are connected to each other as signal wires for address Ad, data Dt and control signal Ct. The wiring for address Ad, data Dt and control signal Ct is constructed so as to be connected to mask ROM 28.

Further, at primary memory cassette 21, connector 24 with a predetermined pin number is connected to the grounding electrode. When connector 32 of secondary cassette 31 is connected with connector 24 of primary cassette 21, it comes into contact with the grounding electrode of connector 24. A pin inside connector 24 is grounded. Accordingly, the signals taken from a pin of this connector 24 are signals Sa indicating connection of secondary cassette 31 to primary cassette 21.

Further, in the circuit system of secondary cassette 31, a connector 32, a mask ROM 38 and an address transfer circuit 39 as a connection state judging means are arranged. Address Ad, data Dt and control signal Ct, respectively, of connector 32 with a predetermined pin number is connected to a predetermined pin of mask ROM 38, and address Ad and control signal Ct and signal Sa are connected to a predetermined electrode of address transfer circuit 39. The address transfer signals generated by address transfer circuit 39 are supplied to the address changing input terminal of mask ROM 38.

Fig. 3 is a circuit diagram indicating an example of the structure of such address transfer circuit 39.

In Fig. 3, address transfer circuit 39 comprises a decoder 391 which forms first chip select signal CSa or second chip select signal CSb based on a certain memory address Ad and a certain memory control signal Ct, and a selector circuit 392 which generates signals for transferring the memory address based on chip select signal CSa, CSb from decoder 391 and signal Sa which indicates the connection of primary cassette 21 with secondary cassette 31, and is constructed as follows.

In decoder 391, the wires are arranged so that address Ad and control signal Ct may be supplied to the decoder. The wiring allows supply of chip select signals CSa, CSb generated by decoder 391 to A, B terminals of selector circuit 392.

Further, wires are arranged for supply of signal Sa to selection terminal A/B of selector circuit 392. Also, the output terminal Y of selector circuit 392 is connected to the address transfer terminal of mask ROM 38.

Now, the operations of such embodiment will be described with reference to Figs. 4-6 based on Figs. 1-3. Fig. 4 indicates the operation when primary and secondary memory cassette are fitted together, and describes the relation between the individual address values of the primary and secondary memory cassette, and the address value when both cassettes are fitted together. Fig. 5 (1) is a flow chart for describing the movements when only the secondary memory cassette is connected to the game machine body, and Fig. 5 (2) is a flow chart for describing the movements when only the primary memory cassette is connected to the game machine body.

Fig. 6 describes the memory map when both cassettes are fitted together.

First, as shown in Fig. 4 (c), primary memory cassette 21 normally stores its program data B from address OOOOOOH (H indicates the hexadecimal system) toIFFFFFH. In the same way, as shown in Fig. 4 (b), secondary memory cassette 31 normally stores its program data A from address OOOOOOH to IFFFFFH.

The installation of only primary memory cassette 21 in game machine body 11 as shown by arrow X results in a state in which game machine body 11 and primary memory cassette 21 are electrically connected via connector 12 and connector 22.

When in this state power source is input by turning switch 13 of game machine body 11 on, game machine body 11 principally commences with address OOOOOOH and processes the necessary program data, etc. (Fig. 5 (2) Step 200), and immediately judges the existence of any program data, etc. at and after address 200000H (Step 201). This judgment is conducted as follows. Assuming the output of game machine body 11 of address Ad is 200000H and predetermined control signal Ct is output, one only needs to judge whether any information may be obtained as data Dt.

In this case, even if address Ad and control signal Ct as above are input to mask ROM 28, no data are output from mask ROM 28 to data Dt. Therefore, game machine body 11 judges that program data do not exist at and after address 200000H (Fig. 5 (2) Step 201; NO), so it will operate using only the program data B stored from addressOOOOOOH to address 1FFFFFH of primary memory cassette 21 (Fig. 5 (2) Step 202).

In the same way, when installing only secondary cassette 31 in game machine body 11 as shown by arrow Y (Fig. 1), a state is provided so that game machine body 11 and secondary cassette 31 are electrically connected via connector 12 and connector 32. In this state, when power flows by turning switch 13 of game machine body 11 on (Fig. 5 (1) Step 101), game machine body 11 will operate only with program data A stored fromOOOOOOH to 1FFFFFH of secondary cassette 31 (Fig.

5 (1) Step 102).

Next, primary memory cassette 21 is installed in game machine body 11 as shown by arrow X in Fig. 1, and additionally, secondary memory cassette 31 is installed on primary memory cassette 21 as shown by arrow Z. In this case, game machine body 11 and primary memory cassette 21 are electrically connected via connector 12 and connector 22, and primary memory cassette 21 and secondary memory cassette 31 are electrically connected via connector 24 and connector 32.

Now, when switch 13 of game machine body 11 is switched on and power flows through, signal Sa indicating connection state becomes "L," given to address transfer circuit 39 of secondary memory cassette 31 via connector 24 and connector 32. Game machine body 11 processes here the necessary program data (vector) commencing basically with the execution from address OOOOOOH (Step 200).

Thereby, game machine body 11 judges whether there is any program data from address 200000H and onwards (Step 201).

Therefor, game machine body 11 makes address Ad to addresses from 200000H on, gives control signal Ct, and judges whether there is any information as data Dt.

When address Ad and control signal Ct are input to address transfer circuit 39, address transfer circuit 39 is based on address Ad and control signal Ct and forms chip select signal CSb with decoder 391. The chip select signal CSb is given to mask ROM 38 via select circuit 392, as signal Sa indicating connection state indicates "L." Thereby, the address of mask ROM 38 is transferred from 200000H to 2FFFFFH. Then, when primary memory cassette 21 and secondary memory cassette 31 are fitted together, the address of mask ROM 28 of primary memory cassette 21 is, as shown in Fig. 4(a) and Fig. 6, still fromOOOOOOH to lFFFFFH, but the address of mask ROM 38 of secondary memory cassette 31 is allotted from 200000H to 2FFFFFH.

As the address of secondary memory cassette 31 has been transferred as above, the designation of an address from 200000H onwards by game machine body 11 leads to the output of information of such address from mask ROM 38 to the data wires.

In other words, when game machine body 11 finds some kind of information at the designated address in Step 201, it determines that program data exists at and after address 200000H (Step 201; YES), and, thereafter, game machine body 11 operates using program data B stored from address OOOOOOH to 1FFFFFH in primary memory cassette 21 and program data A stored from address 200000H to 3FFFFFH in secondary memory cassette 31 (Step 203).

In other words, when game machine body 11 judges that primary memory cassette 21 and secondary memory cassette 31 have been fitted together, it can access these freely, as described above.

Further, in such state where primary memory cassette 21 and secondary memory cassette 31 are fitted together, the program area exists from 000000H toxxxxxxH, and the data area exists from xxxxxxH to 1FFFFFH in primary memory cassette 21, as indicated in Fig. 6. At the secondary memory cassette 31, the program area exists from 200000H to xxxxxxH and the data area from xxxxxxH to 3FFFFFH, as indicated in Fig. 6 According to the embodiment above, it is possible to use primary memory cassette 21 and secondary memory cassette 31 alone or fitted (connected) together, satisfying various demands for the development of a variety of games. Further, as two memory cassettes may be used at the same time, a large amount of program capacity may be used.Moreover, by installing a secondary memory cassette on the primary memory cassette, old games can be used again, providing the advantage of effectively using the development steps for the games, the ROM and other resources.

Fig. 7 shows another exemplary construction of a primary and secondary memory cassette used in an embodiment of the present invention. Same composing elements in Fig. 7 as in Fig. 2 are indicated by identical reference numbers.

The circuit system of primary memory cassette 21 comprises connector 22, connector 24, mask ROM 28 and address transfer circuit 29 as the circuit judging the connection state, and the wires with the same pin numbers at connector 22 and 24 are connected as signal wires for address Ad, data Dt and control signal Ct. The wiring for such address Ad, data Dt and control signal Ct is constructed such to be connected to mask ROM 28.

Further, address Ad and control signal Ct and signal Sa are connected to a predetermined electrode of address transfer circuit 29, and the address transfer signals generated by this address transfer circuit 29 are supplied to the address changing input terminal of mask ROM 28. The address transfer circuit 29 has the same circuit construction as address transfer circuit 39 shown in Fig. 3.

Further, the circuit system of secondary memory cassette 31 comprises connector 32 and mask ROM 38. Address Ad, data Dt and controls signal Ct of such connector 32 with predetermined pin numbers, which have the predetermined pin numbers of connector 32 to be connected to predetermined pins of mask ROM 38, is constructed such to be connected to the grounding electrode.

The operations of this embodiment will be explained with reference to Figs. 5, 8 based on Figs 1, 3 and 7. Fig. 8 explains the memory map when both cassettes are fitted together.

First, primary memory cassette 21 and secondary memory cassette 31 individually store program data B and A from address OOOOOOH to 1FFFFFH alone, as described above.

Then, when only secondary memory cassette 31 is installed in game machine body 11 as shown by arrow Y (Fig. 1), then game machine body 11 will, as described above, operate based only on program data A stored fromOOOOOOH to 1FFFFFH of "secondary memory cassette 31" (Fig. 5, Step 101, 102).

In the same way, when only primary memory cassette 21 is installed in game machine body 11 as showy by arrow X (Fig.

1), game machine body will, as described above, commence with the operation from addressooooooH and process the necessary program data (Step 200), then immediately judge the existence of program data from address 200000H on (Step 201), and operate based only on program data B stored from address OOOOOOH to 1FFFFFH (Step 202).

Next, primary memory cassette 21 is installed in game machine body 11 in accordance with arrow X, and further, secondary memory cassette 31 is installed on primary memory cassette 21 in accordance with arrow Z. In this case, game machine body 11 and primary memory cassette 21 are electrically connected via connector 12 and connector 22, and, further, primary memory cassette 21 and secondary memory cassette 31 are electrically connected via connector 24 and connector 32. In this state, power flows through by switching switch 13 of game machine body 11 to on, signal Sa indicating connection state becomes "L" and this signal Sa is given to address transfer circuit 29 of primary memory cassette 21 via connector 32 and connector 24.

Accordingly, when game machine body 11 outputs control signal Ct by using address Ad at and after address 200000H, address transfer signals are output from address transfer circuit 29 to mask ROM 28. Through this address transfer signal, the address of mask ROM 28 is transferred and the address of mask ROM 28 moves from 200000H to 3FFFFFH, as shown in Fig. 8. At this point, game machine body 11 processes the necessary program data (vector) by commencing basically with the operation from 000OO, but by compulsorily transferring the vector of primary memory cassette 21 to address OOOOOOH of secondary memory cassette 31, it is possible to continue operating program A of secondary memory cassette 31.

Then, game machine body 11 judges the existence of programs at address 200000H and onwards (Step 201; YES). This judgment is made by determining whether information is output at data Dt when address Ad from address 200000H on is output and control signal Ct is output. When such address Ad and control signal Ct is input to address transfer circuit 29, address transfer circuit 29 generates chip select signals based on address Ad and control signal Ct, generates address transfer signals from these chip select signals and signal Sa indicating connection state ("L,") and gives this to mask ROM 28.

Thereby, as the address allotted to mask ROM 28 is transferred from 200000H to 3FFFFFH, the fitting together of primary memory cassette 21 and secondary memory cassette 31 results in the address of mask ROM 28 of primary memory cassette 21 being transferred from 200000H to 3FFFFFH, and that of mask ROM 38 of secondary memory cassette 31 from 00000H to lFFFFFH, as indicated in Fig. 8. As the address of primary memory cassette 21 has been transferred as above, the designation of an address at 200000H and onwards by game machine body 11, the information of such address is output from mask ROM 28 to data Dt.

Therefore, at game machine body 11, when information is acquired at a certain address as above, the judgment is that there is program data at 200000H and onwards (Step 201; YES), and afterwards, game machine body 11 will operate by using both the program data B stored from address 200000H to 3FFFFFH in primary memory cassette 21, and the program data A stored from OOOOOOH to 1FFFFFH in secondary memory cassette 31 (Step 203). In other words, game machine body 11 may, as described above, access both cassettes freely when it has judged that both primary memory cassette 21 and secondary memory cassette 31 have been installed.

Further, in such state of installed primary memory cassette 21 and secondary memory cassette 31, primary memory cassette 21 has, as shown in Fig. 8, its program area from address 200000H to xxxxxxH, and its data area from xxxxxxH to 3FFFFFH. Secondary memory cassette 31 has, as shown in Fig. 8, its program area from OOOOOOH to xxxxxxfi, and its data area from xxxxxxH to 1FFFFFH.

Fig. 9 illustrates another embodiment of the primary and secondary memory cassette used in the present invention. The embodiment of Fig. 9 differs from that of Fig. 7 in that chip select signal *CS (* indicates the inversion of CS) is supplied from game machine body 11 to decoder 40 via connector 22, and a predetermined address is supplied to decoder 40.

Another difference to the embodiment of Fig. 7 is that chip select signal CSa and chip select signal CSb is generated by decoder 40, and the electric wiring is arranged so that such chip select signal CSa is supplied to mask ROM 28 and chip select signal CSb is supplied to mask ROM 38 of secondary memory cassette 31 via the predetermined pin number portion of connector 24 and the same pin number portion of connector 32.

The other construction is the same as in Fig. 7. The same reference numbers are attached to the portions which are identical in Fig. 9 and Fig. 7.

Fig. 10 is a view of a circuit indicating an example of the concrete construction of the decoder. As shown in Fig.

10, decoder 40 is composed of two NAND circuits 401, 402 and two inverter circuits 403, 404, and has the following connection state. An electric connection allows address *ax (in this case, * indicates the inversion of ax) to be directly given to one input terminal of NAND circuit 401 and one input terminal of NAND circuit 402 via inverter circuit 403.

Further, an electric connection allows chip select signal *CS sent from game machine body 11 via connector 12 and connector 22 of primary memory cassette 21 to be input to the other input terminals of NAND circuits 401, 402 via inverter circuit 404.

Chip select signal CSa is output from the output terminal of NAND circuit 401, and chip select signal CSb is output from the output terminal of NAND circuit 402, respectively.

This embodiment allows the single or joint use of primary memory cassette 21 and secondary memory cassette 31, satisfying demands for development of a variety of games.

Further, the use of two memory cassettes allows the use of a large program capacity. It also has the advantage of using the steps of development, ROM and other resources of such game effectively, as it is possible to use old games again.

This embodiment will be explained in detail with reference to Figs. 9, 10, 11 and 12. Fig. 11 describes the memory map arranged by the embodiment of Fig. 9. Fig. 12 is an explanation for using the operation of such embodiment.

Game machine body 11 can output address *ax used for switching of primary memory cassette 21 or secondary memory cassette 31, and can also output chip select signal *CS.

In this state, as shown in Fig. 12, when address *ax is "L" ("0"), and chip select signal *CS output from game machine body 11 is "L" ("0"), both input terminals of NAND circuit 401 become "H" ("1. ") Thereby, the output of NAND circuit 401 becomes "L" ("0. ") As one input terminal of NAND circuit 402 is "L" ("0, ") the output of NAND circuit 402 becomes "H" ("1. ") In other words, chip select signal CSa will be output from decoder 40. Thereby, game machine body 11 will use the programs, etc. stored in primary memory cassette 21. This leads to the use of addressesOOOOOOH to 1FFFFFH in primary memory cassette 21, as shown in Fig. 11.In this case, regardless of whether primary memory cassette 21 is installed in game machine body 11 alone or whether a secondary memory cassette 31 is installed on (fitted together with) primary memory cassette 21 installed in game machine body 11, game machine body 11 will use the programs in primary memory cassette 21.

On the other hand, as shown in Fig. 12, if a certain address *ax (in this case, using for example the 6th data Dt in 200000H) becomes "H" ("1,") and chip select signal *CS output from game machine body 11 becomes "L" ("0, ") both input terminals of NAND circuit 402 become "H" ("1,") so that the output of NAND circuit 402 becomes "L" ("0. ") Further, as one input terminal of NAND circuit 401 is "L" ("0, ") the output of NAND circuit 401 becomes "H" ("1. ") Then, chip select CSb will be output from decoder 40.

This leads to game machine body 11 being unable to access with primary memory cassette 21, only being able to access with secondary memory cassette 31. Then, address Ad is from 200000H to 3FFFFFH, so that game machine body 11 is able to use the programs, etc. stored in secondary memory cassette 31.

As shown in Fig. 11, hereby used is the address of secondary memory cassette 31 which has been transferred from 200000H to 3FFFFFH.

Further, when chip select signal *CS is "H" ("1, ") the output terminals of NAND circuits 401, 402 of decoder 40 will both output "H" ("1,") regardless of the value of address *ax, so that both primary memory cassette 21 and secondary memory cassette 31 are not accessible.

Further, the installation of secondary memory cassette 31 alone in game machine body 11 leads to input of chip select signal *CS directly to mask ROM 38 of secondary memory cassette 31, so that secondary memory cassette 31 will use the addresses fromOOOOOOH to lFFFFFH.

According to this embodiment, primary memory cassette 21 and secondary memory cassette 31 are used alone or jointly, satisfying demands for a variety of game developments.

Further, as two memory cassettes can be used, a large program capacity can be used. Further, as it is possible to use old games again, there is the advantage that the steps of development, ROM and other resources of such game are used effectively.

Further, in the present embodiment, the circuit for judging the connection state may be provided at the game machine body, i. e. at the side of the processing device body, too.

Claims

CLAIMS:

1. A data processing system comprising; a) a processing device body for performing the process based on the stored contents of memory cassettes; b) a primary memory cassette which is connectable to said processing device body; and c) a secondary memory cassette which is connectable to either said primary memory cassette or said processing device body, wherein when either the primary memory cassette or the secondary memory cassette is connected to the processing device body, data is read from such memory cassette in a first address range, and wherein when the processing device body is connected to the primary memory cassette which is then connected to the secondary memory cassette, data is read in a wider address range, which includes a second address range which does not overlap with the first address range.

2. A memory cassette which is said secondary memory cassette used for said data processing system according to claim 1, comprising: a) a connector which is electrically connectable to either a connector of said primary memory cassette or said processing device body; b) a connection state judging circuit which judges by the connection state of the connector whether the connector has been connected to the primary memory cassette and outputs an address transfer signal corresponding to such connection state; and c) a memory for outputting data corresponding to the address transfer signal supplied from the connection state judging circuit and to the address signal supplied from the connector.

3. A memory cassette according to claim 2, wherein when said connection state judging circuit judges that said connector has been connected to said primary memory cassette, the connection state judging circuit outputs said address transfer signal in order to transfer the address range for reading data from the memory to said second address range which does not overlap with said first address range for reading the data from the memory of the primary memory cassette.

4. A memory cassette according to claim 2, wherein when the signal logic of one predetermined pin of a plurality of pins constituting said connector becomes a predetermined signal logic, said connection state judging circuit judges that the connector has been connected to another memory cassette.

5. A memory cassette which is said primary memory cassette used for said data processing system according to claim 1 and which is connectable to the memory cassette according to claims 2, 3 and 4 as said secondary memory cassette, comprising: a) a first connector which is electrically connectable to said processing device body; b) a memory for outputting data corresponding to an address signal supplied from the processing device body when connected to the processing device body via the first connector; and c) a second connector which is connectable to the secondary memory cassette and which is provided so that the address signal supplied from the processing device body via the first connector is transmittable, wherein one predetermined pin of a plurality of pins constituting the second connector is retained at a predetermined signal logic.

6. A memory cassette which is said secondary memory cassette used for said data processing system according to claim 1, comprising: a) a connector which is electrically connectable to a connector of said primary memory cassette; and b) a memory for outputting data corresponding to an address signal supplied from the connector, wherein one predetermined pin of a plurality of pins constituting the connector is retained at a predetermined signal logic.

7. A memory cassette which is said primary memory cassette used for said data processing system according to claim 1, and which is connectable to said memory cassette according to claim 6 as said secondary memory cassette, comprising: a) a first connector which is electrically connectable to said processing device body; b) a second connector which is connectable to the secondary memory cassette and which is provided so that an address signal supplied from the processing device body via the first connector is transmittable; c) a connection state judging circuit which judges by the connection state of the second connector whether the secondary memory cassette has been connected to the second connector and outputs an address transfer signal corresponding to such connection state; and d) a memory for outputting data corresponding to the address transfer signal supplied from the connection state judging circuit and to the address signal supplied from the first connector.

8. A memory cassette according to claim 7, wherein when said connection state judging circuit judges that said second connector has been connected to said secondary memory cassette, said connection state judging circuit outputs said address transfer signal in order to transfer the address range for reading data from the memory of such primary memory cassette to said second address range which does not overlap with said first address range for reading data from the memory of the secondary memory cassette.

9. A memory cassette according to claim 7, wherein when the signal logic of one predetermined pin of a plurality of pins constituting said second connector becomes a predetermined signal logic, said connection state judging circuit judges that the connector has been connected to said secondary memory cassette.

10. A memory cassette which is said secondary memory cassette used for said data processing system according to claim 1, comprising: a) a connector which is electrically connectable to said primary connector; and b) a memory for outputting data corresponding to said address signal supplied from the connector, wherein a lead extending from one predetermined pin of a plurality of pins constituting the connector is connected to a chip select terminal of the memory.

11. A memory cassette which is said primary memory cassette used for said data processing system according to claim 1, and which is connectable to the memory cassette according to claim 10 as said secondary memory cassette, comprising: a) a first connector which is electrically connectable to said processing device body; b) a second connector which is connectable to the secondary memory cassette and which is provided such that said address signal supplied from the processing device body via the first connector is transmittable;; c) a connection state judging circuit which, based on a certain address signal supplied from the first connector, outputs a first chip select signal which becomes effective when the address signal is within said first address range, and outputs a second chip select signal which becomes effective when the address signal is within said second address range to a predetermined pin of the second connector; and d) a memory for outputting data corresponding to the first chip select signal supplied from the connection state judging circuit and to the address signal supplied from the first connector.

12. A memory cassette according to one of claims 5, 7, 8, 9 or 11, wherein the memory cassette has a three-dimensional construction comprising two opposing faces, and said first connector and said second connector are provided on the opposing faces, respectively.

13. A data processing method employing: a processing device body performing the process based on the stored contents of memory cassettes; a primary memory cassette which is connectable to said processing device body; and a secondary memory cassette which is connectable to either the primary memory cassette or the processing device body, wherein when it is judged that either the primary memory cassette or the secondary memory cassette is connected to the processing device body, data is read from such memory cassette in said first address range, and wherein when it is judged that the processing device body is connected to the primary memory cassette which is then connected to the secondary memory cassette, data is read in a wider address range, which includes said second address range which does not overlap with the first address range.

14. A data memory device (21;31) which is detachably connectable to the main body (11) of a data processing device, and including means (29;39) for determining whether said device has been connected to said main body (11) in conjunction with another data memory device (31;21) and means (28;38) operable in response to a positive determination by said determining means for masking address data (Ad) supplied from said main body so as to change the address range for reading data from said memory device in such a way that it does not overlap an address range for reading data from said another data memory device.

15. A data processing system, substantially as hereinbefore described with reference to Figures 1 to 6 of the accompanying drawings.

16. A data processing system, substantially as hereinbefore described with reference to Figures 2 to 6 of the accompanying drawings.

17. A data processing system, substantially as hereinbefore described with reference to Figures 1, 7 and 8 of the accompanying drawings.

18. A data processing system, substantially as hereinbefore described with reference to Figures 7 and 8 of the accompanying drawings.

19. A data processing system, substantially as hereinbefore described with reference to Figures 1 and 9 to 12 of the accompanying drawings.

20. A data processing system, substantially as hereinbefore described with reference to Figures 9 to 12 of the accompanying drawings.

21. A memory cassette, which is the primary or secondary memory cassette of the data processing system according to any of claims 15 to 20.

22. A data processing method substantially as hereinbefore described employing a data processing system according to any of claims 15 to 20.