KR0184931B1 - Data processing system, method thereof and memory cassette - Google Patents

Abstract

An object of the present invention is to provide a data processing system that can realize various processes.

The second memory cassette 31 has a connector 32 which can be coupled to both the first memory cassette 21 or the processing apparatus main body, and whether the connector is connected to the first memory cassette 21 depending on the connection state of the connector. And an address conversion circuit 39 for outputting an address conversion signal, and a memory 38 for outputting data corresponding to the address conversion signal and the address signal supplied from the connector 32. The first memory cassette 21 includes a mask ROM 28, a connector 22 connectable with the main body of the processing apparatus, and a connector 24 connectable with the second memory cassette 31. The predetermined pin of connector 24 is connected to ground.

When the first memory cassette 21 is connected to the second memory cassette 31, the signal Sa becomes level L so that the address conversion circuit 39 changes the memory allocation of the ROM 38.

Description

Data processing system, method and memory cassette

1 is a perspective view showing a structure of one embodiment of a data processing system according to the present invention and a memory cassette used in the system.

2 is a block diagram showing circuits of a first memory cassette and a second memory cassette used in the above embodiment.

3 is a block diagram of the address conversion circuit of the embodiment.

Fig. 4 is a diagram for explaining the relationship between the address values of the first and second memory cassettes and the address values when both cassettes are combined with each other in accordance with the above embodiment.

5 is a flowchart for explaining the operation of the game machine main body according to the embodiment.

6 is a diagram for explaining a memory map when both cassettes are combined with each other according to the embodiment.

Fig. 7 shows another configuration of the first and second memory cassettes according to the embodiment.

8 is a diagram for explaining a memory map when two cassettes are combined with each other according to the embodiment.

9 is a diagram for explaining first and second memory cassettes according to the embodiment;

10 is a block diagram of a decoder circuit according to the embodiment.

11 is a view for explaining a memory map of each of the memory cassettes according to the embodiment.

12 illustrates the operation of an embodiment according to the present invention.

* Explanation of symbols for main parts of the drawings

11: game console body 13: switch

21: first memory cassette 12, 22, 24: connector

23: housing 28: mask ROM

31: second memory cassette 39: address conversion circuit

The present invention provides a data processing system including a processing apparatus capable of performing information processing such as execution of a program and use of data by providing a memory cassette in which a program and data are embedded, and a memory cassette structure used in the system, and It relates to a data processing method of the system.

These types of data processing systems include a memory cassette in which programs and data are embedded, and an operator (processing device) having a connector for connecting to the memory cassette, and the cassette program is connected by connecting the memory cassette with such a connector. It is known as executing. A general data processing system of this type is a system for game machines. As is known, game machines execute game programs by installing memory cassettes containing programs and data embedded for various games. Generally, the game machine further includes a game machine main body for use of the above data, and a controller which provides various operation commands (operation signals) to the game machine main body to display the processed matters in the game machine main body and the like on a television receiver. Doing.

These types of memory cassettes are configured to have a connector on one side of the box-shaped cassette body and to include a ROM and its peripheral circuits inside the cassette body. Since the memory cassette having this type of structure has a substantially constant cassette body volume, the storage capacity of the ROM is determined. This determines and erases the capacity of the program that can be stored in the ROM, so it is necessary to increase the program capacity.

Therefore, the small connector provided in the main body of the memory cassette provides a game machine capable of installing a new small ROM cassette with such a small connector. This game machine is configured to install a memory cassette provided with a small connector in the game machine body. By installing a small ROM in the small connector of the memory cassette, data stored in the small ROM can be used in the main body of the game machine.

However, these game machines use only data in a small ROM cassette without any change in the development of the game itself, and thus do not completely satisfy the desire for various game development.

The development of various games and the execution of various other processes require large programs and large memory capacities for storing large programs. However, conventional game machines have the disadvantage that the memory capacity of the cassette body is limited in terms of transportation, processing or price.

In addition, conventional game machines are not able to reuse games developed in the past in a new game program, and thus the re-use of such old programs causes waste of processes, ROM, and other resources required to develop such programs. .

Accordingly, it is an object of the present invention to solve these problems by providing a data processing system that can realize various processes and utilize resources effectively. Yet another object is to provide a novel memory cassette structure for use with such a system.

A data processing system of the present invention according to claim 1 for solving such a problem includes a processing apparatus main body which performs a process according to stored contents of a memory cassette, a first memory cassette connectable to the processing apparatus main body, and A second memory cassette connectable to either the first memory cassette or the processing apparatus body, wherein a first address range when either the first memory cassette or the second memory cassette is connected to the processing apparatus body Reads data from the memory cassette within, and includes a second address range that does not overlap with the first address range when the processing apparatus body is connected to the first memory cassette and the second memory cassette is connected to the memory cassette. The data can be read from a wider address range.

The memory cassette according to claim 2 is a second memory cassette used in the data processing system according to claim 1, wherein the connector is electrically connectable to the connector of the first memory cassette or to the main body of the processing apparatus. A connection state determination circuit that judges whether or not the connector is connected to the first memory cassette through the connection state of the connector and outputs an address conversion signal corresponding to the above connection state, and an address conversion supplied from the connection state determination circuit. And a memory for outputting a signal and data corresponding to the address signal supplied from the connector.

The memory cassette according to claim 3 is the memory cassette according to claim 2, and when the connection state determination circuit determines that the connector is connected to the first memory cassette, the connection state determination circuit reads data from the memory. And outputting the address conversion signal to convert the address range to the second address range which does not overlap with the first address range for reading data from the memory of the first memory cassette.

The memory cassette according to claim 4 is the memory cassette according to claim 2, wherein when the signal logic of one of a plurality of pins constituting the connector becomes a predetermined signal logic, the connection state determination circuit is configured to connect the connector. It is characterized by determining that it is connected to another memory cassette.

The memory cassette according to claim 5 is the first memory cassette used for the data processing system according to claim 1, and can be connected to the memory cassette according to claims 2, 3, and 4 as the second memory cassette, Connectable to a first connector electrically connected to the processing apparatus main body, a memory for outputting data corresponding to an address signal supplied from the processing apparatus main body when connected to the processing apparatus main body via a first connector, and a second memory cassette And a second connector provided to transmit an address signal supplied from the main body of the processing apparatus through the first connector, wherein a predetermined pin of one of the plurality of pins constituting the second connector is held in predetermined signal logic. It is characterized by.

The memory cassette according to claim 6 is the second memory cassette used in the data processing system according to claim 1, the connector electrically connectable to a connector of the first memory cassette, and the data corresponding to the address signal supplied from the connector. And a memory for outputting a predetermined pin of one of the plurality of pins constituting the connector.

The memory cassette according to claim 7 is the first memory cassette used in the data processing system according to claim 1, which is connectable to the memory cassette according to claim 6 as the second memory cassette, and electrically connected to the processing apparatus main body. A first connector connectable to the second memory cassette and a second connector provided to transmit an address signal supplied from the processing apparatus main body through the first connector and whether the second memory cassette is connected to the second connector. A connection state determination circuit that judges whether or not the connection state of the second connector is to output an address conversion signal corresponding to the connection state, and an address conversion signal supplied from the connection state determination circuit and an address signal supplied from the first connector. And a memory for outputting corresponding data. The.

The memory cassette according to claim 8 is the memory cassette according to claim 7, wherein when the connection state determination circuit determines that the second connector is connected to the second memory cassette, the connection state determination circuit determines the first memory cassette. And outputting the address conversion signal to convert the address range for reading data from the memory of the memory into the second address range that does not overlap with the first address range for reading data from the memory of the second memory cassette. .

The memory cassette according to claim 9 is the memory cassette according to claim 7, wherein when the signal logic of one of the plurality of pins constituting the second connector becomes a predetermined signal logic, the connection state determination circuit is connected to the connector. Is determined to be connected to the second memory cassette.

The memory cassette according to claim 10 is the second memory cassette used in the data processing system according to claim 1, and is a connector electrically connectable to the first connector and outputs data corresponding to the address signal supplied from the connector. And a lead extending from a predetermined pin of one of the plurality of pins constituting the connector, the memory being connected to a chip select terminal of the memory.

The memory cassette according to claim 11 is the first memory cassette used in the data processing system according to claim 1, which is connectable to the memory cassette according to claim 10 as the second memory cassette, and electrically connected to the processing apparatus main body. A first connector capable of being connected to the second memory cassette and provided so that the address signal supplied from the processing apparatus body through the first connector can be transferred; a specific address signal supplied from the first connector According to the present invention, a connection for outputting a valid first chip select signal if the address signal is within the first address range and outputting a valid second chip select signal to a predetermined pin of the second connector if the address signal is within the second address range First chip select signal supplied from a state judgment circuit and a connection state judgment circuit Article characterized in that it comprises a memory for outputting the data corresponding to the address signal supplied from the first connector.

The memory cassette according to claim 12 is a memory cassette according to any one of claims 5, 7, 8, 9, or 11, and has a three-dimensional structure having two opposing surfaces, wherein each of the first connectors is provided on the opposing surfaces. And the second connector.

The data processing method according to claim 13 is connected to any one of a processing apparatus main body which performs processing according to stored contents of a memory cassette, a first memory cassette connectable to the processing apparatus main body, and the first memory cassette or processing apparatus main body. A data processing method using a second memory cassette that can be used, wherein when it is determined that either one of the first memory cassette or the second memory cassette is connected to the processing apparatus main body, the data is transferred from the memory cassette within the first address range. At a wider address range that reads and the processing apparatus main body is connected to the first memory cassette, and when the second memory cassette is connected to the cassette, the second address range not overlapping the first address range. The data is read.

Therefore, the present invention can satisfy the desire for various game development because the first and second memory cassettes can be used alone or in combination. In addition, by using two memory cassettes, a program using a large capacity memory can be used. In addition, since the old games can be reused, there is an effect that the development process, ROM, and other resources for such games can be effectively used.

Embodiments of the present invention will now be described with reference to the drawings.

1 is a perspective view showing a temporary example of a data processing system according to the present invention and a memory cassette structure used in the system.

The data processing system shown in FIG. 1 has a game machine main body 11, a first memory cassette 21 and a second memory cassette 31 as its components. On the connector 12 of the game machine main body 11, the connector 22 of the 1st cassette 21 is provided as shown by arrow X, and the connector of the 2nd cassette 31 as shown by arrow Y is shown. 32 can be installed.

In addition, the same connector 24 as the connector 12 provided in the main body 11 of the game machine is provided on the surface (shown as the upper surface) of the main body 23 of the first memory cassette 21 facing the connector 22. As indicated by the arrow Z, the connector 32 of the second cassette 31 may be disposed on the connector 24.

The connector 22 of the first memory cassette 21 is installed in the connector 12 of the main body 11 of the game machine as indicated by the arrow X, and the connector 32 of the second memory cassette 31 is indicated by the arrow Z. As shown, when installed in the connector 24 of the first cassette 21, the game machine main body 11 is in a state in which game programs of both the first cassette 21 and the second cassette 31 can be used. .

In order to be able to use the programs of both memory cassettes 21 and 31 in the game machine main body 11, a structure for dividing an address inside the first memory cassette 21 or the second memory cassette 31 is provided. . In this structure, the connector 22 of the first cassette 21 is installed in the connector 12 of the main body 11 of the game machine, and the connector 32 of the second cassette 31 is the connector of the first cassette 21. When it is installed in (24), it is activated. In this way, one of the memory address ranges of the memory cassettes 21 and 31 is converted and used.

Now, each component of the above data processing system will be described in detail. As shown in the figure, the game machine main body 11 of this embodiment has the parallelogram shape whose length is a little smaller than the width, and height is about 1/20 of the length. The connector 12 is provided on the upper surface of the three-dimensional body, and the switch 13 is provided on the lower left surface of the upper surface as shown.

The first memory cassette 21 includes a thin parallelogram housing 23. The connector 22 is provided on the lower surface 26 of the housing 23, and the connector 12 of the game machine body 11 is provided on the upper surface 27 of the housing 23 (the surface opposite the lower surface). A connector 24 having the same structure as that provided is provided.

The second cassette 31 also includes a thin parallelogram housing 35, with the connector 32 being provided on the lower face 36 of the housing 35. This structure makes it possible to install the connector 32 of the second cassette 31 also in the connector 12 of the main body 11 of the game machine 11 and the connector 24 of the first cassette 21.

2 is a circuit block diagram of the first and second memory cassettes used in one embodiment of the system related to the present invention.

In FIG. 2, the circuit system of the first memory cassette 21 includes a connector 22, a connector 24 and a mask ROM 28. In FIG. These connectors 22 and connectors 24 having the same pin number are connected to each other with signal wirings for the address Ad, the data Dt, and the control signal Ct. The wirings for the address Ad, the data Dt and the control signal Ct are configured to be connected to the mask ROM 28.

In addition, a connector 24 of a predetermined number of pins is connected to the ground electrode in the first memory cassette 21. When the connector 32 of the second cassette 31 is connected with the connector 24 of the first cassette 21, it comes into contact with the ground electrode of the connector 24. The pin inside the connector 24 is grounded. Therefore, the signals taken from the pins of the connector 24 are signals Sa indicating that the second cassette 31 is connected to the first cassette 21.

In the circuit system of the second cassette 31, the connector 32, the mask ROM 38, and the address conversion circuit 39 as the connection state determination means are provided. Each of the address Ad, the data Dt and the control signal Ct of the connector 32 of the predetermined pin number is connected to a predetermined pin of the mask ROM 38, and the address Ad and the control signal Ct and the signal Sa are connected to the address conversion circuit 39. It is connected to a predetermined electrode. The address conversion signal generated by the address conversion circuit 39 is supplied to the address change input terminal of the mask ROM 38.

3 is a circuit diagram showing an example of the structure of the address conversion circuit 39 described above.

In FIG. 3, the address conversion circuit 39 forms a first chip select signal CSa or a second chip select signal CSa according to a specific memory address Ad and a specific memory control signal Ct, and a decoder 391. And a selector circuit 392 for generating a signal for converting a memory address in accordance with the signal selection signals CSa and CSb from the signal Sa and the signal Sa indicating the connection of the first cassette 21 and the second cassette 31. It is composed as follows.

In the decoder 391, a wiring is arranged so that the address Ad and the control signal Ct are supplied to the decoder. This wiring causes the chip select signals CSa and CSb generated by the decoder 391 to be supplied to the A and B terminals of the selector circuit 392. Further, a wiring is arranged so that the signal Sa is supplied to the selection terminal A / B of the selector circuit 392. The output terminal Y of the selector circuit 392 is connected to the address conversion terminal of the mask ROM 38.

The operation of the above-described embodiment will now be described with reference to FIGS. 4 through 6 based on FIGS. Fig. 4 shows the operation when the first and second memory cassettes are combined with each other, and explains the relationship between the individual address values of the first and second memory cassettes and the address values when both cassettes are combined. FIG. 5 (a) is a flowchart showing the operation flow when only the second memory cassette is connected to the game machine body, and FIG. 5 (b) shows the flow of operation when only the first memory cassette is connected to the game machine body. 6 is a flowchart illustrating a memory map when the two cassettes are combined with each other.

First, as shown in FIG. 4C, the first memory cassette 21 stores its program data B from addresses 000000H (H is hexadecimal system indication) to 1FFFFFH. In the same manner, as shown in FIG. 4B, the second memory cassette 31 stores its program data A from addresses 000000H to 1FFFFFH.

If only the first memory cassette 21 is installed in the game machine main body 11 as indicated by the arrow X, the game machine main body 11 and the first memory cassette 21 are electrically connected through the connector 12 and the connector 22. It is connected. In this state, when the switch 13 of the game machine main body 11 is turned on and the power is turned on, the game machine main body 11 mainly starts at address 000000H to process necessary program data and the like (figure 5 (b)). Is immediately determined at the address 200000H and thereafter any program data or the like (step 201). This determination is made as follows. Assuming that the output of the game machine main body 11 at the address Ad is 200000H and the predetermined control signal Ct is outputted, only the need remains to determine whether any information can be obtained as the data Dt.

In this case, even if the address Ad and the control signal Ct are input to the mask ROM 28 as described above, no data is output from the mask ROM 28 to the data Dt. Thus, the game console main body 11 determines that program data does not exist at and after address 200000H (figure 51 (b) in step 201: NO), and from address 000000H to address 1FFFFFH of the first memory cassette 21; It is operated using only the stored program data B (step 202 of FIG. 5 (b)).

Similarly, as shown by arrow Y (FIG. 1), when only the 2nd cassette 31 is installed in the game console main body 11, the game console main body 11 and the 2nd cassette 31 are connected to the connector 12. In FIG. And a state electrically connected through the connector 32. In this state, when the switch 13 of the game machine main body 11 is turned on to allow current to flow (step 101 in FIG. 5 (a)), the game machine main body 11 is 1FFFFFH from 000000H of the second cassette 31. Only the program data A stored up to now is operated (fifth (a) in step 102).

Subsequently, as shown by arrow X in FIG. 1, a first memory cassette 21 is provided in the main body 11 of the game machine, and as shown by arrow Z, a second memory cassette ( 31) install. At this time, the game machine main body 11 and the first memory cassette 21 are electrically connected through the connector 12 and the connector 22, and the first memory cassette 21 and the second memory cassette 31 are connected to the connector ( 24) and the connector 32 to be electrically connected.

On the other hand, when the switch 13 of the main body 11 of the game machine is switched on and current flows, the signal Sa indicating the connection state becomes L and the second memory cassette 31 is connected through the connector 24 and the connector 32. Is provided to the address conversion circuit 39. At this time, the game machine main body 11 processes necessary program data (vector), starting execution basically from the address 000000H (step 200).

As a result, the game machine main body 11 determines whether there is any program data after the address 200000H (step 201). Thus, the game machine main body 11 forms an address Ad for the address starting from 200000H, provides a control signal Ct, and determines whether there is any information as the data Dt.

When the address Ad and the control signal Ct are input to the address conversion circuit 39, the address conversion circuit 39 forms the chip select signal CSb in the decoder 391 according to the address Ad and the control signal Ct. This chip select signal CSb is provided to the mask ROM 38 via the selection circuit 392 when the signal Sa indicating the connection state indicates L. FIG.

As a result, the address of the mask ROM 38 is converted from its 200000H to 2FFFFFFH. Subsequently, when the first memory cassette 21 and the second memory cassette 31 are combined with each other, the address of the mask ROM 28 of the first memory cassette 21 is as shown in FIGS. 4A and 6. Although from 000000H to 1FFFFFH, the address of the mask ROM 38 of the second memory cassette 31 is allocated from 200000H to 2FFFFFH.

When the address of the second memory cassette 31 is converted as described above, the designation of an address of 200000H or later by the game console main body 11 outputs the information of the address from the mask ROM 38 to the data wiring. Becomes

In other words, when the game console main body 11 finds some kind of information at the designated address (step 201), it is determined whether program data exists after the address 200000H (step 201; YES), and then the game console main body 11 Is operated by the program data B stored at 1FFFFFH from address 000000H in the first memory cassette 21 and the program data A stored at addresses 200000H to 3FFFFFH in the second memory cassette 31 (step 203).

That is, when the game console main body 11 determines that the first memory cassette 21 and the second memory cassette 31 are coupled to each other, they can be freely accessed as described above.

In a state in which the first memory cassette 21 and the second memory cassette 31 are coupled to each other, as shown in FIG. 6, in the first memory cassette, program areas exist from 000000H to XXXXXXH, and the data area is XXXXXXH. To 1FFFFFH. As shown in Fig. 6, in the second memory cassette 31, program areas range from 200000H to XXXXXH and data areas range from XXXXXXH to 3FFFFFH.

According to the embodiment described above, since the first memory cassette 21 and the second memory cassette 31 can be used alone or in combination (connected) with each other, various demands for the development of various games can be accommodated. In addition, since two memory cassettes can be used simultaneously, a large program capacity can be used. Furthermore, by installing the second memory cassette in the first memory cassette, the old game can be reused, so that the development process, ROM, and other resources for the game can be effectively used.

7 is a diagram showing the configuration of another embodiment of the first and second memory cassettes used in the embodiment of the present invention. In FIG. 7, the same reference numerals are given to the same components as those in FIG.

The circuit system of the first memory cassette 21 includes a connector 22, a connector 24, a mask ROM 28 and an address conversion circuit 29 as circuits for determining a connection state, and the connectors 22 and 24. The wirings having the same pin number are connected as signal wirings for the address Ad, the data Dt, and the control signal Ct. The wirings for the address Ad, the data Dt and the control signal Ct were configured to be connected to the mask ROM 28.

The address Ad, the control signal Ct, and the signal Sa are connected to predetermined electrodes of the address conversion circuit 29, and the address conversion signal generated by the address conversion circuit 29 is used to change the address of the mask ROM 28. Supplied to the terminal. The address conversion circuit 29 has the same circuit configuration as the address conversion circuit 39 shown in FIG.

The circuit system of the second memory cassette also includes a connector 32 and a mask ROM 38. The address Ad, the data Dt, and the control signal Ct of the connector 32 having a predetermined pin number having the predetermined pin number of the connector 32 connected to the predetermined pin of the mask ROM 38 are configured to be connected to the ground electrode.

The operation of this embodiment will be described with reference to FIGS. 5 and 8 on the basis of FIG. 1, FIG. 3 and FIG. 8 illustrates a memory map when both cassettes are combined.

First, the first memory cassette 21 and the second memory cassette 31 separately store the program data B and A up to the addresses 000000H to 1FFFFFH as described above.

Subsequently, as shown by the arrow Y (FIG. 1), if only the second memory cassette 31 is provided in the game machine main body 11, as described above, the game machine main body 11 is the second memory cassette 31. As shown in FIG. It operates according to program data A stored only from 000000H to 1FFFFFH (FIG. 5, steps 101,102).

Similarly, if only the first memory cassette 21 is installed in the game machine main body 11 as indicated by arrow X (FIG. 1), the game machine main body starts operation from 000000H as described above, and supplies necessary program data. Processing (step 200), it is immediately determined whether program data exists after the address 200000H (step 201), and it operates according to only program B stored up to addresses 000000H to 1FFFFFH (step 202).

Subsequently, the first memory cassette 21 is installed in the game machine main body 11 in the direction of the arrow X, and the second memory cassette 31 is provided on the first memory cassette 21 in accordance with the arrow Z. At this time, the game machine main body 11 and the first memory cassette 21 are electrically connected through the connector 12 and the connector 22, and the first memory cassette 21 and the second memory cassette 31 are It is electrically connected through the connector 24 and the connector 32. In this state, electric current flows by turning on the switch 13 of the game machine main body 11, and the signal Sa which shows the connection state turns into L, and this signal Sa is made through the connector 32 and the connector 24. It is provided to the address conversion circuit 29 of one memory cassette 21.

Thus, when the game machine main body 11 outputs the control signal Ct using the address Ad after the address 200000H, the address conversion signal is output from the address conversion circuit 29 to the mask ROM 28. Through this address conversion signal, the address of the mask ROM 28 is translated, and the address of the mask ROM 28 moves from 200000H to 3FFFFFH as shown in FIG. At this time, the main body 11 of the game machine basically starts the operation from 000000H, but forcibly converts the vector of the first memory cassette 21 to the address 000000H of the second memory cassette 31 to convert the necessary program data (vector). Process. Therefore, the program A of the second memory cassette 31 can be continuously operated.

Subsequently, the game machine main body 11 determines whether a program exists after the address 200000H (step 201; YES). This determination is made by judging whether or not the information is output to the data Dt when the address Ad is output from the address 200000H and the control signal Ct is output. When this address Ad and the control signal Ct are input to the address conversion circuit 29, the address conversion circuit 29 generates a chip select signal in accordance with the address Ad and the control signal Ct, and from these chip select signals, A signal Sa indicating the connection state L is generated and provided to the mask ROM 28.

Accordingly, when the address assigned to the mask ROM 28 is converted from 200000H to 3FFFFFH, when the first memory cassette 21 and the second memory cassette 31 are combined with each other, as shown in FIG. The address of the mask ROM 28 of the memory cassette 21 is converted from 200000H to 3FFFFFH, and the address of the mask ROM 38 of the second memory cassette 31 is converted from 000000H to 1FFFFFH. Since the address of the first memory cassette 21 is converted as described above, designation of an address after 200000H by the game console main body 11, that is, information of the address is output from the mask ROM 28 to the data Dt.

Therefore, in the game machine main body 11, if the information is obtained at a specific address as described above, it is determined that there is program data after 200000H (step 201; YES), and then the game machine main body 11 is the first memory cassette. It is operated using both program data B stored from addresses 200000H to 3FFFFFH and program data A stored from addresses 200000H to 3FFFFFH in the second memory cassette 31 (step 203). In other words, when it is determined that both the first memory cassette 21 and the second memory cassette 31 are installed as described above, the game machine main body 11 can freely access both cassettes.

In the state where the first memory cassette 21 and the second memory cassette 31 are installed as described above, the first memory cassette 21 has its program area from addresses 200000H to XXXXXXH as shown in FIG. Has its data area from XXXXXXH to 3FFFFFH. As shown in Fig. 8, the second memory cassette 31 has its program area from 000000H to XXXXXXH and its data area from XXXXXXH to 1FFFFFH.

9 is another embodiment of the first and second memory cassettes used in the present invention. The embodiment of FIG. 9 differs from the embodiment of FIG. 7 in that the chip select signal * CS (* is an inverse representation of CS) is supplied from the main body 11 of the game machine 11 to the decoder 40 via the connector 22, The address is supplied to the decoder 40. Another difference from the embodiment of FIG. 7 is that the chip select signal CSa and the chip select signal CSb are generated by the decoder 40, the electrical wiring is supplied to the mask ROM 28, and the chip select signal CSa is supplied to the chip select signal CSb. Is arranged to be supplied to the mask ROM 38 of the second memory cassette 31 via a predetermined pin number portion of the connector 24 and the same pin number portion of the connector 32. The other configuration is the same as that in FIG. Like parts in FIGS. 9 and 7 have the same reference numerals.

10 is a circuit diagram showing an example of a specific configuration of a decoder. As shown in FIG. 10, the decoder 40 consists of two NAND circuits 401 and 402 and two inverter circuits 403 and 404, and has the following connection states. The electrical connection causes the address * ax (* where ax indicates reverse) to be provided directly through the inverter circuit 403 to one input terminal of the NAND circuit 401 and one input terminal of the NAND circuit 402. . In addition, the electrical connection is such that the chip select signal * CS transmitted from the main body 11 of the game machine through the connector 12 and the connector 22 of the first memory cassette 21 is connected to the NAND circuit 401 through the inverter circuit 404. The output is input to the other input terminal of the NAND circuits 401 and 402.

The chip select signal CSa is output from the output terminal of the NAND circuit 401, and the chip select signal CSb is output from the output terminal of the NAND circuit 402, respectively.

In this embodiment, since the first memory cassette 21 and the second memory cassette 31 can be used individually or in combination, they can satisfy various game development requirements. Also, by using two memory cassettes, a large amount of program capacity can be used. In addition, the old game can be reused, so that the development process, the ROM and other resources of the game can be effectively used.

This embodiment will be described in detail with reference to FIGS. 9, 10, 11, and 12. FIG. 11 illustrates a memory map arranged in accordance with the embodiment of FIG. 12 is an illustration using the operation of the above embodiment.

The game machine main body 11 can output the address * ax used for switching of the 1st memory cassette 21 or the 2nd memory cassette 31, and can simultaneously output the chip selection signal * CS.

In this state, as shown in FIG. 12, when the address * ax is L (0) and the chip select signal * cs output from the game console main body 11 is L (0), the amount of the NAND circuit 401 The input terminal becomes H (1) and the output of the NAND circuit 401 becomes L (0). Since one input terminal of the NAND circuit 402 is L (0), the output of the NAND circuit 402 becomes H (1).

That is, when the chip select signal CSa is output from the decoder 40, the game machine main body 11 can thereby use a program or the like stored in the first memory cassette 21. Thus, as shown in FIG. 11, addresses 000000H to 1FFFFFH can be used in the first memory cassette 21. As shown in FIG. At this time, only the first memory cassette 21 is installed in the main body 11 of the game machine, or the second memory cassette 31 is installed on the first memory cassette 21 installed in the main body 11 of the game machine 11 (combined with each other). Irrespective of this, the game machine main body 11 uses the program of the first memory cassette 21.

On the other hand, as shown in Fig. 12, the specific address * ax (in this case, for example, using the sixth data Dt in 200000H) is H (1), and the chip select signal * output from the game console main body 11 is shown. If cs is L (0), both input terminals of the NAND circuit 402 become H (1), and the output of the NAND circuit 402 becomes L (0). In addition, since one input terminal of the NAND circuit 401 is L (0), the output of the NAND circuit 401 becomes H (1). The chip select signal CSb is then output from the decoder 40.

As a result, the main body 11 of the game machine cannot access the first memory cassette 21 and can only access the second memory cassette 31. Therefore, since the address Ad is 3FFFFFH from 200000H, the game machine main body 11 can use the program etc. which were stored in the 2nd memory cassette 31. FIG. Therefore, as shown in Fig. 11, a second memory cassette 31 which is converted from 200000H to 3FFFFFH is used.

In addition, when the chip select signal * CS is H (1), the output terminals of the NAND circuits 401 and 402 of the decoder 40 output the H (1) regardless of the address value * ax, so that the first memory cassette 21 ) And the second memory cassette 31 become inaccessible.

If only the second memory cassette 31 is provided in the game machine main body 11, the chip select signal * cs is directly input to the mask ROM 38 of the second memory cassette 31, so that the second memory cassette 31 is provided. Can use 000000H to 1FFFFFH address.

According to this embodiment, the first memory cassette 21 and the second memory cassette 31 can be used individually or in combination to satisfy the demand for diversification of game development. In addition, since two memory cassettes can be used, a large program capacity can be used. In addition, since the old game can be reused, there is an advantage that the game development process, ROM and other resources can be effectively used.

Further, in the embodiment of the present invention, the circuit for determining the connection state may be provided on the side of the game main body, that is, the processing apparatus main body.

Claims (15)

a) a processing apparatus main body which executes processing in accordance with the stored contents of the memory cassette, b) a first memory cassette that can be connected to the processing apparatus main body, and c) the first memory cassette or the processing apparatus main body can be connected. And a second memory cassette, wherein the first memory cassette or the second memory cassette reads data from the memory cassette in a first address range when the first memory cassette or the second memory cassette is connected to the processing apparatus main body, and the processing apparatus main body reads the first memory cassette. A data processing system characterized in that when data is connected to one memory cassette and the second memory cassette is connected to the memory cassette, data is read in a wider address range including a second address that does not overlap with the first address range. A memory cassette as the second memory cassette for use in a data processing system according to claim 1, comprising: a) a connector electrically connected to the connector of the first memory cassette or the main body of the processing apparatus, b) the connector being connected to the first memory cassette; A connection state determination circuit that outputs an address conversion signal corresponding to the connection state by judging whether or not a memory cassette is connected to the memory cassette; and c) an address conversion signal supplied from the connection state determination circuit and the And a memory for outputting data corresponding to the address signal supplied from the connector. 3. The memory of claim 1, wherein if the connection state determination circuit determines that the connector is connected to the first memory cassette, the connection state determination circuit determines an address range for reading data from the memory. And outputting said address translation signal for conversion to said second address range that does not overlap with said first address range for reading data from. The connection state determining circuit determines that the connector is connected to another memory cassette when the signal logic of one specific pin of the plurality of pins constituting the connector is a predetermined signal logic. Memory cassette. A memory cassette as the first memory cassette used in the data processing system according to claim 1 and connectable to the memory cassette according to claims 2, 3 and 4 as the second memory cassette, comprising: a) electrically to the main body of the processing apparatus; A connectable first connector, b) a memory for outputting data corresponding to an address signal supplied from said processing apparatus main body when connected to said processing apparatus main body via said first connector, and c) connecting to said second memory cassette And a second connector provided to transmit an address signal supplied from the main body of the processing apparatus through the first connector, wherein a predetermined pin of one of the plurality of pins constituting the second connector is predetermined. A memory cassette characterized by being held in signal logic. A memory cassette as the second memory cassette used in the data processing system according to claim 1, comprising: a) a connector electrically connectable to a connector of the first memory cassette, and b) an address signal supplied from the connector And a memory for outputting data, wherein one particular pin of the plurality of pins constituting the connector is held in predetermined signal logic. A memory cassette as the first memory cassette used in the data processing system according to claim 1 and connectable to the memory cassette according to claim 6 as the second memory cassette, comprising: a) electrically connectable to the processing apparatus main body; A first connector, b) a second connector connectable to the second memory cassette and provided to transmit an address signal supplied from the processing apparatus main body through the first connector, c) a second memory cassette to the second connector A connection state determination circuit for judging whether or not the connection is made by the second connector and outputting an address conversion signal corresponding to the connection state; and d) an address change signal supplied from the connection state determination circuit and the first connection state. Memory for outputting data corresponding to the address signal supplied from the connector Memory cassette comprising a. The address determining circuit according to claim 7, wherein the connection state determining circuit reads data from the memory of the first memory cassette when the connection state determining circuit determines that the second connector is connected to the second memory cassette. And outputting the address translation signal to convert a range into the second address range that does not overlap with the first address range that reads data from the memory of the second memory cassette. 8. The connection state determination circuit of claim 7, wherein the connection state determining circuit is connected to the second memory cassette when the signal logic of one of the plurality of pins constituting the second connector is predetermined signal logic. And a memory cassette, which is judged to be present. A memory cassette as the second memory cassette used in the data processing system according to claim 1, comprising: a) a connector electrically connectable to the first connector, and b) data corresponding to the address signal supplied from the connector. And a memory extending from a specific pin of one of the plurality of pins constituting the connector, the memory being output to a chip select terminal of the memory. A memory cassette as the first memory cassette used in the data processing system according to claim 1 and connectable to the memory cassette according to claim 10 as the second memory cassette, comprising: a) an agent electrically connected to the processing apparatus main body; A first connector, b) a second connector connectable to said second memory cassette, said second connector being provided so as to transmit said address signal supplied from said processing apparatus main body via said first connector. c) outputting a valid first chip select signal when the address signal is within the first address range, in accordance with a particular address signal supplied from the first connector, and valid second when the address signal is within the second address range And a connection state determination circuit for outputting a chip select signal to a predetermined pin of the second connector. d) a memory for outputting data corresponding to a first chip select signal supplied from said connection state determination circuit and an address signal supplied from said first connector. 6. The memory cassette of claim 5, wherein the memory cassette has a three-dimensional configuration comprising two opposing surfaces, and wherein the first connector and the second connector are provided on the opposing surface, respectively. Data processing using a processing apparatus main body that executes processing in accordance with stored contents of a memory cassette, a first memory cassette connectable to the processing apparatus main body, and a second memory cassette connectable to the first memory cassette or the processing apparatus main body. A method, comprising: reading data from the memory cassette in a first address range when it is determined that the first memory cassette or the second memory cassette is connected to the processing apparatus main body, and wherein the processing apparatus main body is configured to read the data from the memory cassette. When it is determined that the second memory cassette is connected to the first memory cassette, the data is read from a wider address range including the second address range that does not overlap with the first address range. And processing the data. 10. The memory cassette of claim 7, wherein the memory cassette has a three-dimensional configuration including two opposing surfaces, and wherein the first connector and the second connector are provided on the opposing surface, respectively. A memory cassette characterized by the above-mentioned. 12. The memory cassette of claim 11, wherein the memory cassette has a three-dimensional configuration including two opposing surfaces, and wherein the first connector and the second connector are provided on the opposing surface, respectively.