GB2255451A - Ceramic three dimensional electronic structures - Google Patents

Ceramic three dimensional electronic structures Download PDF

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Publication number
GB2255451A
GB2255451A GB9109687A GB9109687A GB2255451A GB 2255451 A GB2255451 A GB 2255451A GB 9109687 A GB9109687 A GB 9109687A GB 9109687 A GB9109687 A GB 9109687A GB 2255451 A GB2255451 A GB 2255451A
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United Kingdom
Prior art keywords
substrate
stack
laminated
green sheets
sheets
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Granted
Application number
GB9109687A
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GB9109687D0 (en
GB2255451B (en
Inventor
Elizabeth Anne Logan
Kevin Joseph Lodge
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAE Systems Electronics Ltd
Original Assignee
GEC Marconi Ltd
Marconi Co Ltd
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Priority to GB9109687A priority Critical patent/GB2255451B/en
Publication of GB9109687D0 publication Critical patent/GB9109687D0/en
Publication of GB2255451A publication Critical patent/GB2255451A/en
Application granted granted Critical
Publication of GB2255451B publication Critical patent/GB2255451B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B18/00—Layered products essentially comprising ceramics, e.g. refractory products
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B35/00—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
    • C04B35/622—Forming processes; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
    • C04B35/64—Burning or sintering processes
    • C04B35/645—Pressure sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/4807—Ceramic parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0014—Shaping of the substrate, e.g. by moulding
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B2235/00—Aspects relating to ceramic starting mixtures or sintered ceramic products
    • C04B2235/65—Aspects relating to heat treatments of ceramic bodies such as green ceramics or pre-sintered ceramics, e.g. burning, sintering or melting processes
    • C04B2235/656—Aspects relating to heat treatments of ceramic bodies such as green ceramics or pre-sintered ceramics, e.g. burning, sintering or melting processes characterised by specific heating conditions during heat treatment
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B2235/00—Aspects relating to ceramic starting mixtures or sintered ceramic products
    • C04B2235/65—Aspects relating to heat treatments of ceramic bodies such as green ceramics or pre-sintered ceramics, e.g. burning, sintering or melting processes
    • C04B2235/656—Aspects relating to heat treatments of ceramic bodies such as green ceramics or pre-sintered ceramics, e.g. burning, sintering or melting processes characterised by specific heating conditions during heat treatment
    • C04B2235/6567—Treatment time
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B2235/00—Aspects relating to ceramic starting mixtures or sintered ceramic products
    • C04B2235/65—Aspects relating to heat treatments of ceramic bodies such as green ceramics or pre-sintered ceramics, e.g. burning, sintering or melting processes
    • C04B2235/658—Atmosphere during thermal treatment
    • C04B2235/6583—Oxygen containing atmosphere, e.g. with changing oxygen pressures
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
    • C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
    • C04B2237/32—Ceramic
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
    • C04B2237/50—Processing aspects relating to ceramic laminates or to the joining of ceramic articles with other articles by heating
    • C04B2237/62—Forming laminates or joined articles comprising holes, channels or other types of openings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
    • H05K2203/302—Bending a rigid substrate; Breaking rigid substrates by bending
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Structural Engineering (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A three dimensional integrated electronic structure include at least one substrate formed from a laminated stack of ceramic green unfired sheets, at least one of which has a printed circuit formed on its surface. The laminated stack is sintered and electronic devices are mounted on the sintered substrate. The substrate is shaped, formed, moulded or designed so as to provide thereto a predetermined profile suitable for mounting, fixing or locating the structure in a pre-selected enclosure apparatus, machine or the like. The predetermined profile can be given to the structure at any one of three stages in the production process thereof; viz a) before the laminating step; b) during the laminating step, and c) after the laminating step. <IMAGE>

Description

Ceramic Three Dimensional Electronic Structures This invention relates to monolithic three dimensional electronic structures and a method of making the same. The three dimensional electronic structures of the present invention will give military and professional electronic designers additional design freedoms to better utilise the space available to them, in a high reliability format. It utilises the newly developed low-dielectric, low-temperature firing, glass-ceramic tapes to make reliable, three dimensional substrates which combine the electrial interconnect function with that of structural support.
Demands for increased performance from aviation equipment has led to a proliferation in electronic sub-systems, all struggling to fit into a weight/volume envelope which is already under pressure from the performance requirements of the overall system. Silicon integration, and novel interconnection schemes such as multichip modules are helping to ease that pressure, but the finite size of passive components and the interconnection structures, coupled with the limited and often non-orthogonal spaces that sub-systems must be fitted into, mean increasing problems for the designer, not assisted by a constant customer demand for reduced costs and greater value for money. The introduction of more integrated opto-electronics into these systems is likely to make the matter worse, with demands for minimum bend radii for lightguides and line of sight interconnections.
Similar pressures in the area of consumer electronics, assisted by the introduction of engineering polymers capable of withstanding soldering temperatures, has led to the development of three dimensional moulded printed circuit boards. These claim to offer better electrical and mechanical performance than standard pcbs; greater design freedom with the removal of the need to accomodate all the components on flat circuit boards; space savings by incorporating components onto the structure of the equipment; improved reliability by integrating connectors into the structure; and reduced costs, due to the elimination of the need to machine slots, recesses or vias in the board. Additional cost savings arise during the assembly process as it is possible to mould component holding fixtures, snap-ons and stiffening ribs into the initial basic structure.Over the last few years a large number of technologies and prototypes have been developed. The production of such structures has required a great deal of development of the infrastructure; in the design and development in 3-D CAD tools; methods of placing and holding components on non-planar surfaces; soldering methods; test and inspection. Not all of these problems have been solved but progress has been made and some products, usually with an integrated electrical/mechanical function, have been produced.
In the military and professional environment, apart from some early proposals for electronic integration into the composite skin of an aircraft (a concept now known as 'smart skin'), little work is known in the field of structural/electronic integration. Three dimensional structures are used but are built up by hand from individual flat substrates. An example of this approach is the Tx/Rx unit, which is used in large numbers in some phase array radars.
These have a distributor circuit mounted on the lens at the base of the structure, with the Tx unit fixed vertically on one side of it and the Rx circuit on the other side to form a 'U' shaped unit.
Electrical connection, and some of the mechanical strength, is achieved through hand made solder joints where the units meet. This results in units that are costly to build, with unit to unit variability due to the hand soldered joint.
According to the invention there is provided a three dimensional integrated electronic structure including a substrate or substrates, the substrate or each substrate being formed of a laminated stack of ceramic green sheets, at least one of the ceramic green sheets of the substrate or each substrate having a printed circuit formed on the surface thereof, said laminated stack of green sheets or each of said laminated stack of green sheets being sintered and electronic devices mounted on said sintered substrate or substrates and wherein said substrate or each said substrate is shaped, formed, moulded or designed so as to provide thereto a predetermined profile suitable for mounting, fixing or locating said structure in a preselected enclosure, apparatus, machine or the like.
According to one embodiment of a method of forming the three dimensional electronic structure of the present invention, each of said green ceramic sheets is shaped, formed, moulded or designed such that when said sheets are laminated and sintered, said structure of predetermined profile is formed.
According to another embodiment of a method of forming the three dimensional electronic structure of the present invention, the stack of sheets or each of said stack of sheets is shaped, formed, moulded or designed during lamination thereof to provide said predetermined profile thereto.
According to still another embodiment of a method of forming the three dimensional electronic structure of the present invention, said laminated stack of green sheets is shaped, formed, moulded or designed during sintering thereof to provide said predetermined profile thereto.
The stack of green sheets or each said stack of green sheets may be laminated at a temperature of 60 C to 150@C and at a pressure between 3.45xlO3kPa and 3.45xlO4kPa (500 Psi and 5000 Psi) using copper or graphite formers for example to achieve said predetermined profile.
Typically the stacks of green sheets are laminated at a temperature of 700C and a pressure of 2.1xlO4kPa (3000 Psi).
The invention will now be described further by way of example with reference to the accompanying drawings in which: Figure la-g illustrates a conventional method of forming a known two dimensional integrated electronic structure; Figure 2a-f illustrates a method of forming a three dimensional integrated electronic structure embodying the present invention; Figure 3a-d illustrates another method of forming a three dimensional integrated electronic structure embodying the present invention; Figure 4a-e illustrates an alternative method of forming a three dimensional integrated electronic structure embodying the present invention.
The advent of low temperature firing ceramic tapes in 'green' (ie unfired) form could allow an opportunity for military systems to gain some of the benefits of moulded circuit boards combined with the benefits and reliability of cofired and thick film technology. These materials are a mixture of ceramic powders with suitable binders and are supplied unfired in the form of rolls of unfired tape (Fig. la).
The production sequence for conventional flat substrates, well known to those skilled in the art, is shown in outline in Fig. la to Fig. lg and is described in more detail by J.I.Steinberg, S. J. Horowitz & R.
J. Bacher, in "Low Temperature Co-Fired Dielectric Material System for Multi-Layer Interconnections", 5th European ISHM Conference, Stresa, Italy, May 1985. The process starts by cutting tiles from the roll of tape (Fig. la). The tile is then punched with a series of small via holes, to allow later interconnection through the substrate, along with larger holes for alignment pins (Fig. lah). The via holes are then filed with a conducting paste or ink, and a pattern of conductors is printed on the surface of the tile in the same or compatible ink system (Fig. inc). The tile and inks are then allowed to dry before it is stacked with other tiles on alignment pins and subjected to moderate heat and pressure, of the order of 70etc and 2.1xlO4kPa (3000 psi) (Fig. led). Final burn out is carried out in two steps.
The laminated substrate is placed on a flat carrier and burnt out in air, typically at 350ec for one hour (Fig. le), removing about 85% of the organic materials in this process. The same carrier and tile is then passed, in a one hour cycle, through a standard thick film firing oven with with a peak temperature of 850eC for 15 minutes. The tile now has the final dimension (Fig. if). The final processes, printing and firing the surface conductors and trimming any resistors etc, are now carried out (Fig lg) to produce a flat, co-fired, application specific ceramic (or more correctly glass-ceramic) substrate.Recent developments in low temperature ceramic tape technology have produced material of lower dielectric constant (5.8) than alumina and claimed insertion losses of 0.2 dB/inch at 10GHz, (twice that at 20GHz), making the substrate potentially useful at microwave frequencies.
This invention consists of a method of modifying the process used in making these flat co-fired ceramic substrates to produce shaped substrates. In addition, inserts, cut-outs and recesses could be cut in the green material before the stack is laminated, complete with any additional stand-offs and component locations . Different design rules would be needed from those applied to standard, flat structures made from low-temperature firing tape, to allow for the relative movement between the planes, differential shrinkage and geometric restrictions on shrinkage.
These modifications can take place at three stages in the production process; before the laminating step; during the laminating step; or after this stage. Figures 2a-f show the steps needed for the pre-laminating shaping process, where the tiles are bent whilst still in the unfired, green stage. At this stage the tape has the consistency of hard rubber and can be bent into non-planar shapes, possibly using a former or mould (Fig. 2d).
Assemblies of these 'bent' sheets could be assembled on a former, using alignment pins in slits to allow for the shrinkage on firing, and laminated into 'bent' substrates (Figs 2d to 2f). Figures 3a-d show the process of moulding the shaped substrate from a flat stack of tiles during the lamination stage, using the moderate temperatures and pressures to push the stack onto a shaped former. The final method illustrated in Figures 4a-4e does not use applied pressure on the laminated flat stack, but relies on the lack of structural strength of the substrate during burn-out and firing to enable the pliable substrate to take up the shape of the former it is sitting on.
In all three methods described with reference to Figures 2 to 4, the shaped laminated substrate would then be cofired, populated with devices and soldered. The final structure should show improved mechanical and electrical reliability due to the removal of the soldered joints, improved electrical performance both from the improved dielectric properties of the materials and from the reduced reflections from smooth, rounded transitions in board direction; better space utilizations and improved value for money due to savings on assembly.

Claims (8)

1. A three dimensional integrated electronic structure including a substrate or substrates, the substrate or each substrate being formed of a laminated stack of ceramic green sheets, at least one of the ceramic green sheets of the substrate or each substrate having a printed circuit formed on the surface thereof, said laminated stack of green sheets or each of said laminated stack of green sheets being sintered and electronic devices mounted on said sintered substrate or substrates and wherein said substrate or each said substrate is shaped, formed, moulded or designed so as to provide thereto a predetermined profile suitable for mounting, fixing or locating said structure in a preselected enclosure, apparatus, machine or the like.
2. A method for forming a three dimensional integrated electronic structure as claimed in Claim 1, in which each of said green ceramic sheets is shaped, formed, moulded or designed such that, when said sheets are laminated and sintered, said structure of predetermined profile is formed.
3. A method of forming a three dimensional integrated electronic structure as claimed in Claim 1, in which said stack of sheets or each said stack of sheets is shaped, formed, moulded or designed during lamination thereof to provide said predetermined profile thereto.
4. A method of forming a three dimensional integrated electronic structure as claimed in Claim 1, in which said laminated stack of green sheets or each said laminated stack of green sheets is shaped, formed, moulded or designed during sintering thereof to provide said predetermined profile thereto.
5. A method as claimed in Claim 3, in which said stack of green sheets or each said stack of green sheets is laminated at a temperature of 50 C to 150 C and at a pressure between 3.45xlO3kPa and 3.45x104kPa (500 Psi and 5000 Psi) using copper or graphite formers to achieve said predetermined profile.
6. A method as claimed in Claim 5, in which said stack of green sheets or each said stack of green sheets is laminated at a temperature of 70 C and at a pressure of 2.1xlO4kPa (3000 Psi).
7. A three dimensional integrated electronic substrate/structure substantially as hereinbefore described with reference to any one of figures 2 to 4 of the accompanying drawings.
8. A method of forming a three dimensional electronic structure substantially as hereinbefore described with reference to figures 2 to 4 of the accompanying drawings.
GB9109687A 1991-05-03 1991-05-03 Ceramic three dimensional electronic structures Expired - Fee Related GB2255451B (en)

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GB2255451A true GB2255451A (en) 1992-11-04
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0595075A2 (en) * 1992-10-30 1994-05-04 Corning Incorporated Microlaminated composites and method for preparing them
WO1997032455A2 (en) * 1996-03-01 1997-09-04 Copp John B Printed circuit board fabrication apparatus
EP0872882A2 (en) * 1997-04-15 1998-10-21 Curamik Electronics GmbH Method of fabricating a curved metal-ceramic-substrate
EP1416546A1 (en) * 2002-10-21 2004-05-06 Friedrich-Alexander-Universität Erlangen-Nürnberg Method of making a laminated ceramic with a non-planar structure
US7205655B2 (en) 2001-10-23 2007-04-17 Schaffner Emv Ag Multilayer circuit including stacked layers of insulating material and conductive sections
EP2825004A4 (en) * 2012-03-06 2015-12-23 Tyco Electronics Japan G K Three-dimensional laminated wiring substrate
EP2871172A4 (en) * 2012-07-03 2016-07-13 Kuang Chi Innovative Tech Ltd Metamaterial and manufacturing method threfor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0186550B1 (en) * 1984-12-28 1992-03-25 Fujitsu Limited Process for producing multilayer ceramic circuit board with copper

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0186550B1 (en) * 1984-12-28 1992-03-25 Fujitsu Limited Process for producing multilayer ceramic circuit board with copper

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0595075A2 (en) * 1992-10-30 1994-05-04 Corning Incorporated Microlaminated composites and method for preparing them
EP0595075A3 (en) * 1992-10-30 1994-11-17 Corning Inc Microlaminated composites and method for preparing them.
US5987736A (en) * 1996-03-01 1999-11-23 Copp; John B. Printed circuit board fabrication apparatus
WO1997032455A3 (en) * 1996-03-01 1997-10-30 John B Copp Printed circuit board fabrication apparatus
WO1997032455A2 (en) * 1996-03-01 1997-09-04 Copp John B Printed circuit board fabrication apparatus
EP0872882A2 (en) * 1997-04-15 1998-10-21 Curamik Electronics GmbH Method of fabricating a curved metal-ceramic-substrate
EP0872882A3 (en) * 1997-04-15 1999-04-21 Curamik Electronics GmbH Method of fabricating a curved metal-ceramic-substrate
DE19715540C2 (en) * 1997-04-15 2002-02-07 Curamik Electronics Gmbh Method of manufacturing a domed metal-ceramic substrate
US7205655B2 (en) 2001-10-23 2007-04-17 Schaffner Emv Ag Multilayer circuit including stacked layers of insulating material and conductive sections
EP1416546A1 (en) * 2002-10-21 2004-05-06 Friedrich-Alexander-Universität Erlangen-Nürnberg Method of making a laminated ceramic with a non-planar structure
EP2825004A4 (en) * 2012-03-06 2015-12-23 Tyco Electronics Japan G K Three-dimensional laminated wiring substrate
US9894758B2 (en) 2012-03-06 2018-02-13 Tyco Electronics Japan G.K. Three-dimensional laminated wiring substrate
EP2871172A4 (en) * 2012-07-03 2016-07-13 Kuang Chi Innovative Tech Ltd Metamaterial and manufacturing method threfor

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Publication number Publication date
GB9109687D0 (en) 1991-06-26
GB2255451B (en) 1995-01-25

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