GB2248534A - Digital video processing apparatus - Google Patents

Abstract

A digital video luma or chroma signal supplied to an input port 18 is routed by a switching arrangement 17 to selected ones of a set of field stores 11 to 16 having respective input/output video ports. The input video data is read from selected field stores through a pixel string resampler 20, that can increase or decrease the number of pixels corresponding to a selected segment of the input pixels, to other field stores. On a first pass through the resampler 20, video data is processed vertically, and on a second pass is processed horizontally, so that two dimensional distortions can be effected. The output pixel values are adjusted accordingly in the resampler 20. A host computer 21 exercises overall control. Processed fields are read out through an output port 19. Switching arrangement 17, is preferably a plurality of crossbar switches. <IMAGE>

Description

DIGITAL VIDEO PROCESSING APPARATUS This invention relates to digital video processing apparatus, and especially to digital video processing apparatus for spatially manipulating two-dimensional figures.

In an article entitled nA Non-Aliasing Real-Time Spatial Transform Technique" by Karl M. Fant, published in IEEE Computer Graphics and Applications, January 1986, the author describes a two pass spatial transform technique for spatial transforming of discrete sampled images using a continuous resampling interpolation algorithm. All the pixels of the input image under the map of the output image fully contribute to the output image. A first pass maps all the input pixels into their correct vertical orientation in relation to the final output image, and creates an intermediate image. A second pass maps all the pixels from the intermediate image into their correct horizontal orientation to create the final output image. The technique thus combines two operations of a one-dimensional resampling interpolation technique.

It is an object of the present invention to provide digital video processing apparatus for carrying out a spatial transform technique with economical use of processing hardware.

According to one aspect of the invention there is provided digital video processing apparatus comprising a plurality of field stores having respective input/output video ports, at least one pixel string resampling means, a video signal input port, a video signal output port, selectively switchable video signal routing means, and control means, the routing means being connected to provide selected routes between the video signal input port and the respective input/output video ports of selected ones of the field stores, between the respective input/output video ports of selected ones of the field stores and the video signal output port, and between the respective input/output video ports of selected ones of the field stores and the at least one pixel string resampling means, the control means being coupled to the routing means to determine selection of the said routes, and being coupled to the field stores and the at least one pixel string resampling means to control transformation of video data held in selected ones of the field stores by operation of the at least one pixel string resampling means on routing of said data by the routing means to the at least one pixel resampling means and from the at least one pixel resampling means to further selected ones of the field stores.

According to another aspect of the invention there is provided digital video processing apparatus comprising a plurality of field stores having respective input!output video ports, a video signal input port, a video signal output port, means for effecting distortion in at least one dimension in a video field, selectively switchable video signal routing means, and control means, the routing means being connected to provide selected routes between the video signal input port and the respective input/output ports of selected ones of the field stores, between the respective input/output video ports of selected ones of the field stores and the video signal output port, and between the respective input/output video ports of selected ones of the field stores and the distortion means, the control means being coupled to the routing means to determine selection of the said routes, and being coupled to the field stores and the distortion means to control distortion of video data held in selected ones of the field stores by operation of the distortion means on routing of said data by the routing means to the distortion means and from the distortion means to further selected ones of the field stores.

In a first embodiment for half real-time processing, a digital video luma or chroma signal supplied to a video signal input port is routed by a switching arrangement to selected ones of a set of field stores. The video data is read from selected field stores to a pixel string resampler that can increase or decrease the number of pixels corresponding to a selected segment of the input pixels. The output pixels, which have recalculated values, are written into others of the field stores. In a first pass through the resampler, video field data is processed vertically, and in a second pass through the resampler, the vertically processed field data is processed horizontally, so that two dimensional distortion of selected areas of the video field can be effected. A host computer exercises overall control. The fully processed fields are read out through a video signal output port.Alternate frames of the input video signal are thus processed, so that the processing is half real-time processing.

In a second embodiment, full real-time processing is effected.

This embodiment has a larger number of field stores, and two pixel string resamplers. One of the resamplers carries out only vertical processing, and the other only horizontal processing. By appropriate use of the switching arrangement of this embodiment, every frame of an input digital video signal can be fully processed, horizontal processing of one field being carried out at the same time as vertical processing of an adjacent field, so that the output rate of production of fully processed new fields matches the input rate of original fields.

The invention will now be described by way of example with reference to the accompanying drawings, in which: Figure 1 is a graphical illustration of an input pixel string and an output pixel string; Figure 2 is a graphical illustration of a one dimensional transformation; Figure 3 is a graphical illustration of successive stages of a two dimensional transformation; Figure 4 is a block diagram of a first digital video processing apparatus embodying the invention; Figures 5 to 8 are block diagrams illustrating operation of the apparatus of Figure 4; Figures 9 and 10 are graphical illustrations of interpolation of pixel values; Figures 11 to 15 are graphical illustrations of algorithms for interpolation of pixel values; Figure 16 is a block diagram of part of the apparatus of Figure 4;; Figure 17 is a block diagram of a part of the apparatus of Figure 4 incorporating the part illustrated by Figure 16; Figure 18 is a graphical illustration of a perspective effect obtained by two dimensional transformation of a plane image; Figure 19 is a schematic diagram of a crossbar switch usable as a component of the apparatus of Figure 4; Figure 20 is a block diagram of a second digital video processing apparatus embodying the invention; and Figures 21 and 22 are block diagrams illustrating operation of the apparatus of Figure 20.

An arbitrary segment of linearly arranged input pixels is mapped onto an arbitrary segment of linearly arranged output pixels, by specifiying start position, finish position, processing direction, size change and run-length (number of pixels to process).

Since the input and output pixels are the same size, the ratio of number of pixels output to number of input pixels determines whether an apparent expansion or compression takes place. In Figure 1, expansion and compression are respectively shown for segments 1A and 3A of a line of input pixels. The segment 1A is expanded to be output as segment 1B. Segment 3A is compressed to form output segment 3B, and segment 2A is output as segment 2B with an unchanged number of pixels.

The input pixels, which can be luma pixels or chroma pixels, have, accordingly, respective luma or chroma values. Values for the output pixels must be calculated. Where there is no change in the number of pixels in a segment, and no shifting of position, each output pixel corresponds to one input pixel and therefore has the same value as that input pixel. However, where an input segment of pixels is compressed or expanded, new values are calculated for the output pixels. The new pixel values are interpolated from the original values of the input pixels, which are treated as point values at regular positions along a linear axis, the corresponding segment of output pixels being considered to be projected to points along the same linear axis. Consequently fractional contributions from the input pixel values are added to give the output pixel values.

Fractions are generated in the hardware (see below) and are multiplied by the luma or chroma values of input pixels, and the results are added to generate the luma or chroma values of new output pixels.

Each column or row of input pixels can be subdivided into regions that can be transformed differently. Furthermore, adjacent parts of the columns or rows can be defined to lie in the same transformation region. Thus 2-dimensional transformation regions can be specified as shown in Figure 2, where the transformation of one source region 10 to a destination region 10A in one direction is shown. It is possible to automatically vary the start position, destination position, runlength and size change from one column or row to the next. Thus it is possible to define trapezoidal shaped transformation regions, which are necessary to fully subdivide polygonal input areas of the input image, including, where necessary, degeneration to triangles or to lines one row or column wide.

The transformation of three regions of an original input image 42 is illustrated in Figure 3. Selected regions 4, 5, 6 are first respectively transformed in a vertical direction, shown as regions 4A, 5A, 6A. The resulting intermediate image 44, 46 is then redivided into a new set of transformation regions 7, 8, 9, and transformed horizontally 7A, 8A, 9A to provide a processed image 48.

Figure 4 is a functional block diagram of a first embodiment of the invention. Six general purpose fields 11 to 16 have respective input/output video ports that are connectable through a switching arrangement 17 to an input port 18, and output port 19, and a pixel string resampler 20. A host computer 21 supplies control and timing signals to the field stores 11 to 16, the switching arrangement 17, and the pixel string resampler 20, and supplies control data to a control memory unit 22 of the resampler 20. This embodiment will be described as operating on eight bit luma signals. It will be apparent that by multiplying the number of component functional blocks, an embodiment capable of operating on twenty-four bit video signals comprising eight luma bits, eight chroma B bits and eight chroma R bits can be implemented.

A video frame is composed of two fields, and therefore the embodiment of Figure 4 carries out, in a cyclical manner, the following four processes: 1) Odd field vertical pass; 2) Odd field horizontal pass; 3) Even field vertical pass; and 4) Even field horizontal pass.

An input digital video (luma) signal is supplied to the input port 18, but only every second frame is utilized by the apparatus of Figure 4. Field store 11 receives the odd field, and field store 12 receives the even field.

Figure 5 illustrates the odd field vertical pass. In Figure 5, the odd field in field store 11 is read column by column through the switching arrangement 17 to an input line store 23 of the resampler 20. One or more segments of the column held currently in the input line store 23 are selected in sequence by a segment selector 24 of the resampler and shifted or expanded or compressed or left unchanged by the operation of the control memory 22 and a multiply/accumulate unit 25 of the resampler 20, and read into an output line store 26. The contents of the output line store 26 are written as columns into the field store 13 for intermediate storage.

During this processing, a fully processed odd field stored in the field store 14 is being read out to the output port 19 through the switching arrangement 17.

Figure 6 illustrates the odd field horizontal pass. In Figure 6, the vertically processed odd field stored in field store 13 is read row by row through the switching arrangement 17 to the input line store 23. One or more segments of the row held currently in the input line store 23 are selected in sequence by the segment selector 24 and shifted or expanded or compressed or left unchanged by the operation of the control memory 22 and the multiply!accummulate unit 25, and read into the output line store 26. The contents of the output line store 26 are written as rows into the field store 14. During this processing, a fully processed even field stored in the field store 15 is being read out to the output port 19 through the switching arrangement 17.

Figure 7 illustrates the even field vertical pass. In Figure 7, the even field in field store 12 is read column by column through the switching arrangement 17 to the input line store 23. The pixel string resampler 20 operates again to produce output columns ore 11 from the input port 18 through the switching arrangement 17.

Figure 8 illustrates the even field horizontal pass. In Figure 8, the vertical processed even field stored in field store 13 is read row by row through the switching arrangement 17 to the input line store 23. The pixel string resampler 20 operates again to produce output rows in the output line store 26, as in the odd field horizontal pass but with parameters selected for this horizontal processing in accordance with the desired end ore 11 from the input port 18 through the switching arrangement 17. Also, a fully processed odd field stored in field store 14 is read out to the output port 19 through the switching arrangement 17.

Figure 8 illustrates the even field horizontal pass. In Figure 8, the vertical processed even field stored in field store 13 is read row by row through the switching arrangement 17 to the input line store 23. The pixel string resampler 20 operates again to produce output rows in the output line store 26, as in the odd field horizontal pass but with parameters selected for this horizontal processing in accordance with the desired end result. The contents of the output line store 26 are written as rows into field store 15 through the switching arrangement 17. During this processing, the fully processed even field held in field store 16 is read out to the output port 19 through the switching arrangement 17, and an input even field is written into field store 12 from the input port 18 through the switching arrangement.

From figures 5 to 8 it will be seen that a fully processed odd field is read out twice from field store 14, and the accompanying fully processed even field is read out once from field store 15, then a second time from field store 16, the individual readings of the odd and even fields being alternate.

Thus the embodiment of Figure 4 operates in half real time.

The basis and details of the operation of the pixel string resampler 20 will now be discussed.

Figure 9 is a representation of a line of input pixels with pixel values PO to P4 shown by the lengths of arrows. A sequence of translated (shifted) output pixel values PO', P1', etc. are generated by adding weight proportions of pairs of adjacent pixels.

Thus, F01 = (FA x PO) + (FB x P1) P1' = (FA x P1) + (FB x P2) P2' = (FA x P2) + (FB x P3) etc, where FA + FB = 1.

The weighting coefficients, FA and FB, are fractions and if the same values of FA and FB are used for each new pixel, then when the new pixels are displayed there will be an apparent fractional displacement, relative to the original pixels. The extent of the apparent displacement depends on the values of FA and FB.

Translation is treated in the hardware as an expansion with a 1:1 expansion ratio.

An expansion is shown in Figure 10. A larger number of new pixel values Pro', P1', F2', etc, is generated from an original sequence PO, Pl, P2, etc, by combining pairs of adjacent original pixel values. However, the fractional coefficients FA and FB are different for each new generated pixel. Furthermore, the same pair of original pixels can be used more than once, so more new pixel values can be generated from fewer original pixels, although the information contained is of course essentially the same. Hence an apparent expansion has taken place.

Figure 11 is an alternative representation of the expansion algorithm, which shows it as a 1 pixel wide "window" 101, that moves along and samples the input pixels such as PO, P1, P2 for example.

At each new position of the input window a new output pixel is generated from two input pixels. Thus, = =(FA0*P0) + (FB0*P1), P1' = (FA1*P0) + (FBl*Pl), P2' = (FA2*Pl) + (FB2*P2).

The proportions of the input pixels depend on the position of the window, and the displacement Z of the window at each sample governs the rate at which input pixels are processed, so that the apparent size change depends on Z. The quantity Z is a fraction, and the expansion ratio is 1/Z.

The expansion algorithm can use a one input pixel wide averaging window to smooth transitions between input pixels, as shown in the example of Figure 12. A half input pixel averaging window may be used as shown in the example of Figure 13. In these figures, IP1 denotes the input signal for pixel 1, for example.

A group of adjacent pixel values can be multiplied by coefficients and summed, to produce a resultant output pixel. In the example shown in Figure 14, input pixel value PO and P3 have smaller weighting than P1 and P2, and it can be said that the output pixel PO' is made up of two "partial" pixels (P0 and P3) and two "whole" pixels (P1 and P2). This means that a non-integer number of pixels has gone into producing a single output pixel, so effectively causing compression, with a "compression ratio" that is non-integral. If an input pixel is only partially "consumed" for a given output pixel, then the "remainder" of the pixel can be used for the next output pixel, so that all pixels contribute equally to the output.In Figure 14, PO to P6 are input pixels, PO' and P1' are output pixels and the compression ratio is l/z : 1. Thus, PD' = (FB0*P0) + (Z*P1) + (Z*P2) + (FB3*P3), where FB0 + z + Z + FAD: 1, FA0 +FBl : similarly P1' = (FA4*F3) + (Z*P4) + (Z*P5) + (FB6*P6), and so on.

The compression algorithm combines values from input pixels to make up complete output pixels as shown in Figure 15, where IP1 denotes the signal for input pixel 1 for example.

Although the expansion and compression algorithms operate differently, they produce the same results in the 1:1 case. The mechanism is implemented with a continuous scale of expansion/compression. Transitions between the two algorithms are smooth and do not require special programming.

Hardware for one digital video (luma or chroma) path is shown in Figure 16, consisting of the multiply/accumulate unit 25 and a fraction generator 80 which is part of the control memory 22. Two consecutive pixel input values from the input line store 23 are input to the unit 25, namely a current value B and a previous value A. These two values are held by respective series connected latches 86, 88. A common clock is connected to elements of the hardware, so that each element performs one task in each clock cycle. Each latch has a clock-enable, and stores the pixel value present at its input during the clock cycle, when the clock-enable is on.

The fraction generator 80 produces a pair of numbers for each cycle of its operation called FA and FB. The FA and FB values are 12 bits in length, i.e. they range from 0 to 2048 which is 2 to the power of 11. They are regarded as fractions, since there is in the hardware an implicit divide by 2048 at a later stage. Hence an FB value of 2048 is equivalent to 100%, while an FB value of 1024 is 50% and so on. FB is the coefficient of the most recently read input pixel value, while FA is the coefficient of the previous pixel value.

These two numbers are fed to the video path in parallel, such that FB and current signal input value B are fed to a first Multiplier/Accumulator 84 and FA and previous input signal value A are fed to a second Multiplier/Accumulator 82.

The fraction generator 80 is a synchronous i.e. clocked arithmetic unit in which for each clock cycle a new FA and FB pair is generated.

For each cycle, video signals related to B*FB and A*FA are respectively accumulated. These signals are added in an adder 90 until an output pixel is provided to a video output by way of a hard-wired binary division unit 92. Both the Expand and the Compress algorithms allow the final result to be scaled by the binary division unit 92.

The operation of the hardware shown in Figure 16 in expansion mode is as follows: For any expansion, no more than two input pixels can contribute to any output pixel. At the start of the generating of an output pixel, the first contributing input pixel (A) is latched into the latch 88, while the next input pixel (B) is latched into latch 86. The fraction generator 80 provides the fractions FA, FB appropriate to the contribution from each input pixel to the output pixel. These fractions are multiplied by the appropriate input pixel values and output to the following stage as the output pixel value. The value of the second input pixel (B) replaces the first pixel value in the latch 88, while a third input pixel is latched into latch 86 to replace the value B. The fractions supplied by the fraction generator 80 are changed to suit the new pixels.These fractions are multiplied by the input pixel values, and the result is output. This continues, outputting one pixel per clock cycle, until the final input pixel which contributes to this output pixel has been processed.

The operation of the hardware shown in Figure 16 in compression mode is as follows: at the start of processing of an output pixel, the fraction generator 80 calculates the fraction of the first input pixel that contributes to the output pixel. In the example of Figure 15 this fraction is i. This fraction is multiplied by the input pixel value (IPl in Figure 15) and the result put in the accumulator stage of the multiplier/accumulator 82.

Then the next input pixel is processed, being multiplied by its fraction, and the result is added to first result held in the accumulator stage. This procedure continues until the final input pixel (in Figure 15, input pixel 3) which contributes to the current output has been processed. The values in the two accumulator stages are then added together by the adder 90 to provide the value for the current output pixel. This output is passed out. Then the next sequence of input pixels is processed, starting with the last processed pixel (if it contributes to two output pixels).

Figure 17 illustrates the arrangement of the components of the resampler 20 so as to show signal paths more clearly.

A 2-dimensional image can be made to appear to be at any distance and orientation in 3D-space with respect to the viewer by performing the appropriate subdivision and transformations. The method of simulating perspective by video image subdivision and vertical processing followed by image subdivision and horizontal processing is shown in Figure 18. An original image 62 showing an object 64 is divided into regions 66. The image is transformed vertically to provide an intermediate image 68. The intermediate image 68 is again subdivided into a new set of regions 70.

Horizontal transformation then results in an output image 72 showing the object in simulated perspective 74. The image regions may be trapezoidal, triangular or even a segment of one line. The regions may be contiguous or otherwise.

To summarize, a 2-dimensional image with an arbitrary polygonal outline is subdivided into trapezoid shaped regions, or triangles in the special case, and each of these input regions undergoes a different spatial transformation to map onto an output region which is also trapezoidal (or triangular) to give the variation in size over the output image that would occur in a true perspective view.

The nature of the transformation depends on the required position and orientation of the output region is 3-space relative to the input region. If a sufficient number of regions are used then a good approximation to a perspective view is attained.

The original image transformation is carried out in two passes as described above, once in the vertical direction to give an intermediate output which is subsequently processed in the horizontal direction. The combination of the two passes gives rise to the required arrangement of the output in two dimensions. In the one-dimensional transform, an arbitrary number of linearly arranged input pixels is mapped onto an arbitrary number of linearly arranged output pixels, by a process of interpolation and accumulation of the input pixels to generate new output pixels. Depending on the ratio of an input to output pixels, an apparent expansion or contraction occurs. More than one segment of the line may be involved, with each segment having a different transformation onto the output segment. The segments may or may not be contiguous.

The trapezoids are formed by adjacent groups of the line segments of varying length, where the variation in length follows an arithmetic progression. Hence the parallel sides of the trapezoids are parallel to the direction of processing. The non-parallel sides of the trapezoids correspond to the ends of the segments, and these may be contiguous with the segments of other trapezoids.

The switching arrangement 17 of Figures 4 to 8 is formed by two high speed digital crossbar switches of the type 74AS8840 manufactured by Texas Instruments, Incorporated, Dallas, Texas, United States of America. The 74AS8840 switch can switch from 1 to 16 nibbles, i.e. 4 to 64 bits, in one operation, having 64 input/output pins arranged in 16 switchable nibbles. A single input nibble can be switched through to any one or more of the other 15 nibble outputs. A schematic diagram of the 74AS8840 switch is shown in Figure 19. Further details are given in the product leaflet entitled: 74AS8840 Innovation ... The new digital crossbar switch from Texas Instruments" published in 1988 by Texas Instruments, Incorporated.

Each of the field stores 11 to 16 must be of a type allowing reading and writing both by row and by column, and having an eight bit input/output video port.

The two 74AS8840 switches used as the switching arrangement 17 are arranged to operate in parallel, with corresponding nibble input/outputs of the two switches being paired to serve as 8 bit input/output ports of the arrangement 17.

It will be apparent that more than two 74AS8840 switches may be used to form the arrangement 17 if desired.

Figure 20 is a functional block diagram of a second embodiment of the invention. In this embodiment eight general purpose field store 31 to 38 are connectable to an input port 51, an output port 52, and two pixel string resamplers 53 and 54, under the control of a host computer 55 which supplies control and timing signals to the field stores 31 to 38, to a switching arrangement 56 for selectively interconnecting the stores 31 to 38 with the ports 51 and 52 and the resamplers 53 and 54, and to the resamplers 53 and 54. The host computer 55 also supplies control data to respective control memories 56 and 57 in the resamplers 53 and 54.

Each pixel string resampler 53 or 54 is formed as and operates in the same manner as the pixel string resampler 20 of Figs. 4 to 8.

However, one pixel string resampler 53 is dedicated to vertical processing, and the other pixel string resampler 54 is dedicated to horizontal processing.

The embodiment of Figure 20 will now be described as operating on eight bit video signals. The video signals may be luma signals, or chroma signals. It will be apparent that by multiplying the number of component functional blocks, an embodiment capable of operating on twenty-four bit video signals comprising eight luma bits, eight chroma B bits, and eight chroma R bits can be implemented.

The embodiment of Figure 20 utilizes every frame of a video signal supplied to the input port 51.

Figure 21 illustrates the processing and routing carried out during an odd field time. During this time, an input odd field is written from the input port 51 to field store 31, the previous even field, held in the field store 32, is read column by column into the input line store of the vertical resampler 53 which processes this data to provide shifted or compressed or expanded or unchanged pixel strings in its output line store from which columns are written to field store 34. Also, the previous odd field, already vertically processed by the resampler 53, is read from field store 33 row by row to the input line store of the horizontal resampler 54 which processes this data to provide shifted or compressed or expanded or unchanged pixel strings in its output line store from which rows are written to field store 35. A fully processed previous even field held in field store 36 is written into field store 38, and a fully processed previous odd field held in field store 37 is read out to the output port 51.

Fig. 22 illustrates the processing and routing carried out during the even field following the odd field of Fig. 21. During this even field time, an input even field is written from the input port 51 to field store 32, the previous odd field (that of Fig. 21), which is held in field store 31, is read column by column into the input line store of the vertical resampler 53 which processes this data to provide shifted or compressed or expanded or unchanged pixel strings in its output line store from which columns are written to field store 33. Also, the previous even field, already vertically processed by the resampler 53, is read from field store 34 row by row to the input line store of the horizontal resampler 54 which processes this data to provide shifted or compressed or expanded or unchanged pixel strings in its output line store from which rows are written to field store 36.A fully processed previous odd field held in field store 35 is written into field store 37, and a fully processed previous even field held in field in store 38 is read out to the output port 51.

The switching arrangement 56 can be composed of two, or more, 74AS8840 switches arranged with the two, or other even number, of switches in parallel to provide eight bit input/output ports for the arrangement 56.

In both of the embodiments described, each field store can be composed of a suitable number of Hitachi HM534252 series multiport CMOS video RAMs.

The embodiment of Figures 20 to 22 processes all frames of the input video signal which, in terms of data content, is simply delayed and transformed relative to the input video signal. Thus the embodiment of Figures 20 to 22 carries out real time processing.

In each pixel string resampler 20, 53, or 54, the input line store and the output line store may each be implemented by an eight bit shift register of sufficient length to accommodate a row of pixels (or a column if the vertical extent in pixels of a field is greater than the horizontal extent). Suitably addressed RAM may be used for this purpose. The segment selector is an addressing circuit for use in reading out a selected segment, i.e. pixel string, from a row or column of pixels held in the input line store.

Such addressing circuitry will be of a kind apparent to those skilled in the art. The control memory comprises the fraction generator 80 of Figure 16, together with RAM for storing the control data written by the host computer to the resampler, and logic circuitry for producing control signals to be applied to the segment selector, the input and output line stores, and the multiply/accumulate unit. The fraction generator may include calculating circuitry for generating the fractions to be used in calculating output pixel values. An example of pixel string resampling circuitry is described in co-pending U.K. patent application no. 9107732.1 and United States patent application serial no. , which is hereby incorporated. It will also be apparent that the functions of the control memory and the segment selector may be carried out by a microprocessor or multi-microprocessor-based control unit loaded by the host and operating at sufficient speed. Such control units are of a kind well known to those skilled in the art. A commercially available pixel storing resampler is the Bt710 SCORE module which incorporates a Scaler/Orthoganol Rotator Element and is manufactured by Brooktree Corporation, 9950 Barnes Canyon Road, San Diego, California 92121-2790, United States of America.

Claims (7)

1. Digital video processing apparatus comprising a plurality of field stores having respective input/output video ports, at least one pixel string resampling means, a video signal input port, a video signal output port, selectively switchable video signal routing means, and control means, the routing means being connected to provide selected routes between the video signal input port and the respective input/output video ports of selected ones of the field stores, between the respective input/output video ports of selected ones of the field stores and the video signal output port, and between the respective input/output video ports of selected ones of the field stores and the at least one pixel string resampling means, the control means being coupled to the routing means to determine selection of the said routes, and being coupled to the field stores and the at least one pixel string resampling means to control transformation of video data held in selected ones of the field stores by operation of the at one pixel string resampling means on routing of said data by the routing means to the at least one pixel resampling means and from the at least one pixel resampling means to further selected ones of the field stores.

2. Digital video processing apparatus according to claim 1, wherein there are two pixel resampling means, one of which is arranged to process columns of pixels supplied thereto from selected field stores, and the other of which is arranged to process rows of pixels supplied thereto from selected field stores, whereby real time processing of an input video signal supplied to the video signal input port is effected.

3. Digital video processing apparatus according to claim 1 or 2, wherein each pixel resampling means comprises an input line store for receiving a column or a row of pixels, a segment selector for selecting segments of the content of the input line store for processing, means for generating output pixels from the input pixels in a selected segment, and an output line store for assembling a column or row of output pixels to be routed to a selected one of the field stores.

4. Digital video processing apparatus according to claim 1 or 2 or 3, wherein the routing means comprises a plurality of controllable crossbar switches.

5. Digital video processing apparatus according to any preceding claim, wherein the control means comprises a host computer.

6. Digital video processing apparatus comprising a plurality of field stores having respective input/output video ports, a video signal input port, a video signal output port, means for effecting distortion in at least one dimension in a video field, selectively switchable video signal routing means, and control means, the routing means being connected to provide selected routes between the video signal input port and the respective input/output ports of selected ones of the field stores, between the respective input/output video ports of selected ones of the field stores and the video signal output port, and between the respective input/output video ports of selected ones of the field stores and the distortion means, the control means being coupled to the routing means to determine selection of the said routes, and being coupled to the field stores and the distortion means to control distortion of video data held in selected ones of the field stores by operation of the distortion means on routing of said data by the routing means to the distortion means and from the distortion means to further selected ones of the field stores.

7. Digital video processing apparatus substantially as described hereinbefore with reference to Figures 4 to 8 or Figures 20 to 22 of the accompanying drawings.