JPH0634202B2 - Fractal generation method and generator - Google Patents

Description

Description: FIELD OF THE INVENTION This invention relates to the faster computation of functions of the type called fractals, especially video
Regarding computer generated graphics display.

BACKGROUND OF THE INVENTION Traditional mathematics has relied on complex and irregular forms of idealized models and natural physical processing. These idealized models can be expressed in the form of continuous differentiable functions and do not have the statistical basis needed for their generation. In this way, clouds, mountains, coastlines,
It is extremely difficult to represent a graphic representing a tree or the like. Freeman of San Francisco in 1982
an) published by The Fractal Geometry of na
ture ”in the document Benoit Mandelblot (Be
Noit Mandelbrot) has elaborated on a new kind of function, called a fractal, that represents such irregular, finely separated natural forms.

The fractal function includes both a basic shape specific to the shape and a statistical or random property of the position of the shape in space. For example, clouds are drawn using overlapping circles. A circle is a basic shape that makes the cloud look natural by randomly determining the size and position of the circle.

Fractals have the property of self-similarity, as do the dimensions of space that vary in size over large orders of magnitude.
As an example, consider the rugged, jagged coastline. The coastline looks similar when viewed from a jet airplane at a distance of 10 km, when viewed from a low altitude airplane of 100 m, or from a standing position of 1 m. Mountains are another example of self-similar shapes. Viewed closer to the mountains, the minor peaks and hills are generally similar. At smaller dimensions, the rock formations and fissures that make up the mountain have structures that suggest the structure of the entire mountain. When considering clouds, coastlines, or mountains, the basic form, or "generator"
It can be recognized that can be represented on many spatial dimensions, from huge to small.

Self-similar structures can have the randomness of mountains and clouds,
Or they specify geometrically in a more regular way,
Can be configured. A self-similar structure with an infinite number of spatial dimensions begins with the desired structure or "initiator" and is constructed by intentionally including the "structure" with a second structure, or successively smaller spectral dimensions. can do. The fractal obtained is called a "teragon". Mandelbrot, cited above, gives numerous examples of both regular and random terragon.

A typical topological dimension D _T in an intuitive Euclidean criterion, the point D _T = 0, the lines D _T = 1, the surface is D _T = 2,
The solid has D _T = 3. The concept of dimension is generalized by Mandelbrot to Hausdorff or Fractal dimension D, which is suitable for measuring complex and sometimes infinitely long fractal structures from the _DT of the usual topological dimension. .
The similarity dimension is also related to the fractal dimension. To rephrase Mandelblot's example of this concept of dimension in more detail, consider again the rough rugged coastline. In order to measure the length of the coast between two points from a detailed map, a linear measuring rod with a length of ε = 10 km is used to measure the size on the map and a distance L = Nε is measured. However, using such shoreline measurements overlooks some jaggedness and results in L measurements that are too short. ε = 1k
When measured again on a map scale with a m length bar, the overall length L increases. When the length of the measuring rod becomes shorter, the coastline uses a surveying instrument, then the actual measuring rod,
Furthermore, it can be directly measured using a microscope. ε
→ According to 0, each fine terrain can be measured, and the total length of the coast approaches infinity. A problem arises because L is measured in units of one dimension (original), that is, L (ε) = Nε ¹ . If instead L is measured in units of ε ^D (where D is fractal (Hausdorff)
In dimensions, there are 1 <D <2 numbers D), and the measured length L = Nε ^D becomes independent of the value of ε. The fractal shoreline consists of a series of connected straight lines that can be clearly measured by one dimension measuring rod, and space filling where normal two dimension area measurements are appropriate.
Somewhere between the original structure. The fractal dimension (former) lies between 1 and 2. The fractal has a structure in which Hausdorf dimension D exceeds its topological dimension D _T. The larger D is
Compared to D _T , a given fractal with greater convolution, space filling, or irregular fractals.

The modern computer graphics community expects fractal geometry as a way to synthesize naturally appearing shapes or compositions. Fractal generation according to the prior art involves a large amount of calculation and generally requires several minutes or tens of minutes, or even several hours of calculation time per image. In most simulations, the rules for generating the base form are identified and random walk-like statistical processing is initiated. Many steps are performed and the fractal image is the final product. For an overview of prior art that uses fractals for image synthesis, see "IE E Transactions on Pattern and Machine Intelligence (IEEE Transactio
ns on Pattern and Machine Intelligence) "
MI-6, No. 6, November 1984, pp. 661-674, by Alex Pentland, "Fractal-Bas".
ed Description of Natural Scenes ”.
In addition, Vol.25, No.6,19 of "Communications of the ACM"
June 1982 Mr. A. Fournier, Fussel (D.
Fussell) and L. Carpenter's paper "Computer Rendering of Stochastic Models" also give an overview of conventional techniques. It is desirable to use a method that requires a short calculation time to generate fractals. It would be desirable to have a method that can be implemented in digital hardware to generate fractals in real time at normal television scan rates.

The present invention provides a new and more effective method for generating fractals, which is of the nature of the terragon (a complex geometry of one or more dimensions). . This method is based on the insight of the present inventor that the fractal self-similarity is related to the self-similarity present in the inverse pyramid transformation.

Pyramid and inverse pyramid transformations are described, for example, in Renss, Troy, New York 12181, USA.
elaer Polytechnic Institute's “Image Processing la
boratory, Electrical and Systems Engineering Depart
ment ”issued by Bert (PJBur in IPL-TR-038
t) The Pyramid as a Structure for Efficien
t Computation ”. The inverse pyramid transformation is described in“ ACM Transactions on Graphics ”, Vol.
2, No. 4, October 1983, pp. 217-236, Bart (P.
J. Burt and EHAdelson's paper “A Multireso-lution Spline with Application to Im
More detailed in age Mosaics ”.

Bert's Pyramid Transform is a spectral analysis algorithm that decomposes a signal into spatial frequency bandpass components each having a width of about one octave in one or more dimensions and the remaining lowpass components. . The bandpass components have successively lower center frequencies and successively lower density samplings in each dimension, each halving from one bandpass component to the next lower component. The residual low pass component may be sampled at the same density as the lowest band pass component, or at half the density in each dimension. A process operating on a lower spatial frequency, more coarsely sampled transform result component, will result in a signal reconstructed over a larger area than a process operating on a higher spatial frequency, higher density sampled transform result component. Influence. This is due to the nature of the inverse pyramid transformation.

In the inverse pyramid transform process, the (possibly modified) more coarsely sampled transform result components are expanded by interpolation so that they are sampled at the same density as the most densely sampled transform result. Similarly, the expanded transform result components sampled at the sampling density are linearly combined by single matrix addition. That is, in the sample space sampled at the highest density, the expanded transform result components are added together at each corresponding sample position they share.

Since the enlarging process and the straight line synthesizing process are combined in association with each other, this process is most effectively executed as described below. The most coarsely sampled transform result component is scaled up with the same sampling density as the penultimate low density sampled transform result component, and then linear with the penultimate lowest sampled transform result component. To obtain a linear combination of the two conversion result components in the sampling cycle of the second lowest density. This 2
The linear combination of the two transformation result components is expanded at the same sampling density as the transformation result component sampled at the third to lowest density, and they are linearly synthesized to form the sampling cycle of the third to lowest density. Then, a linear combination of these three conversion result components is obtained. This continuous stepwise expansion and linear synthesis is continued until the linear synthesis of all the conversion result components is obtained at the highest density sampling period (the sampling period of the conversion result component of the highest octave).

"Proceding Things Of The Eye E
E (PROCEEDINGS OF THE IEEE) ", Vol.61, No.6,197
Rabina (LRRab) on pages 692 to 702, June 3
iner) and RW Schaefer's paper "A Digital Signal Processing Approach to Interpol"
ation ”shows a valid way to do the interpolation of the sample data function. The coarse sampling matrix has an O (null) inserted between the sampled data to generate a higher density sampling matrix, and the spurious harmonic frequencies generated by the O insertion are due to the low pass filter. Removed.

<Outline of the Invention> A method for generating a fractal according to the features of the present invention is
It includes the steps of identifying the first to nth sample data spaces. The first space is regularly sampled in multiple dimensions and each of the other samples is regularly sampled in each of these dimensions, but with a coarser density than the sampling density used in the next lower ordinal space. Sampled at. A dot pattern (hereinafter referred to as a seed image) is provided in each sample data space.
Each dot pattern may be random, semi-random, or regular in nature, and it may be similar or different than the dot patterns provided in other sample spaces. Dot patterns may not be present in some sample spaces. There are also generators, which are simple images such as aircraft geometry or images taken from a video camera. Spatial convolution between each pattern and generator (convolutional integration or convolutional integration)
Is performed to obtain each convolution result.
The generator is rotated between sample spaces (sample spaces) or is slightly different in size, but the same for each sample space. These convolution results in the ordinal sample space higher than the "first" are expanded to the same density as the first sample space by the interpolation process and are combined with the convolution result in the first sample space. Generate fractals. These interpolation and synthesis (combination) processes are most effectively performed by the distributed and related characteristics of the expansion and synthesis processes.

<Description of Embodiments> Hereinafter, the present invention will be described in detail with reference to the drawings.

The fractal generating method according to the present invention can generate a video signal representing a fractal-based graphic image in real time. Although the method has been described in terms of such a graphic image generator, the method is also applicable for use in software for generating an image in a stretched time.

FIG. 1 shows, in block form, an overall apparatus for generating in real time a video signal representing any of various graphic images based on fractals. In each successive television image field,
Seed of dots in each of the consecutive sampled sample data spaces of decreasing density.
The pattern is convolved with the pattern of the generator,
Each produces a larger scale feature. These shapes are then composited using a dilation and compositing process. The convolution is advanced by sliding the seed pattern over the generator pattern. The sliding seed pattern is generated by scanning a random access memory that stores the seed pattern.

Consecutive image fields can be considered to be non-interlaced fields that are numbered consecutively modulo 2. For television equipment designers, field-to-field lines or pixel
It goes without saying that changes to interlaces can also be easily implemented, assuming a field rate of 1/60 second, with 2 ⁸ lines per field and 2 ⁸ pixels per line, for the sake of simplicity. . The designer of the television device can easily adapt it to the television system used in broadcasting or the graphic display video system relevant to the invention.

The set 10 of RAMs 11, 12, 13, 14 stores the seed pattern used for convolution in the even alternating fields of the video image field. RAM1
1 is the bit for video graphic image
It has a map structure (each storage cell in RAM 11 has an address which corresponds one-to-one to the address of a particular pixel in the image). That is, the storage location in RAM 11 is an integer value of orthogonal address coordinates that precisely indicates each storage location for a particular pixel or pixel in the image generated in the form of a video signal for display on a video monitor screen. At the address. RAN11 has 2 ¹⁶ memory locations,
256 lines of the address corresponds to 2 ⁸ lines per field, the address of the 256 columns corresponds to 2 ⁸ pixels per line. RAM11 stores very fine, very high resolution dot seed patterns, each dot is RA
It has corresponding row and column address storage locations in M11. RAM12 has 2 ⁷ row addresses and 2 ⁷
It has a position addressed by column addresses. RAM 12 stores a fine or high resolution dot seed pattern, each dot having a corresponding row and column address location. Each storage location in RAM 12 creates a map of 2x2 different pixels in the video graphic image. RAM13 has 2 ¹² memory locations,
It stores a seed pattern of coarse or low resolution dots. Each storage location in RAM 13 creates a map of 4x4 different pixels. RAM14 has a 2 ¹⁰ storage locations, which is very rough, i.e. further stores a seed pattern of low resolution dot. Each storage location in RAM 14 creates a map of 8x8 different pixel groups.

Group 15 of RAMs 16, 17, 18, 19 stores the seed pattern used for the convolution of the odd alternating fields of the video image field. RAM16,
Group 15, 17, 18, 19 is RAM 11, 12, 13, in the way this creates a map of pixels and groups of pixels in a video image.
Corresponds to 14 groups of 10 each.

Write a dot pattern to RAM10 and RAM15
The procedure used to read the seed pattern from AM groups 10 and 15 is as follows. During each of the alternating odd fields, the seed pattern is RAM group 10
And are read from the RAM group 15. During each even-numbered field in the middle, the seed pattern is
It is read from the RAM group 10 and written in the RAM group 15.

This approach is taken for several reasons. In particular, this approach can accommodate delays in the expansion and combination process as will be explained later. This approach also makes it possible to easily animate the graphic display retrieved from the fractal generator. In addition, this technique allows a new seed
The pattern can be easily input (loading).

In order to carry out this method, the number of fields modulo 2 is supplied to the RAMs 11, 12, 13, 14 as write command signals and to the RAMs 16, 17, 18, 19 as read command signals.
The instruction executes in a logic one state. Logic inverter 20 produces the complement of the number of fields modulo 2. This complement is supplied to the RAMs 11, 12, 13, and 14 as a read command signal and to the RAMs 16, 17, 18, and 19 as a write command signal. The memory address multiplexer 21 selects the read address signal to the RAM group 10 or 15 to be read in response to the number of fields modulo 2, or its complement as shown, or both. RAM group to be written 10
Or select the write address signal to 15.

The write address generator 22 generates the basic write addresses supplied to the read address generator 23, which modifies them to generate the read address signal. These address generators 22 and 23 are second
It includes a circuit as shown. The master clock oscillator 24 generates pulses at the pixel scan rate used as the first sample space clock signal. This signal is provided as an input to a cascade of circuits 25, each of which divides the pulse by two to sequentially double the second sample space.
Clock signal, second sample space clock signal, doubled third sample space clock signal, third sample space clock signal, doubled fourth sample space clock signal, fourth sample space -Generate a clock signal. The generation of these clock signals is itself incidental to the generation of the basic write address and read signals.

These address signals are generated by circuit 26. Master·
The pulses from the clock oscillator 24 are counted by a 16-stage binary counter 27 which precedes the 1-stage binary counter 28. All stages of counters 27 and 28 are reset to 0 on conversion between odd and even fields, synchronizing the fractal generator with the display and other display generators. The 16 position binary number generated by the counter 27 is the raster scan basic write address signal at the first sample position, with the RAMs 11 and 1 selected for reading.
It is supplied to one of 6 as a read address signal. The eight higher order bit output signals of counter 27 are the number of scan lines used as row addresses, and the eight lower order bit output signals of counter 27 are the number of pixels along the scan lines used as addresses. is there. The output of counter 28 produces the number of fields modulo 2 shown earlier in this specification.

Of course, an integral power of 2 lines per field and 2 per line
Of the output signal of the counter 27 to be used directly as a row and column address for scanning in raster one storage location of the RAM 11 and 16 selected for reading by selecting an integer power of pixels of Higher and lower order bits can be used. If other line numbering and pixel numbering techniques are used, a more complex arrangement for dividing the pixel count value is needed to obtain an indication of scan line and pixel position. However, providing a device having such a configuration is merely a design matter for a television device and a circuit design engineer. A simplified raster scan of RAM 12,13,14,17,18,19 can be provided by selecting an integer power of 2 lines per field and pixels per scan line.

The raster scan rate for one of the RAMs 12 and 17 selected for reading is 1/4 of the raster scan rate for one of the RAMs 11 and 16 selected for reading. The row address for one of the RAMs 12 and 17 selected for reading is obtained to some extent by discarding the least significant bit of the eight high order bits of counter 27, and the basic write to the second sample space. Generate the row component of the address signal. The column address for one of the RAMs 12 and 17 is obtained, in part, by discarding the least significant bit of the eight least significant bits of counter 27 to generate the column component of the basic write address signal for the second sample space. Let The generated 14-bit basic write address signal for the second sample space is provided as an input to adder 29 along with the other input connected to add the offset. This offset is
It compensates for the delay difference between the convolution result in the sample space specified by the output signal of counter 27 and the convolution result in the sample space specified by the 14-bit basic write address signal. These adders 29, 30, 31 actually subtract the offset. However, this subtraction is done by an addition that produces an overflow bit and then discards it. Adder
29 14-bit output signal selected RA for read
It is supplied as a read address to one of M12 and M17. The 7 high order bits are used to address a row and the 7 low order bits are used to address a column.

The raster scan rate for one of the RAMs 13 and 18 is 1/4 of the scan rate for one of the RAMs 12 and 17 selected for reading. RAMs 13 and 18 selected for reading
The row address for one of the
Resulting in the basic write address row component for the third sample space, which is obtained by discarding the least significant bit of the high order bits. The column address for one of the RAMs 13 and 18 selected for reading is obtained in part by discarding the two least significant bits of the eight least significant bits of counter 27, Generate a basic write address column component for the sample space of The generated 12-bit basic write address signal for the third sample space is provided as an input to adder 30 along with other inputs connected to add the offset. This offset compensates for the delay difference between the convolution result in the sample space specified by counter 27 and the convolution result in the sample space specified by the 12-bit basic write address signal. 12 of 30 adders
The output signal of the bit is supplied as a read address to one of the RAMs 13 and 18 selected for reading. The 6 high-order bits are used as the row address and the 6 low-order bits are used as the column address.

The raster scan rate for one of the RAMs 14 and 19 selected for reading is 1/4 of the raster scan rate for one of the RAMs 13 and 18 selected for reading. The row address for one of the RAMs 14 and 19 selected for reading is obtained, in part, by discarding the three least significant bits of the eight most significant bits of counter 27, the fourth sample Generate the row component of the basic write address signal for the space. The column address for one of the RAMs 14 and 19 selected for reading is obtained, in part, by discarding the three least significant bits of the eight least significant bits of counter 27, the fourth sample Generate the column component of the basic write address signal for space. The generated 10-bit basic write address signal for the fourth sample space is added by the adder 31 with the other inputs connected to add the offset.
Supplied as an input to. This offset is the counter
Compensate for the delay difference between the convolution result in the sample space specified by the 27 output signals and the convolution result in the sample space specified by the 10-bit basic write address signal. Adder
31 bit output signal is RAM1 selected for read
It is supplied as a read address to one of 4 and 19.
Five high order bits are used as a row address and five low order bits are used as a column address.

Advantageously, RAMs 11-14, RAMs 16-19 are used to store pixel elements for fields without retrace periods. If the retrace period is not stored in RAMs 11-14 and RAMs 16-19, the motion of the generated fractals in successive fields can be easily obtained. Initially, the image scan pattern was considered to be a series of scan lines with each end returning to each beginning. That is, each scan line is considered as a circle that wraps the surface of the cylinder, and each circle identifies the end of the cross section cut at an angle perpendicular to the main axis of the cylinder. The distance along each circle corresponds to the elapsed time within the scan line expressed in pixel scan units. The distance along the axis of the cylinder corresponds to the elapsed time in the field period expressed in terms of line scan units. The axis of the cylinder is then formed in the circle to transform the cylinder into a torus, whereby a ring of scan lines occurs at each cross section of the torus. According to the principle of this map formation
Due to the organization of each of RAM 11 to 19, it is not necessary to consider the field retrace or line retrace period during the fractal generation processing period, and RAM 11 to 14 and RAM 16 to 19 are continuously scrolled horizontally or vertically. be able to. A retrace period can be inserted after fractals have been generated and processed to form video signal samples. by this,
The problem of having to deal with discontinuities at the ends of the field can be avoided.

Returning to FIG. 1, the write address generator 22 generates a write address signal distributed by the multiplexer 21. These write address signals are generated by the address generator 23.
May be the same as or different from the basic write address signal provided to read As will be described in more detail below, write address generator 22 generally selects among various methods for generating a write address signal. Once the seed pattern is loaded into one of the RAM groups 10 and 15, it is convenient to select the basic write address signal as the write address signal provided to this RAM group by the memory address multiplexer 21. Here it is assumed that this is done.

It is convenient to store frequently used seed patterns in programmable read-only memories (PROMs) such as PROM33, PROM34 and PROM35, so that such patterns can be provided to PROM33, 34, 35. Called in response to the read address signal. PROM is a bit
The map composition seed pattern may be stored. This is preferred if the dot pattern is sufficiently dense.
The PROM may store a pattern of dots in run-length-code format, which is preferred for sparse dot patterns. The PROM may be of addressable content and stores the seed pattern as a list of read address signals.

It is desirable to store a very high resolution seed pattern as half of each word in the PROM and provide the basic write address signal from generator 27 as the read address signal. The other half of each PROM word spatially multiplexes the lower resolution seed pattern. The RAM write controller 40 applies the seed pattern in the halfword read from the PROM according to the basic write address signal selected by the bit selector 38 to the RAM in the group 10 or 15
Classify for distribution to.

The seed pattern used in RAMs 10 or 15 is also provided by dot pattern generator 36 or random dot pattern generator 37.

The seed pattern used to generate the fractal is selected by selecting one of the PROMs 33-37 according to the seed pattern read command signal provided to the PROMs 33-37.

In response to receiving the seed pattern write command, the RAM write controller 40 sends (a) the RAM 11 and the selected seed pattern specified by the sample space matrix sampled at four sequentially smaller densities. Input / output bus 41 shared by 16; (b) Input / output bus 42 shared by RAM 12 and 17; (c) Input / output bus 43 shared by RAM 13 and 18; and (d) Shared by RAM 14 and 19 Supply to input / output bus 44 respectively.

As described above, the conversion from one fractal-based image to the next fractal-based image passes through an intervening black field in the fractal generator of FIG. The input / output bus switching device may simply be configured to convert between fields without an intermediate black field if desired. The shield pattern is written to the selected RAM group 10 or 15 during that field for writing.

When RAM is loaded and the next field begins,
The generator pattern is selected for convolution with the seed pattern in each of the sample spaces sampled at low density and in succession. This generator pattern should be maintained during the next field and RAM groups 10 and 1 selected for reading in this next field.
One of the five is in its scanned storage location. RAM 11 or 16, 12 or 17, 13 or 18, selected for reading
Each of 14 or 19 is a respective convolver 45, 46, 47, 48
Supply one of the inputs to. The other input to the convolvers 45-48 is the generator pattern.

It is convenient to store the generator patterns in parallel in the access memory 49, and in response to the supply of both the generator pattern selection address signal and the read generator pattern command signal, all the generator patterns are paralleled from the memory. Be accessed. The output of the memory provides the generator pattern throughout the field scan of the selected RAM group 10 or 15 for reading into the convolvers 45-48. The memory 49 functions as a "window scanned", for example, a US patent issued by LA Christopher et al. 4th, 4th
Stacked PR using the technique shown in 60,958
It can be configured as an OM (banked PROM). RAM11
14 to 14, RAM 16 to 14, line PROM 49 can be window scanned, the convolver 45 to 48 is a back buffer between the RAM group 10 or 15 selected for reading and the convolver 45 to 48. Configured without the need to provide memory. Consider how each of these convolvers is configured, assuming that the window scan memory feeds the convolvers 45-48.

Each convolution consists of a generator pattern memory 49 and RAM 11-14 or 16-19 selected for reading.
Suppose we are between a 3x3 sample matrix from one of Assume that the spatial matrix from the generator pattern memory is of the form Space sample matrices from the selected RAM for A B C D E F G H I read is assumed to be a form:. a b c d e f g h i These matrices a, b, c, d, e, f, g,
Assume that h, i, A, B, C, D, E, F, G, H, I are steady state or quasi steady state variables. Steady-state variables do not change from field to field. Pseudo steady state variables change only between fields. The run product of these matrices is the convolution result. The convolution between a 3x3 sample matrix is shown for the simplicity of the drawing. Convolution between 5 × 5, 7 × 7 or more sample matrices may be used in a fractal generator embodying the present invention.

FIG. 3 shows that the generator pattern retrieved from the memory 49 is n.
Shows how each convolver 45-48 is configured if it has a gray scale of bits and the dot pattern retrieved from the RAM group 10 or 15 selected for reading is actually 1 bit. ing. The addition tree 50 is supplied with the nine-component product of the matrix multiplication included in the convolution process. The latch 51 having three parallel states multiplies the n-bit variable A and the 1-bit variable a to generate the first component product of the matrix product. The latches 52 to 59 each having three states are intermediate position products A · a , B · b , C ·.
c , D · d , E · e , F · f , G · g , H · h , I ·
A component dot is generated at i .

The convolver of FIG. 3 has 1-bit string RAMs 11 to 14,
It is attractive in that it does not require a high-speed digital multiplier capable of matching 16 to 19 and multiplying multiple bit numbers by multiple bit numbers. However, the number of bits during matrix multiplication is limited to n + p. Where p is the number of component products during matrix multiplication
log ₂ . The interpolation process used after the convolvers 45-48 adds more bits to the generated fractal.
The large number of bits in the fractal gives the function a higher resolution and increases the likelihood of multiplication that gives the function a threshold.
As discussed in more detail herein, multiplication thresholding is an important technique for converting fractals into usable representations.

FIG. 4 shows that the design document of the fractal generator embodying the present invention uses a high-speed digital multiplier, PROM31 to 33, RAM1.
Each of the convolvers 45 to 48 which can be used when the sacrifice caused by forming the RAMs 1 to 14 and the RAMs 16 to 19 into an m-bit string (where m is a plurality of integers) is not intended is shown. An addition tree 60 is used in place of the addition tree 50 of FIG. 3 so that it can accept (m + n) bits of input, and m instead of the latches 51-59 of FIG.
Bit by n bit digital multipliers 61-69 are used. In this fractal generator, each term a 1 , b 2 , c 3 ,
Each of d , e , f , g , h , and i has m bits.

It is also possible to design a simplified fractal generator by making both the seed pattern and the generator pattern into a one bit string only. This case can be done using AND gates to generate each component product. The products from the AND gates are successively added to produce a correlation result. The following interpolation process is the source of amplitude resolution in the generated fractal. One way to obtain fractals with increased resolution is to use the same generator and seed patterns, each spatially arranged relative to each other, even though the fractal generation process is primarily low resolution in nature. And multiplying independently generated multiple lower resolution fractals together.

A way to reduce the hardware associated with the convolvers 45-48, especially when considering digital multiplication of m-bit by n-bit numbers, is the time division mactiplex using a digital multiplier. Clock through
Since the gh) rate is reduced by a factor of 4 in each sample space, this increases the speed of multiplication by just under 50%.
Of course, some data rate buffers are needed before and after the digital multipliers which do their time division multiplexing.

Another possible way to reduce the hardware associated with the convolvers 45-48 is to take advantage of the property of self-similarity in fractals. The initial portion of the convolution of the first very high sampling density sample space is re-timed to the lower clock rate of the sample space sampled at the higher order number of lower density. This retiming, for example, uses serial input / parallel output shift registers to accept convolution results at high speed, and also accepts convolution results in parallel and outputs them serially at a reduced clock rate. Implemented using a parallel input / serial output shift register.

In this regard, considering the operation of the apparatus of FIG. 1, the seed pattern of each of the denser sample spaces sampled sequentially is convolved with the generator pattern. The convolution results from the convolvers 48, 47, 46 are transformed into a sampling matrix of the same sampling density as the sample matrix supplied by the convolver 45 with the convolution results, thereby combining all the convolution results. The combined convolution result is superimposed on the dc pedestal. The dc pedestal is supplied from the generator pattern PROM49 via the bus 70 as shown in FIG.
The convolution result of the convolver 48 is combined with the combiner 71. The output of the combiner 71 is expanded to the same sampling density as the output signal of the convolver 47 by interpolation in the expander 72, and the output is combined with the combiner 73. The output signal of the combiner 73 is expanded to the same sampling density as the output signal of the convolver 46 by interpolation in the expander 74, and the output signal and the combiner 75
Is synthesized in. The output signal of the combiner 75 is expanded to the same sampling density as the output signal of the convolver 45 by interpolation in the expander 76, and is combined with the output signal in the combiner 77.

The output of combiner 77 is the generated fractal. This fractal and possibly other fractals simultaneously generated by another fractal generator are fed to a fractal processor 78 for conversion into a video signal representing a graphic image to be displayed on a video monitor. . Although some of the fractal processing employed in this invention is further described in this specification, it will now be described in more detail how the expansion and composition processing is performed.

FIG. 5 shows one form of obtaining the expanders 72, 74 or 76. The basic idea of how to expand the original signal sampled at the original sampling density by two-dimensional linear interpolation to generate a signal of twice the sampled density at each dimension is described below. First, the original signal is expanded in the direction perpendicular to the line scan, ie in the vertical direction. This compresses a row of samples in a sample space sampled at low density into alternating rows with a sample space of twice the sampling density, and interleaves the alternating rows of samples with O or O value samples. By placing and then low pass filtering the result in a direction orthogonal to the line scan by a lateral filtering technique.

The low-pass filter response, which is twice the original sampling density, is then subjected to line-scan direction expansion, i.e. horizontal expansion. This is done by alternating the samples from the low pass filter response with the O value samples to generate a signal at a density four times the original sampling density and then low pass processing to produce the output signal. . The output signal is the same as the original signal except that it is sampled at twice the density in each direction.

FIG. 5 shows the original sample sampled at the pulse rate r / 4 applied to the cascaded delay lines 79 and 80,
Each delay line has a sufficient number of consecutive stages to store the entire scan line sampled at a density associated with a pulse rate of r / 4. 5 taps, 2 phase, finite impulse response,
A low pass lateral spatial filter is used to filter orthogonal to the direction of the line scan. O value line, original non-delayed signal line, other O value line, delayed by one line period (r /
The original signal line (of the sampling density associated with a pulse rate of 4) and yet another O-value line are weighted and summed in one phase of the low pass filter convolution. This is actually done by supplying the original signals appearing at the input and the output of the clock delay line 79 respectively and the original signal delayed by one line period to the weighting and summing circuit 81 as inputs. O-values do not cause filter response, no need for weighting,
Is added. The phase of the response output of the filter supplied from the weighting and addition circuit 81 is input to the serial input / parallel output shift register 82 having a scanning line storage capacity as an input signal clocked at a clock rate of r / 4. Supplied in series. Original non-delayed signal line, O value line, original signal line delayed by one line period, O value line, and 2
The original signal lines, delayed by a line period of the book, are weighted and summed with the other phases of the low pass filter convolution. This is due to the original signal at delay line 79, the original signal delayed by one line period appearing at the connection between cascaded delay lines 79 and 80, and the two signals appearing at the output of delay line 80. This is done by feeding the original signal delayed by the line period to the weighting and summing circuit 83 as an input. The phase of the filter response output supplied from the weighting and addition circuit 83 is supplied as an input signal clocked at a clock rate of r / 4 to a serial input / parallel output shift register 84 having a scanning line storage capacity. To be done.

At the end of each line scan period at the clock rate of r / 4, shift
Registers 82 and 84 are filled with samples. A shift signal is generated to transfer the contents of parallel register 82 to parallel input / serial output shift register 86. The serial output connection of shift register 86 is the serial input connection of shift register 85. Two consecutive lines of response output of the low pass lateral filter in shift registers 85 and 86
Two of the filter response outputs are shifted through registers 86 and 85 at a clock rate of r / 2, and in the time occupied by only one line of the original signal when fed at a clock rate of r / 4. Supply scan lines. The samples serially supplied from the output connection of the shift register 85 at a clock rate of r / 2 are the original signals that have been doubled in density to sample in the direction perpendicular to the line scan direction.

As a first step in the extension process in the direction of line scanning, ie in the horizontal direction, this signal is applied to cascaded one pixel delay stages 87 and 88 clocked at a clock rate of r / 2. These stages are 5 taps, filtering in the direction of the line scan,
It is part of a two-phase, finite impulse response low pass lateral space filter. O value signal, vertically expanded non-delayed signal, other O value signal, vertically expanded signal delayed by 1 pixel period at a clock rate of r / 2, and other O value signal Are weighted and added with one phase of filtering. This is a vertically expanded non-delayed signal and 1
This is done by applying a vertically expanded signal delayed by a pixel period to a weighting and summing circuit. A vertically delayed non-delayed signal, an O-valued signal,
The vertically expanded signal delayed by 1 pixel period, the O value signal, and the vertically expanded signal delayed by 2 pixel periods are weighted by the filtering of the other phases and added. This is done by feeding the vertically expanded undelayed signal and the output signals of clock delay stages 87 and 88 to weighting and summing circuit 90. A match-plexer 91 clocked at a clock rate of r resamples the parallel stream output signals of the weighting and summing circuits 89 and 90 into an alternating sequential format to produce a horizontally and vertically expanded signal at a pulse rate of r. Occur.

In the expander 72, r / 4, r / 2, and r are 4 from the pulse frequency dividers cascaded in FIG. 2, respectively.
Second sample interval clock, doubled fourth sample space clock, third sample space clock
Corresponds to each clock signal. In the expander 74, r / 4, r / 2, and r are the third sample interval clock from the cascaded pulse frequency divider 25, the third sample space clock doubled, and the second, respectively. Corresponding to the sample space clock signal of. In the Xpanda 76, r / 4, r / 2, and r are the second sample space clock, which is twice the second sample space clock, and the first sample space clock, respectively.
Corresponds to the space clock signal.

It is possible to use different types of expanders 72, 74, 76 than those shown in FIG.
One of them is a random number written at a relatively low rate for weighting and addition and read multiple times at a relatively high rate.
You are using access memory.

The signal synthesizers 71, 73, 75, 77 are worth further consideration. In the inverse pyramid transform image synthesis procedure, an adder capable of handling at least one input signal of either polarity is used as the linear synthesizer. First
Such adders can be used as combiners 71 to 77 in the fractal generator shown. Also a synthesizer
Subtractors can also be used for 71-77.

The possibility of non-linear combiners 71-77 was considered by the inventor, but not all non-linear combiners can generate valid fractals. Generally speaking, a combiner exhibiting discontinuities in the transfer function for any of the signals being combined is such that these discontinuities are likely to occur during the time that the signal exposed to the discontinuities has an O value. If not set, it is inappropriate. For example, a combiner that raises both input signals to a uniform power and adds the powers is
It is not the kind of synthesizer considered unsuitable for fractal generators. As long as the switch between the two synthesizers is made when the addend / subtract input is an O value, neither synthesizer will randomly add or subtract.

FIG. 6 is a fractal processor shown in the block of FIG.
Details of 78 are shown and the connection between the fractal processor 78 and the color video monitor is shown. Fractal processor 78 is red
Digitally samples (R), green (G), and blue (B) video signal
The analog converters 92, 93 and 94 are supplied respectively. The D-A converters 92-94 include video filters. DA
The R, G, B analog video signals from the converters 92, 93, 94 are supplied as input signals to the video amplifiers 95, 96, 97, respectively, and the response outputs of these video amplifiers 95, 96, 97 are color video tubes. Drives 98 red, green and blue electron guns. It is assumed that gamma correction is performed in either DA converter 92, 93, 94 or video amplifier 95, 96, 97. A deflection (not shown) of the color picture tube 98 is a field scan in one of the RAMs 11 and 16 selected for reading in the fractal generator of FIG. 1 and a memory used to store a map of the video area. Synchronized to 99 field scans.

Memory 99 stores the retrace blanking pattern on a permanent basis. Memory 99 with programmable base
Is a video signal generated by an R, G, B video signal multiplexer 100 from an output signal provided by a fractal generator 101 of the type described in connection with FIG. 1 instead of blanking, other fractal generation. A pattern of areas for selecting either one (eg 103) of the video signals generated by the device 102 or the video signals from the alternating video signal source that can be used to provide the video input signal of the multiplexer 100 is stored. The output of memory 99 is usually in the form of binary codewords. The dictionary of sample code is as follows.

These codes are not only used by multiplexer 99. These codes are PRO104, 1 if any
Used by read selector 110 to select which of 05, 106 should be used to process the fractals generated by fractal generator 101. The code is also used by the read selector 111 which selects which of the PROMs 107, 108, 109, if any, should be used to process the fractals generated by the fractal generator 102.

Next, the relationship between one of the PROMs 104-109 and one of the fractal generators 101 and 102 used with that PROM, eg, the read selector 110 and the multiplexer 100, controls the display on the screen of the video tube 98, R, G. , B signals are generated, the relation of this PROM 104 to the fractal generator 101 is considered when a processing combination of the PRO 204 and the fractal generator 101 is selected. Fractal generator 101 is PROM1
Generate memory address on 04. PROM 104 stores the amplitude of the R, G, B video signal samples for each of its possible addresses. Assume that PROM 104 stores, for all addressable locations, the address of the fractal generator weighted by the relative weights of the R, G, B components in the luminance-only signal at the addressed location. To do. The PROM 104 supplies the R, G and B signals to the video tube 98 and reproduces the fractal in the gamma-corrected gray scale relationship.

Choosing PROM 105 instead of PROM 104 to process the output of fractal generator 101 into R, G, B video introduces another fractal processing algorithm. Another way to modify the fractal processing algorithm is to superimpose the fractal on another function of the image space to generate the input address for the PROM used for fractal processing. For example, a ramp function is added to the fractal to change the size, brightness, or hue of the generated feature fractally across the image field or from top to bottom of the image field.

When generating a cloud pattern from a fractal generated from a circular or elliptical generator pattern in a fractal generator 101, the PROM 104 has a constant for all fractal values below the intermediate range to generate a blue sky background. It is programmed to give the intensity cyan-blue. Fractal values above the mid range are programmed to give a white brightness value that depends directly on the fractal value. This process creates a fractal boundary between the clouds and the background of the blue sky, applying a cloud pattern to what part of the image field and a blue sky background to what part of the image field. Set.

Practically, in this process, when the cloud patterns on the blue sky background are combined to form one image, priority is given to the cloud patterns on the blue sky background. The portion of the foreground image generated by the fractal that is superimposed on the underlying background image in order to maintain the fractal boundary for the overlapping image portion, even if the background image is more complex than a uniform color field. The priority of is also given. Low-level fractals are represented transparently and prevent them from affecting the displayed image. Conversely, foreground graphics with non-fractal contours are given priority over the background generated by fractals.

More complex prioritization in more complex graphics is also possible. For example, two sets of cloud patterns generated by a fractal having a relatively large size and a fractal having a relatively small size can be generated as a foreground cloud and a background cloud, respectively. Foreground clouds are prioritized for display on the graphic image of the aircraft. Foreground clouds and aircraft must be given priority over background clouds. Foreground clouds, aircraft, and background clouds are given display priority over the sky beyond the background clouds. The motion of the clouds and the flight of the aircraft can be animated as if the aircraft were flying through a cloudy sky on a video monitor display screen.

As another example, the superstructure of the boat's graphic image is prioritized both for the fractal-generated seascape and also the fractal-generated expansive sky. The hull of a boat is always lower than the wave front of the sea, but is given conditional priority to the rest of the sea. Image of wavefront with higher priority
Until it arrives during the downward scan of the field, the hull of the boat has higher priority than the lower priority parts of the sea. This creates waves over the hull of the boat. This general technique can also be used with a reverse scan followed by conversion of the scan to achieve other effects.

The seed pattern generation fractal can be configured to be influenced by the non-fractal graphic image so that the thresholded fractal has an edge line at the desired point opposite the non-fractal image. . For example, the bow of a boat can be made to penetrate the waves of the seascape. In a similar fashion, the fractal processing of FIG. 6 can be used to map the signals used in connection with the priority code associated with the input signal of multiplexer 100 without the map generation video area of memory 99 directly controlling , May be modified to provide to determine the selection made by multiplexer 100.

The boundary of the fractal generated by comparing with the fractal threshold can also be used to control the selection between two other video signals, whereby the boundary between the video signals corresponding to the boundary of the fractal is said. At the same time, one of these video signals can be inserted into the other video signal.

Although consideration has been given to the generation of R, G, B signals for delivery to monitor video tube 98, these signals may be encoded for video recording or television transmission. Also,
The fractal processing may be adjusted to directly generate the luminance and chrominance components of the composite video signal for television transmission.

Next, consider the above-mentioned graphic image generator. In audio or video synthesizers, it is important that changes in the obtained results occur rather in accordance with well-determined rules, which make a reasonable expectation that the artist will succeed and that the artist will You can intuitively judge your way toward the result. It is important to be able to reproduce the positives and the results discovered by the artist. Prescriptions or recipes for these favorable outcomes are stored and made into a list for later recall upon request. In the device described above, the PROM49
The generator pattern can be selected for input into. In general, one can choose the density of dots in various seed patterns by the impression of how the dimensions of the reproduction of the lively shape are different. The impression of codification or decodification of shape reproduction translates into more regular or less regular dot structures in the seed pattern. Fractals can be clustered and arranged in selected areas of the screen by focusing the dots in the corresponding areas of the seed pattern. The PROM programming of the fractal processor 78 is controlled by the impression on the dynamic range or degree of compression between the fractal and the displayed video. Control their programming by choosing a color palette. Designers of digital devices for video processing use hardware, firmware, socketware, or a combination of these for their programming tasks, making the impression of artistic control easier and more natural. You can do it.

In this invention, it is necessary to understand the important rules of the seed pattern. By concentrating the dots in the first part of the seed pattern and not placing the dots in the second part of the seed pattern, the strongest is in the part of the image space corresponding to the first part of the seed pattern. Fractals are generated and fractal thresholding creates a fractal boundary between the first portion of the image space in the processed fractal and the remaining image space. When the processed fractals are given display priority, the boundaries of these fractals appear in the final displayed image, creating edges that make them appear natural.

By using a seed pattern, the present invention can predict the artistically pleasing fractal reproduction, despite the random arrangement of features in each dimension. Although there is a great deal of randomness in the seed pattern, the random pattern can be accurately reproduced from one of the PROMs 33-35, if desired, by the operator. By the convolution of this particular pattern with a particular generator pattern,
Predictable convolution results can be generated. Even when changing the seed pattern from field to field to create a fractal animation or animation on the display screen of the video tube 98, the sequence of convolution results is desired, as will be explained in more detail later. You can make predictions as close as possible. Specific information about the placement of the generator pattern (or base pattern) contained in the seed pattern will cause the fractal generator to operate in parallel with the predictable results. Animated display sequences can facilitate the handling of seed patterns in response to elements of the display other than the generated fractals of particular interest. For example, dots are arranged in a higher density in a seed pattern at a position corresponding to a bow on a boat that pushes waves apart and the wave level of the bow is raised with respect to the stern.

The fractal generators 101 and 102 operate independently of each other and their fractal processing is also independent of each other, but more sophisticated results can be obtained by cooperating the fractal generators. A special fractal generator using an associated generator and seed pattern can be used for each color in a plurality of color palettes, for example. The following some examples give it.

Multiple fractal generators. It is possible to use the same seed pattern but different generator patterns.
These generator patterns consist of more complex generator patterns. The annular generator pattern is divided into component annular arcs to be used as generator patterns in various fractal generators, for example. The fractal generator generates a component fractal of a complicated fractal. The components of this complex fractal are each PR in the fractal processor.
The OM is colored and brightened respectively, and the generated ones are combined into R, G, and B formats.

Multiple fractal generators can use the same generator pattern and the same seed pattern in spaces sampled at lower densities, but different seeds in spaces sampled at higher densities to generate complex fractals. Patterns can be used. Different synthesizers can be used in the fractal generator for more densely sampled spaces.

With the exception of the offset between the same generator pattern and the same seed pattern, a set of fractal generators operated with each of these patterns have amplitudes to generate edge information for shading. Be compared.
Based on this description, many types of fractal processing techniques generated based on complex fractal functions can be foreseen.

Until now, mainly fractal generators and fractal
It has been considered to generate a still image in combination with a processor. Next, let us consider how to animate the graphic images generated by fractals. The basic method of providing animation in the apparatus of FIG. 1 is to use a read address signal supplied to the RAM group 10 or 15 being read and a write address signal supplied to another RAM group being written. This is a way to introduce additional corrections during. During subsequent field scans of this other RAM group, there will be motion in the fractal and in the display of the video tube 98 derived from it as they are read during the raster scan by the read address signal.

FIG. 7 shows a write address generator for the fractal generator of FIG. 1 which translates the display fractally generated by the write address generator across the screen. Horizontal drift variable offset is added by adders 121, 122, 123, 124
The horizontal scan column address portion of the write address signal is generated by being supplied with the appropriate scaling to be added to or subtracted from the lower bit of the basic write address signal therein. Vertical drift variable offset can be added in appropriate ratio to adders 125, 126, 127, 128
At, the vertical write row address portion of the write address signal is generated by adding to or subtracting from the higher bit of the basic write address signal. The vertical drift rate depends on the value of the vertical drift variable offset. The O vertical drift variable offset freezes the display vertically. A positive vertical drift offset scrolls the display upwards, assuming that the scan lines are sequentially numbered from top to bottom of the display screen. A negative vertical drift offset scrolls the display down. The horizontal drift rate depends on the horizontal drift variable offset. Assuming the pixels are numbered consecutively from left to right, a positive horizontal drift variable offset will scroll the display to the right,
A negative horizontal drift variable offset scrolls the display to the left. In order to prevent stepwise discontinuities in the line scans that appear in the display, the lift rate is limited to a function of the display screen width per field. However, this limit may be exceeded if desired. To do this, counter 27
Reset, and from the 8 least significant bit stages
The read address generator 23 is modified for carry to the higher bit stages.

FIG. 8 shows one type of circuit for rotating the fractal based display on the display screen of picture tube 98.
The address generator circuit 26 allows Cartesian
n) The basic write address signal generated in coordinates is fed to Cartesian-Polar coordinate converter 130 to convert the bit map address to polar coordinates. These polar coordinates, which appear one after another, consist of respective radial coordinates ρ and respective angular coordinates θ. The angular coordinate θ is supplied to one input of the adder 31 and added to or subtracted from the input of the rotational offset per field. The corrected angular coordinate θ ′ and radius component φ supplied from the output connection line of the adder 31 are supplied to the polar-Cartesian coordinate converter 132 and converted into a write address signal in Cartesian coordinates. Coordinate transformers 130 and 1
Each of 32 is constituted by a lookup table of a read only memory (RAM). Storage techniques for performing such conversion are well known. Techniques for raster rotation for performing a Cartesian coordinate-rotational Cartesian coordinate transformation are known for phantom signal raster scans of bit-mapped memory, which are written by other devices of this aspect of the invention. It is adapted to rotate the basic write address signal raster to obtain the address signal raster scan.

FIG. 9 shows a modification to the apparatus of FIGS. 7 and 8 so that the drift or rotation is not uniform over the field. Cascaded adders 133 and 134 modify the base write address not only by adding or subtracting the fixed offset in adder 133, but also by adding or subtracting a small random number in adder 134. . Instead of such a cascade adder, for example, the adder 131 shown in FIG. 8 can be used. Such a cascade adder could also replace each of the adders 121-128 of FIG. Random numbers for use in the apparatus of Figure 9 are randomly generated, for example, by regularly performing an analog-to-digital conversion of white noise. However, a series of random movements can be made predictable by selecting the random numbers in a defined order from a random number look-up table memory. In that case, the random numbers are not truly random, but can be viewed as being essentially pseudo-random or apparently random.

FIG. 10 shows how to introduce more complex motion than field drift or field rotation into the image display generated on the display screen of video tube 98. A 16-bit basic write address or read address signal allows multiple write address lookup memories (eg 141, 142, 14) that can be configured in the PROM.
3) is supplied as an address. In response to the address translation select command, the read selector 140 is one of the write address look-up memories to provide a 16-bit write address signal for the first, most densely sampled space. Is selected for reading. Given that the 16-bit basic write address signals for the sample space are in the address generator circuit 26 of FIG. 2, these 16-bit write address signals will be used for other, less densely sampled sample spaces. Decomposed to provide the write address signal. Examples of field movements that can be provided by the device of Figure 10 are as follows.

(1) Wellspring or source function: In this case, the size of the graphic image increases as it flows outward from the source point toward the edge of the image field.

(2) Drain function: In this case, the graphic image size decreases as the graphic image flows from the edge of the image field to the drain point of the image field.

(3) Wellspring function combined with rotation about the source point.

(4) Drain function combined with rotation about the drain point.

FIG. 11 shows a device for rotating the generator pattern supplied to the transducers 45-48, which device is used in place of the PROM 49 in the fractal generator of FIG. Not only is the generator pattern circuit useful for animating certain types of display images, but it can also be used to generate a wider variety of fractals.

The PROM 149 stores the generator pattern in a bit map configuration. PROM149 is stacked as a window scan (bank)
It is constructed and has an interpolator in it so that its contents are addressed by non-integrated row and column addresses. Such a memory is called "WINDOW SCANN".
ED MEMORY) "in U.S. Pat. No. 4,460,958 dated July 17, 1984.

Generator pattern loading control circuit 150 is PROM149
A plurality of generator pattern buffer memories (for example, four buffer memories 151, 152,
153, 154) to control the transfer of the selected generator pattern with the selected amount of rotation. The storage locations of these memories are scanned serially during the write period and used in parallel during the read period. This control is performed by the buffer memory write select command supplied to the multiplexer 155, and enables the writing of one selected one of the buffer memories 151 to 155 by the generator pattern read from the generator pattern PROM 149. Multiplexer 155, which operates as a generator pattern selection control circuit, determines which of the generator patterns stored in generator pattern buffer memories 151-155 if more than one fractal generator is used in parallel. Convolver 45 to 4
8, and controls whether to feed something like a replica of the fractal generator of FIG. This control is performed by the multiplexer 157 to which the buffer memory read selection command is supplied from the generator pattern selection control circuit 156. Mini-raster scan generator 158 generates an address scan for write buffer memories 151-155. Mini-raster scans are miniature raster scans that spread over a relatively small area of the image field. The mini-raster scan generator 158 provides its raster scan memory address as an input to the phantom raster generator 159, which rotates the phantom mini-raster according to the generator pattern rotation command supplied from the generator pattern loading control 150. Causes scan conversion to occur. The generator pattern rotation command is programmed by the operator. The generator patterns are sequentially and cyclically supplied during each mini-raster scan period, and via multiplexer 155 each one of the generator pattern buffer memories 151-154.
Will be written on one.

When a display animation by rotation of a generator pattern is required, the generator pattern selection control circuit 156 sequentially selects the sequentially rotated generator patterns from the buffer memories 151-154 and the convolvers 45-48. Give a convolution with a seed pattern inside. This sequential selection causes the pattern on the display screen of video tube 98 to rotate clockwise, counterclockwise, or a combination thereof.

The apparatus of FIG. 11 can also be used to generate complex fractals using multiple fractal generators operated in parallel. The seed pattern used in the fractal generator is different, and the generator pattern selection control circuit 156 produces a generator pattern of different rotations for the fractal generator in each sample space.

Figure 12 shows another fractal generator capable of producing animated fractals in real time. Single convolver 160 has PROM33, PROM34, PROM4
5, with seed pattern selectively supplied from dot pattern generator 36 or random dot generator 37
It is used to generate a convolution result for each bandpass component of the derived fractal by applying the convolution to the generator pattern selected from PROM49. There is one selected seed pattern with very fine resolution, whereby the generator pattern selected from PROM 49 is convolved to generate each different spatial frequency component of the fractal.

These convolutions are performed to sequentially generate one frame of very fine resolution video signal samples for each of the spatial frequency bands, a very small size fractal change being written to each frame storage RAM 161. Fractal change of small size is RA for each frame memory
A large size fractal change is written to each frame storage RAM 163, and a very large size fractal change is written to each frame storage RAM 164. RAM16
1, 162, 163, and 164 are configured to be continuously scrollable in both horizontal and vertical scanning directions. The frame memory write / read control circuit 165 is a frame memory RAM 16
Controls writing of 1, 162, 163, 164. The control circuit 165 commands the memory address multiplexer 170 to direct the RAM 161,
162, 163 and 164 are connected to a write address generator 166 during the write period to provide the full resolution write address provided at the regular pixel scan rate. In the frame scan, the read / write control circuit 165 controls the write address generator 166 to use the seed pattern PRO at the normal pixel scan rate.
A frame scan is provided to feed M33, 34, 35, and dot generators 36 and 37 generate dots with a particular average density in each scan direction. Seed pattern PROM 33, 34, 35, dot pattern generator 36,
Alternatively, the seed pattern from the selected one of the random dot generators 37 is convolved with the generator pattern selected from the PROM 49. The result of the convolution is for a very small size fractal change, which is directed by the read / write control circuit 165 to the input / output bus of the frame store RAM 161 which it conditions to write. In the second frame scan, the read / write control circuit 165 commands the write address generator 166 to generate an address that scans a quarter portion of the entire frame at a rate of 1/4 the normal pixel scan rate. And dot generators 36 and 37 command to generate half the specified average density of dots in each scan direction. The convolution result generated at a rate of 1/4 of the normal pixel scan rate is fed to the expander 167, which uses interpolation techniques to double the sample matrix density in each direction. Control circuit 165 directs these magnified convolution results supplied at the regular pixel scan rate to the input / output bus of RAM 162 and instructs RAM 162 to write the results to its frame storage locations. In the third frame, the read / write control circuit 165 commands the write generator 166 to generate an address that scans a 1/16 portion of the entire frame at a 1 / 16th of the normal pixel scan rate, Generators 36 and 37 in each scan direction
Instruct to generate 1/4 the specified average density of dots. The convolution result, generated at a rate of 1/16 of the normal pixel scan rate, has a sample matrix that is doubled in each direction using interpolation techniques and is cascaded by the expander 167. And performed by 168. The read / write control circuit 165 supplies the twice-doubled convolution result supplied at the normal pixel scan rate to the input / output bus of the RAM 163 and sends the result to the RAM 163 for the frame. Instruct to write to a memory location. In the fourth frame scan,
The read / write control circuit 165 commands the write generator 166 to generate an address that scans 1/64 of the entire frame at a rate of 1/64 of the normal pixel scan rate, and dot generators 36 and 37 each. Command to generate 1/8 of the specified average density dots in the scan direction. Regular pixel scan rate
The convolution result generated at a rate of 1/64 has the sample matrix doubled three times in each direction by continuously connected expanders 167, 168 and 169. The read / write control circuit 165 is
Supply the input / output bus of the convolution result RAM164 expanded three times at the regular pixel scan rate to the RA
Causes M164 to write the result to that frame storage location.

In another way of writing to the frame store RAM 161, 162, 163, 164, the convolution by the convolver 160 is based on time division multiplex. Every other time of two regular pixel scan rate sample times is allocated to write RAM 161, and alternating remaining sample times are allocated to write RAM 162. In addition, the alternating remaining sample time is allocated for writing to RAM 163 and the alternating further remaining sample time is allocated for RAM 164.

Yet another way to write to RAM 161, 162, 163, 164 is to use rate buffer memory after convolver 160. These rate buffer memories are used to write the convolution result samples at a reduced rate, the expander samples to RAM162, the expander samples to RAM162, and two consecutive RAM163 samples. In order to write the sample generated by the expander, the RAM 164 is supplied to write the sample generated by the three successive expanders.

After writing very small size fractal change, small size fractal change, large size fractal change, and very large size fractal change to RAM161, 162, 163, 164 respectively, then each address offset for each frame By scanning these RAMs while introducing
Generate a series of frames of video that represent a fractal-based animation. During this phase of operation, the read / write control circuit 165 provides the RAM 161, 162, 163, 164 to the memory address multiplexer 170 and the read generator 171.
And the read address is supplied. The fractal components read from the RAMs 161, 162, 163, 164 onto their input / output buses are combined in a combiner 172 to generate a fractal which is supplied to a fractal processor 78. The combiner 171 may be, for example, an addition tree.

FIG. 13 is a block diagram useful for understanding how an address is generated. Write address generator
Assuming a master clock oscillator 173, an interlaced frame of 512 lines, and 512 pixels per scan line, the 166 is a clock oscillator modulo 2
^{It comprises} a counter 174 for counting ^twelve . Counter 174
9 of the write address generated as its output by
The most significant bits identify the scan line by number, and the nine least significant bits represent pixel locations along the scan line. As mentioned above, to implement the serial convolution method of FIG. 12, both of these write address components have some of their respective lower bits discarded. Assuming that the assumed line scan is in the horizontal direction, the 9 least significant bits of the write address signal are provided to the horizontal address corrector 175, which is a RAM 161, which indicates the pixel location along the scan line. Generate portions of read address signals for 162, 163, 164. This is done in a manner similar to the vertical address modifier 176 described below. Vertical address corrector 1
76, in reading each of the RAMs 161, 162, 163, 164, generates the other part of the read address signal representing the scan line by a number.

In the vertical address corrector 176, the write address signal 9
The most significant bits have an offset added to them in adder 177 and generate the scan line identification portion of the RAM 161 read address signal. The offset is supplied from the output register 178 to the adder 177, and integrates a series of address changes for each frame. During frame retrace, adder 179 offsets register 178 from the previous frame line scan line, or number of vertical scroll components.
The line change to the offset of the preceding frame stored in it is added and the resulting sum is offset register 178
Sent to update its contents.

Similarly, the 9 most significant bits have an offset that is added to them in adders 180, 183, 186 to scan the read address signal of RAM 163 and the read address signal of RAM 162 of each read address signal of RAM 64. Generate the line identification part. Offset registers 181 and 182 are connected to accumulate the offset supplied to adder 180. Offset register 184 and adder 185 are connected to accumulate the offset supplied to adder 183. Offset register 187 and adder 1
88 is connected to integrate the offset supplied to the adder 186. Adder 177, 179, 180, 182, 183, 185, 18
The 6,187 are preferably adapted to allow the use of numbered numbers, and movements in either of the two opposite directions can be conveniently performed.

By doubling the frame-to-frame increments provided to the adders 182, 183, 184 as compared to the frame-to-frame increments provided to the adders 181, 182, 183, respectively, a simple frame-to-frame increment is obtained. As an example of an animation to, cause a vertical movement of all fractals. More complex movements of the component fractals can also be constructed, for example rotations using phantom raster scanning techniques.

FIG. 14 shows a fractal generator similar to the fractal generator of FIG. 12, using a single convolver 160 to generate fractal components of various sizes. However, the fractal generator of FIG. 14 does not resample all fractal components into the high spatial resolution sampling matrix for storage in frame store RAM 161, 162, 163, 164 as was done in FIG. Instead, the highest spatial resolution convolution result provided by convolving at the regular pixel scan rate is stored in one frame store RAM 190.

RAM 190, which is equivalent to RAM 161 in the fractal generator of FIG. 12, continuously provides the stored highest spatial resolution convolution result for the first sample space. RAM1
The 90 also provides a stored convolution result for the second sample space which was continuously expanded 2: 1 on each spatial dimension scale. This is the 12th
It produces an enlarged convolution result at the next highest spatial resolution for an area that is four times the area stored in the frame storage RAM 162 of the fractal generator shown. RAM1
The 90 also provides a stored convolution result for the third sample space, which was expanded twice in succession to 2: 1 on each spatial dimension scale, yielding a total 4: 1 expansion on each spatial dimension. give. This is
It provides the convolution result scaled from the lowest spatial resolution to the second resolution for 16 times the area stored in the frame store 163 of the fractal generator of FIG. Finally, RAM 190 provides the stored convolution result for the 4th sample space, which was expanded 3 times 2: 1 on each dimension scale. This provides the expanded convolution result at the lowest spatial resolution for an area of 64 times the area stored in the frame store 164 of the fractal generator of FIG.

In the fractal generator shown in FIG. 12, the frame memory RA
When you scroll the M161, 162, 163, 164 completely, you will notice a circular panoramic effect. With the fractal generator of Figure 14, the circular panoramic effect is barely noticeable. Only the highest spatial frequency details are circularly repeated on a frame-by-frame basis. The lower spatial frequency fractal component recursively repeats a small number of times. If the circulation length is longer than the spatial wavelength that creates the circulation pattern, there is a psychophysical phenomenon that the circulation repetitive shape is hard to notice. Simply put, the major feature of an image that begins to recoil over a given distance is easier to remember than the complexity of the details that accompany the recurrence. Circular recurrence of higher spatial frequency details becomes difficult to detect when it is superimposed on lower spatial frequency details that recurs more frequently. Circular recurrence becomes more difficult to detect when the fractal often undergoes non-linear processing in generating the display image. In fact
In the fractal generator of Figure 14, the circular panorama completes its loop only after 8 frames of crossing passages have been completed. When the fractal generator is used, for example, to generate a playing field in a video game, this various increase in the area of precisely marked (mapped) fractals in the frame store becomes important.

This increase in the area of fractal variation stored in the bit-mapped memory is due to fractal self-similarity. This increased area accumulation phenomenon is utilized in a slightly different way than the fractal generator of FIG. The fractal generator of FIG. 14 can be modified by replacing frame store RAM 190 with, for example, 1/4 frame store RAM. The uncorrected fractal generator of FIG. 14 from this 1/4 frame storage RAM often produces recurring fractals that cycle twice. In practice, the size of RAM 190 is reduced until one finds a circular panoramic effect that becomes noticeable to most viewers of video graphics generated from the particular fractal that they choose to generate.

Also, the fractal generator of FIG. 1 can be modified to take advantage of the increased area accumulation phenomenon. RAM12 and 17 dimensions increased by a factor of 4, RAM13 and 18 dimensions increased to 16
By increasing the size of RAMs 14 and 19 by 64 times, the circular panoramic effect can be reduced, so that each of RAMs 11-14, 16-19 has as many addressable storage locations as other RAMs. have. That is, the circular panoramic effect can be reduced by a factor of 8 by increasing the size of the RAM about 3 times for addressable storage locations.

The fractal generator of FIG. 14 is considered in more detail for the first time by storing the convolution result in RAM 190. In response to the read / write command signal in its write state, the input memory multiplexer 189 is
The convolution result from 60 is provided on the input / output bus of RAM 190, RAM 190 is conditioned to write the convolution result to its addressed storage location, and memory address multiplexer 191 sends the write address signal to RAM 190. Provide to specify the storage location where successive convolution results are written to the storage of the bit map configuration.

RAM1 when the read / write command signal is in the read state
90's are configured (conditioned) to be read on their input / output busses and memory address multiplexer 191
Are conditioned to select a read address signal from read address generator 171 to address a storage location in RAM 190. Read address control circuit 191
Are enabled to read the frame store 190 at the first sample space, the second sample space, the third sample space, and the fourth sample space based on time division multiplex. . Time division multiplexing is performed at twice the normal pixel scan rate. The order in which one of the recurrent cycles of time division multiplex is performed during a line scan is 1, 2, 1, 3, 1, 2,
1, 4, 1, 2, 1, 3, 1, 2, 1, and N. In this order, 1, 2, 3, 4 are the first, second, third,
Represents the sample in the fourth sample space,
N represents O samples to fill the cycle void. Successive 1s in the cycle represent successive samples in the first sample space, and successive 2s in the cycle.
Represents consecutive samples in the second sample space and consecutive 3 represents consecutive samples in the third sample space.

Every other sample of scan rate twice the normal pixel scan rate read from the frame storage RAM 190 is the first
Is assigned to the sample space of to specify the fractal component with the highest resolution. The read address control circuit 192 assumes the read address generator 171 to provide the read address signal to the address generator 171 for the first sample space. Read address control circuit 1
92 also conditions the memory output multiplexer to provide the convolution result for the first sample space read from RAM 190 to synthesizer 77. Synthesizer 77
In the above, the convolution result is
It is combined with the expanded convolution result supplied from 76 to generate the fractal which is supplied to the fractal processor 78.

The read address control circuit 192 conditions the RAM 190 to read every second line of the frame scan at a selected one of the two available spatial phases in the vertical direction and is assigned to the second sample space. Supply the convolution result. Of the normal double pixel rate samples read from the RAM 190 in the selected alternating scanlines, alternating every other of these alternating samples allocated to the first sample space. One is assigned to the second sample space according to the time division multiplex method, where the fractal component with the second highest spatial resolution is identified. During those sample times allocated to the second sample space, the read address control circuit 192 conditions the read address generator 171 to provide the read address signal for the second sample space. This read address signal has delay compensation for the expander 76 at that offset. At the same time, the read address control circuit 192
Conditions memory output multiplexer 193 to provide the signal read from RAM 190 to combiner 75. In the combiner 75, the signal supplied from the RAM 190 is combined with the expanded signal supplied from the third sample space supplied from the expander 74. The signal read from RAM 190 is shown as being provided to combiner 75 via the action of adjustable clocked delay element 196 rather than directly. The adjustable clocked delay element 196 under the control of the read address control circuit 192 has a second selected one of the two possible horizontal phases, as shown for the first sample space. Adjust the spatial phase of the space sample. This enables horizontal scrolling with a first sample space resolution, expands the arbitrary allocation of spatial phases associated with the time division multiplex method, and allows the spatial phase of the second sample space to be expanded. Can be freely selected as in the fractal generator shown in FIG.

The read address control circuit 192 provides a fourth convolution result assigned to the third sample space, every fourth of the frame scan, in a selected one of the four available spatial phases in the vertical direction. Condition the RAM 190 to read the line. Time division multiplex
Every other one of the remaining unselected samples of the sample at twice the normal pixel scan rate in the cycle is assigned to the third sample space according to the time division multiplex method, where The next fractal component of low spatial resolution is identified. During those sample times allocated to the third sample space, the read address control circuit 192 will
The read address generator 171 is set to supply the read address signal for the space. This read address signal contains the delay compensation for the expander 74 at that offset. At the same time, the read address control circuit 192 supplies the signal read from the RAM 190 to the combiner 73 so that it may be combined with the expanded signal supplied from the fourth sample space supplied by the expander 72. Set the memory output multiplexer 193. RAM
The signal read from 190 is provided to combiner 73 by the action of adjustable clocked delay element 195 rather than directly. The adjustable clocked delay 195, under the control of the read address control circuit 192, provides a third to third selected phase of the four possible horizontal phases, as described for the first sample space. Adjust the spatial phase of the space sample. This allows horizontal scrolling of the fully expanded third sample space with the first sample space resolution.

The read address control circuit 192 reads the 8th of the frame scan in the selected one of the 8 available spatial phases in the vertical direction to provide the convolution result assigned to the 4th sample space. Set RAM190. Every other of the remaining unselected ones of the samples at twice the normal pixel scan rate in the time-division multiplex cycle that occurs on every selected eighth line scan is the time-division Marutiplex. According to the method, it is assigned to the fourth sample space, where the fractal component with the lowest spatial resolution is identified. During those sample times assigned to the fourth sample space, read address control circuit 192 sets read address generator 171 to provide the read address signal to the fourth sample space. This read address signal has delay compensation for the expander 72 during its offset. At the same time, the read address control circuit 192 supplies the signal read from the RAM 190 to the combiner 71 and, if present, combines with the direct component supplied from the generator pattern PROM 49 via the connecting line 70. RAM190
The signal read from is supplied to combiner 71 by the action of adjustable clocked delay 194, rather than being supplied directly to combiner 71. Adjustable clocked delay under the control of the read address control circuit 192 1
94, as mentioned for the first sample space,
Adjust the spatial phase of the fourth space sample for the selected one of the eight possible horizontal phases. This allows horizontal scrolling of a fully magnified fourth sample space with the first sample space resolution.

Adjustable clocked delays 194, 195, 196 may be, for example, "Advance Micro Devices Inc.
vanced Micro Devices, Inc.) ”.
“Multi-level pipeline registers (multil
A product named "evel pipeline registers)" can be used. The number of clock cycles of delay through these devices is such that it compensates for the time offset introduced by the time division multiplex in the direction of the line scan. It has a certain component.In addition, the devices 194, 195, 196
It has a component corresponding to an additional bit of the spatial resolution in the horizontal component of each read address signal in the second, third and fourth sample spaces. In the second sample space there are additional bits of horizontal resolution and in the third sample space there are two additional bits, the fourth sample space.
There are 4 additional bits in space. A time-division multiplex read from RAM 190 is needed to provide the limitations imposed on the sampling horizontal phase from RAM 190 in the second, third and fourth sample spaces.

A suitable method can be provided for providing vertical scrolling of the second, third, and fourth sample spaces with the first sample space resolution. This can be easily dealt with by adjusting the differential delay of the start of the read address signal raster scan in various sample spaces. Despite the adjustment of the relative spatial phase of the raster scans in the four sample spaces, the timing of the clock and shift signals for the expanders 72, 74, 76 tracks the read address raster scan in each of those sample spaces. I have to continue.

The fractal generator of FIG. 14 can also be modified by replacing the RAM 190 with two RAMs that store the convolution result of the convolver 160 in parallel, in which case the RAM read is normal. At a pixel scan sample rate of. One RAM supplies the convolution result for the first sample space, the other RAM
Provides the convolution result for the second, third, etc. sample spaces.

The configuration of the fractal generator of FIGS. 12 and 14 can be easily modified so that one RAM or set of RAMs is read to generate a series of fractal animations and the other RAM or RAM The tuple is written with the convolution result used to generate the next series of fractal animations. Variations of the fractal generator of FIGS. 12 and 14 which of course can use field-to-field line interlacing are also possible.

FIG. 15 shows a fractal generator that, instead of storing fractal results in memory, relies on storing the seed pattern itself as a basis for the location of the various fractal components in their respective sample spaces. The address generator 197 provides a raster scan read address signal to the selected one of the seed pattern PROMs 33, 34, 35. First
This is done on a time division multiplex basis in response to a control signal from the time division control circuit 198, much like what was done with the fractal generator of FIG. The multiplex control circuit 198 also controls the multiplexer 199 to control the seed pattern PROMs 33, 34, 35.
The signal read from the selected one of the two is supplied to one of the convolvers 45, 46, 47, 48 operating in the sample space to which the current sample of the read raster scan is associated. Before the lower spatial frequency circular panoramic effect occurs, the fractal generated by the fractal generator of FIG. It is spread over the area of 64 times.

The seed pattern information is less scattered in the space than the convolution result, and its occurrence includes uniformity. Therefore, the memory storage seed pattern of reasonably coarsely distributed dots in the space is likely to be denser than the memory storage convolution result. For example, the seed pattern may be stored in a line address memory where the run length code indicates the dot position along the scan line. Another example is a selected seed pattern PROM3 that stores the lower ones of the dot addresses in memory as data in a somewhat coarser resolution raster scan.
3, 34, 35 may be addressed. The PROM is then read at full resolution using pixel implementation techniques. This pixel execution technology was announced on November 6, 1984 in "RASTER
-SCANNED DISPLAY SYSTEM FOR DIGITALLY-ENCODED GRAP
It is shown in U.S. Pat. No. 4,481,509, patented under the name "HICS". If the dot pattern is inherently repetitive, then a small memory size is selected and its storage location is read many times. A seed
Seed pattern memory can be used by using the pattern, and its storage location is "COMPACTION OF TE
LEVISION DISPLAY GRAPHICS IN PHANTON-RASTER-SCANNE
Addressed by discontinuous integral spatial coordinates according to the technique described in US Pat. No. 4,442,545, issued Apr. 1, 1984, entitled "D IMAGE MEMORY".

In the design of a convolver for the generation of animated fractals according to the present invention, a circular panoramic look of image data retrieved from memory
Arounds are stored in a space that is considered as a circulation item as a module. The convolution result of a generator pattern with seed pattern dots near one end of the range of memory addresses in the spatial dimension (memory addresses are non-modular, in bounded memory address spaces Is present not only at that end within its range, but also near the opposite end. Otherwise, there will be discontinuities in the convolution result that are visibly present in the scanned fractal. Convolution in a module space item is easily constructed by scanning the memory several times over, but the seed pattern is the end of the memory address space, or the dot generator 36 and
You need to consider whether you have a dot at the end of that space for 37.

The fractal generation process described here can also be applied to generate related functions that are not strictly fractal, in which case the generator patterns contained in the convolutions at different scales are similar in shape. It's not a change. "Fractal" in the claims is used in a sufficiently broad sense to include such a relationship.

[Brief description of drawings]

1 is a block diagram showing the structure of a fractal generator embodying the present invention, and FIG. 2 shows in detail the address generator in the fractal generator of FIG. 1 for generating a read address and a basic write address. Block diagrams, FIGS. 3 and 4 show another form of block diagram which can be used in place of each convolver in the fractal generator of FIG. 1, and FIG. 5 shows the fractal generator of FIG. FIG. 6 is a block diagram of a type that can be used as each expander, and FIG. 6 shows a fractal processor that can be used after the fractal generator of FIG. 1 to generate a graphic image from the generated fractals. Block diagram, Fig. 7 is a diagram for giving translation or drift motion to the graphic image generated from the fractal. Figure 8 is a block diagram of a write address generator for a fractal generator, Figure 8 is a block diagram of a write address generator for imparting rotational motion to a fractal generated graphic image, and Figure 9 is a fractal generated. FIG. 10 is a block diagram of a write address generator obtained by modifying the write address generator of FIG. 7 or 8 to give randomness to the movement of the graphic image, and FIG. 10 is selective to the graphic image generated from the fractal. Block diagram of a write address generator for providing more complex movements, FIG. 11 shows a seed
FIG. 12 is a block diagram of an apparatus for rotating the pattern of the generator before being convolved with the pattern, FIG. 12 is a block diagram of another fractal generator embodying the present invention, and FIG. Block Diagram of Address Generator Used in Fractal Generator of FIG. 14 and FIG. 15 are block diagrams of still another fractal generator embodying the present invention. 45, 46, 46, 48, 160 …… Convolver, 71, 73, 75, 77 …… Combiner, 161, 162, 163, 164 …… Fractal frame memory RA
M, 165 ... Frame memory RAM read / write control, 166 ...
… Write address generator, 167, 168, 169 …… Expander, 170 …… Memory address multiplexer, 171
...... Read address generator, 172 …… Combiner, 194, 195, 1
96 …… Adjustable clock delay.

Claims (55)

[Claims] 1. A method for generating a fractal for generating a convolution integral result for each of a plurality of consecutively ordinal sample spaces in the order of further sparse sampling. The pattern is convolved with the seed pattern of dots, and each convolution integral in a higher ordinal sample space is expanded by interpolation to a sampling density comparable to that in a lower ordinal sample space, For each corresponding sample, combine the samples of the convolution integration result and the expansion convolution integration result with similar sampling density, and the expansion convolution integral of each higher ordinal sample space finally becomes the first sample space. Perform the expanding and combining steps by interpolation, as combined with the convolution integral in, thus generating a fractal The method comprising extent. 2. A method of generating a fractal, wherein a dot seed pattern is prepared in each of a plurality of sample spaces to which consecutive 1st to nth ordinal numbers are attached, and 1
The second sample space is regularly sampled in multiple dimensions, and each of the other sample spaces is regularly sampled in these dimensions more sparsely than the sample space with the next lower ordinal, and the normalized sample A generator pattern is prepared in the space, spatial convolution of the generator pattern and each seed pattern is performed in each sample space, and interpolation is performed to obtain each of the other sample spaces. The spatial convolutional integration result is expanded to the sampling density of the first sample space, and the expanded spatial convolutional integration result is combined with the spatial convolutional integration result obtained in the first sample space. And a step of forming the fractal. 3. The expanding and combining steps expand the spatial convolutional integration result obtained in the nth sample space to the sampling density of the (n-1) th sample space by interpolation. , The expanded spatial convolutional integration result obtained in the nth sample space is combined with the spatial convolutional integration result obtained in the (n-1) th sample space, and then (n-2) In each of the 1 st to 1 st sample spaces, the spatial convolutional integration results obtained in that sample space as well as the expansion results obtained previously in the next higher ordinal sample space are combined one after another by interpolation, Extend the combination result in each sample space other than the second to the sampling density of the next lower ordinal sample space so that the fractal is obtained from the combination in the first sample space. Method of generating a fractal claims 2, wherein the including the. 4. A method of generating a fractal according to claim 3, wherein said combination is additive. 5. A method for generating a fractal according to claim 2, wherein the combination is additive. 6. A dot seed pattern is selected in each of the plurality of sample spaces, a generator pattern is selected in a normalized sample space, and spatial convolution integration is performed in each sample space. Repeating the steps of expanding and combining, the selection of the seed pattern being modified in the course of this iteration to produce a series of fractals which, in addition to the fractals, contain at least one further fractal. A method for generating fractals according to range 2. 7. A dot seed pattern is selected in each of the plurality of sample spaces, a generator pattern is selected in the normalized sample space, and spatial convolution integration is performed in each sample space. A series of fractals including at least one other fractal in addition to the fractal, which comprises repeating the steps of enlarging and combining, changing the positioning of the seed pattern relative to a reference point in space in an iterative process. A method for generating a fractal according to claim 2, which produces 8. A dot seed pattern is selected in each of the plurality of sample spaces, a generator pattern is selected in the normalized sample space, and spatial convolution integration is performed in each sample space. A step of rotating the generator pattern in at least one sample space to include at least one other fractal in addition to the fractal in the course of repeating the steps of expanding, expanding and combining. A method for generating a fractal according to claim 2, which produces 9. A dot seed pattern is selected in each of the plurality of sample spaces, a generator pattern is selected in the normalized sample space, and spatial convolution integration is performed in each sample space. Repeating the steps of expanding and combining, in the course of the iterations, rotating the seed pattern in at least one sample space to produce a series of fractals including at least one further fractal in addition to said fractals. A method for generating a fractal according to claim 8. 10. A dot seed pattern is selected in each of the plurality of sample spaces, a generator pattern is selected in the normalized sample space, and spatial convolution integration is performed in each sample space. Repeating the steps of expanding and combining, in the course of this iteration, rotating the seed pattern in at least one sample space,
A method of producing a fractal according to claim 2 which results in a series of fractals which, in addition to said fractal, comprises at least one further fractal. 11. A method of generating a first raster scan video signal in sampled form, wherein a first sample space is regularly sampled in a plurality of dimensions and each other sample space is then sampled. For each field scan, in each of the plurality of sample spaces having the 1st to nth consecutive ordinal numbers, which are regularly sampled in the same dimension more sparsely than the sample space having the low ordinal number. A dot seed pattern is prepared, and for each field scan, a respective generator pattern for each of the plurality of sample spaces having the first to nth consecutive ordinal numbers is prepared, and according to the raster scan pattern, Perform a spatial convolution of the seed pattern and each generator pattern sampled at the same sampling density to obtain each field For the scan, the convolution integration result at each sampling density is obtained, and the convolution integration result having a lower sampling density is expanded by interpolation, and the convolution integration results are combined at the same sampling density, and the expansion is performed. In response to the steps of combining and combining, determining a combination of their convolutional integration results in a raster scan sample space, each level sample of the combination of convolutional integration results according to an established scheme. A method comprising converting each level sample of a first raster scan video signal. 12. The step of transforming each level sample of the combination of convolutional integration results includes converting each level to a first,
The respective levels of the second and third raster scan video signals
The method according to claim 11, wherein the method is to convert into a sample. 13. The method according to claim 12, wherein the first, second and third video signals are a red video signal, a green video signal and a blue video signal. 14. A method of generating a composite video signal using a first video signal generated by the steps of the method of claim 11, further comprising synchronizing with the first raster scan signal. To generate at least one further raster-scanned video signal in a time division multiplexed manner.
Video signal and at least one other video signal to generate the composite signal. 15. A map in which the step of time-multiplexing selecting from the first video signal and the at least one further video signal is stored, at least in part, in a synchronously scanned memory. 15. The method according to claim 14, which is controlled using 16. A time division multiplexed selection from the first video signal takes precedence over a portion of each of the other video signals and a portion of the first raster scan video signal that are within a range. The composite video signal by assigning a rank and selecting, for each successive sample, the highest priority assigned sample of the first video signal and each of the other video signals. 15. The method according to claim 14, which is performed by the step of generating. 17. Means for generating a raster scan seed pattern of dots in each of a number of two-dimensional sample spaces, numbered from 1 to n consecutive ordinal numbers, such that they are sampled sparsely one after the other. And a means for limiting the generator pattern placed over the array of categorized pixel positions, and a raster scan seed pattern in each sample space, similar to where the generator pattern was placed. A means for extracting a successive array of pixel positions and convoluting in each sample space the successive array of generator patterns and each successive array of categorized pixel positions from a raster scan seed pattern in the sample space. And a means for obtaining respective convolution integration results and each sample space except the first one, and by interpolation, in that space, The means sampled in the nth space is expanded from the respective means for expanding the sampled function to the sampling density of the sample space of the next lower ordinal number and the convolution integration result in the nth sample space. Means for extracting a function to be expanded thereafter through interpolation, and a convolution integral result in the sample space is interpolated through interpolation in each of the first to (n-1) th sample spaces. In each of the second to (n-1) th sample spaces, in combination with a function that is expanded to the sampling density of the sample space, by means for expanding the function in that space, then expanded through interpolation. Generating a function sampled in the space and generating the fractal showing the amplitude change in the first sample space, Fractal generator and a stage. 18. At least one fractal generator according to claim 17 and having at least a selected time instant responding to different amplitudes of the fractals generated by each said at least one fractal generator. And a video signal generator having means for generating different color video signals. 19. Having at least one fractal generator according to claim 17, and responding to different amplitudes of the fractals generated by each said at least one fractal generator at least at selected times. And a video signal generator provided with means for generating video signals having different intensities. 20. In a method of generating a fractal, a seed pattern of dots is prepared in a normalized sample space which is regularly sampled along a spatial coordinate in a plurality of dimensions, and the dot seed pattern is prepared in the normalized sample space. A generator pattern is prepared, the generator pattern is convolved with the seed pattern to generate a convolutional integration result, and the convolutional integration result is obtained for each set of integer values of the spatial coordinates. Writing to a first memory having identifiable storage locations, expanding at least a portion of the convolutional integration result a number of times through interpolation in each of the plurality of dimensions, and expanding the convolutional integration result once. , Writing to a second memory having a storage location that can be confirmed for each set of the integer values of the spatial coordinates and expanding the convolution integral result a plurality of times, for each set of the integer values of the spatial coordinates. On the other hand, writing to different memories each having a recognizable storage position, reading the successive storage positions of the first, second and other memories by parallel scanning, and combining successive ones of the parallel scanning to obtain successive samples of fractal. A method including the steps of generating. 21. The steps of claim 20 are further repeated for each successive field of parallel scanning of successive storage locations of said first, second and further memories, said first, second and 21. A method as claimed in claim 20, in which the offset of each parallel scan relative to the parallel scan of the memory at the time of writing is varied between fields of the parallel scan of successive memory locations to animate the fractal thus generated. . 22. The method of generating fractals according to claim 21, wherein said combination is additive. 23. A method of generating fractals according to claim 20, wherein said combination is additive. 24. In combination with the method for generating a fractal according to claim 20, converting successive level samples of each of the generated fractals into samples of a video signal according to an established scheme and thus generated. The order of each of the raster-scan video signal samples
A method of generating a first video signal, the method including converting the video signal into respective portions. 25. A first video signal generated by the steps of the method of claim 24, further comprising at least one further video signal raster-scanned in synchronism with said first raster-scan signal. A method of generating a composite video signal by generating and generating a composite signal by time division multiplexing from the first video signal and the at least one other video signal. 26. Time division multiplexed selecting from said first video signal and said at least one video signal is at least partially using a map stored in a memory which is synchronously scanned. Controlled claims 2
The method according to 5. 27. Time division multiplexed selection from the first video signal takes precedence over a portion of each of the other video signals and a portion of the first raster scan video signal that are within a range. Generating a composite video signal by assigning a rank and selecting for each successive sample the highest priority assigned sample of said first video signal and said another video signal. A method according to claim 25 which is carried out. 28. In a fractal generator for generating a raster scan fractal in the form of sampling data showing amplitude changes, the first to nth ordinal numbers are successively given, and each of the successive larger scales. Memory of multiple bit mats with each addressable array of storage locations for storing the fractal components of the, and raster scan each memory of each bit map in sync with the other during the read cycle. And each of the successive addresses in the synchronous raster scan, each set of fractal component samples read in parallel from the plurality of bit-mapped memories are combined to obtain the sampling data. Means for generating one of successive samples of the raster scan fractal in form, each fractal component being the bit map structure. Selectively adjusting the offset of each raster scan of the bit-mapped memory during each successive raster scan in a read cycle relative to the order stored in the addressable array of memory locations of the memory. ,
A fractal generator having means for animating the generated fractal. 29. n is an integer that is at least 3 and means for scanning memory locations in memory of each bit map organization in parallel during a write cycle and at selected intervals during the write cycle. A means for generating dots, a means for convolving and integrating each dot with a generator pattern to generate a convolution integration result in the form of sampling data as a fractal component of the smallest scale, and a fractal for the smallest scale. A means for writing the component into a memory of a first bit map configuration, and expanding the convolution integral through interpolation in each spatial dimension to provide expanded sampling as the fractal component of the next graduation of the smallest graduation. -Means for generating the convolution integral result in the form of data and the fractal component of the next graduation of the smallest graduation are written in the memory of the second bit map configuration. Means for further expanding said convolution integral through interpolation in each spatial dimension to generate successively larger scale (n-2) additional fractal components, and each said additional Fractal component,
29. A fractal generator according to claim 28, further comprising means for writing to a memory having a bit map structure other than the first and second memories, respectively. 30. At least one fractal generator as set forth in claim 28, and responsive to different amplitudes of fractals generated by each said at least one fractal generator at least at selected times. And a video signal generator having means for generating different color video signals. 31. Having at least one fractal generator according to claim 28 and responding to different amplitudes of the fractals generated by each said at least one fractal generator at least at selected times. And a video signal generator having means for generating video signals of different intensities. 32. A method of generating a fractal, wherein a seed pattern of dots is prepared in a first sample space which is regularly sampled in a plurality of dimensions, a generator pattern is prepared, and the first pattern is prepared. Convolution-integrating the dot seed pattern of the sample space with the generator pattern of the first sample space to generate a spatial convolutional integration result of the first sample space, the first sample The spatial convolutional integration result is stored in a memory having a storage location for mapping a space, where n is an integer of at least 3 and the second to nth ordinal numbers are given,
A spatial attributed to another sample space such that each said other sample space is regularly sampled in each of said plurality of dimensions less sparsely than the sample space having a lower ordinal number than itself. In order to reproduce a convolutional integration result, a part of the mapped first sample space is selected, and the spatial convolution integral obtained in each of the other sample spaces is interpolated to obtain the first sample space. A sampling density and combining the expanded spatial convolutional integration result with the spatial convolutional integration result obtained in the first sample space to produce the fractal. 33. The expanding and combining step expands the spatial convolutional integration result obtained in the nth sample space to the sampling density of the (n−1) th sample space by interpolation, The expanded spatial convolutional integration result obtained in the nth sample space is combined with the spatial convolutional integration result obtained in the (n-1) th sample space, and then (n- 2) In each of the 1 st to 1 st sample spaces, combine the spatial convolutional integration result obtained in that sample space with the expanded result obtained previously in the next higher ordinal sample space, and by interpolation Expanding the combined result to the next lower ordinal sample space sampling density in each of the sample spaces other than the first sample space, the fractal being obtained as a result of the combination in the first sample space. Method of generating a fractal claims 32 wherein the including step to like. 34. A method of generating a fractal according to claim 33, wherein said combination is additive. 35. A method of generating fractals according to claim 32, wherein said combination is additive. 36. A method of generating a first raster scan video signal in the form of sampling, prior to the first field scan of a series of field scans of said video signal,
One of a plurality of sample spaces, which are sequentially sparsely sampled and are sequentially numbered from the 1st to the nth consecutive ordinal numbers, and are selected from sample positions at periodic positions in each dimension. Prepare a sheet pattern of dots that correspond to different sample positions, prepare a generator pattern before the first field scan in each said sequence of field scans, and spatially define the seed pattern and generator pattern. A convolution integral is performed to obtain a sample-data convolution integral result in the normalized sample space, and a raster scan in each sample space is performed in the normalized sample space during each subsequent field scan. Sampling data Sampling data A selected part of the convolutional integration result is sampled again, and each convolutional integration result is obtained in each ordinal sample space. During each subsequent field scan, interpolation is used to extend the selected portion of the convolution integral result for the higher ordinal sample space to the sampling density of the lower ordinal sample space, and Of selected convolution integration results of different sampling densities, and in response to the expanding and combining step, obtain a combination of these convolution integration results in a raster scan sample space, and calculate the combination of the convolution integration results. Each level
Converting the samples into respective level samples of the first raster scan video signal according to an established scheme. 37. The step of transforming each level sample of a combination of convolutional integration results includes converting each level to a first, second
37. A method as claimed in claim 36, in which each and every third raster scan video signal is converted to a respective level sample. 38. The method of claim 37, wherein the first, second and third video signals are a red video signal, a green video signal and a blue video signal, respectively. 39. A method of generating a composite video signal using a first video signal generated by the steps of the method of claim 36, further comprising synchronizing with a first raster scan signal. Generating at least one further video signal that is raster-scanned by means of time-division multiplexing from the first video signal and the at least one other video signal to generate the composite signal. Method. 40. A time-division multiplexed selecting from said first video signal and said at least one further video signal is at least partially a map stored in a synchronously scanned memory. 40. The method of claim 39, wherein the method is controlled using. 41. Time-divisionally multiplexed selecting from the first video signal and the at least one other video signal is within a range of each of the other video signal portions and the first video signal portion. Priorities are assigned to the portions of the raster-scan video signal of the
40. The method of claim 39, wherein the method comprises the step of generating the composite video signal by selecting a sample of the highest priority assigned among the other video signals and each of the other video signals. 42. A raster scan seed of dots in a first sample space of a plurality of two-dimensional sample spaces sequentially numbered sparsely, which are numbered consecutively from the 1st to the nth. Means for generating a pattern, means for defining a generator pattern placed on an array of categorized pixel positions, and the raster scan seed pattern being categorized in the same manner as the generator pattern is placed. Means for extracting a succession of array of pixel positions for each of the array of generator patterns in the first sample space and each of the classified pixel positions from the raster scan seed pattern in the first sample space. Means for convoluting and integrating a sequence of arrays to obtain a convolution integration result for each sample point in the first sample space, and the first sample In response to at least a portion of the convolution integration result for the interval, the scale of that portion is modified by causing the resampling to be a sampling density of the sample space other than the first sample space for the other sample space. Means for obtaining respective convolutional integration results and attached to each sample space except the first, and by interpolation, expand the function sampled in the space to the sampling density of the sample space having the next lowest ordinal number. Respective means, means for expanding the function sampled in the n-th space from the convolution integral of the n-th sample space, means for extracting a function to be expanded thereafter through interpolation, and the first to In each of the (n-1) th sample space, the convolution integration result in the sample space is sampled through interpolation. In each of said 2nd to (n-1) th sample space in combination with the function expanded to a sampling density in between, said means for expanding the function in said space is then expanded through interpolation, , A respective means for generating a sampled function in the space and for generating the fractal in the first sample space. 43. Having at least one fractal generator as claimed in claim 42 and responding to different amplitudes of the fractals generated by each said at least one fractal generator at least at selected times. And a video signal generator having means for generating different color video signals. 44. Having at least one fractal generator as claimed in claim 42 and responding to different amplitudes of the fractals generated by each said at least one fractal generator at least at selected times. And a video signal generator having means for generating video signals of different intensities. 45. A bit for storing the first fractal component of a plurality of fractal components, each of which is at least three consecutively ordinal numbers, each having successively larger scales, and the fractal component of the smallest relative scale. A map-configured memory and means for performing multiple raster scans of the bit-mapped memory in a time division multiplexed manner during a read cycle to provide a plurality (n) of raster scan read signals;
Means for adjusting the relative delay times of the second to nth memory read signals with each other, and interpolation for expanding each of the second to nth memory read signals with adjusted delay times, Fractal generator in combination with the fractal component of the. 46. Means for adjusting the relative offset for each field scan during multiple raster scans of the memory of the bit map structure for performing fractal animation, and the relative delay time of the memory read signal. 46. A fractal generator according to claim 45, including means for adjusting the delay time again for each field scan. 47. Means for scanning memory locations in the bit-mapped memory during a write cycle, means for producing dots at selected intervals during the scan, and generators for each dot. Patent having means for convolving integration with a pattern to generate a convolution integration result in the form of sampling data, and means for writing the convolution integration result in the form of sampling data in the memory of the bit map structure A fractal generator according to claim 46. 48. Having at least one fractal generator as claimed in claim 46 and responding to different amplitudes of the fractals generated by each said at least one fractal generator at least at selected times. And a video signal generator having means for generating different color video signals. 49. Having at least one fractal generator according to claim 46 and being responsive to different amplitudes of the fractals generated by each said at least one fractal generator at least at selected times. And a video signal generator having means for generating video signals of different intensities. 50. A memory for storing dot intensity information at selected storage locations corresponding to points in a plurality of dimensional spaces,
In each dimension of space, at successively lower spatial frequencies, the memory storage locations are raster-scanned in a time division multiplexed manner,
A means for generating a number of memory output signals of at least 3 having continuous ordinal numbers, and a continuous ordinal number, each for convoluting the generator pattern with a memory output signal of the same ordinal number. Connected to a large number (n
Number) of the convolutional integrator and the convolutional integration result of the first convolutional integrator as a reference, and the phase of the spatial frequency of the convolutional integration result of each of the other second to nth convolutional integrators. Adjusting means and, through interpolation, phase-adjusted convolutional integration results from the second to nth convolutional integrators to the same sampling density as the convolutional integration results from the first convolutional integrator. A fractal generator having means for expanding and combining the expanded convolutional integration results with each other and with the convolutional integration results from the first convolutional integrator to generate a fractal with amplitude variations. 51. Successive field scans comprising means for varying the spatial offset of the raster scan at successively lower spatial frequencies during successive field scans and means for adjusting the phase of the spatial frequency. 51. A fractal generator according to claim 50, configured to generate fractals with animated activity by providing means for making this adjustment between. 52. Having at least one fractal generator according to claim 51 and responding to different amplitudes of the fractals generated by each said at least one fractal generator at least at selected times. And a video signal generator having means for generating different color video signals. 53. Having at least one fractal generator as claimed in claim 51 and responding to different amplitudes of the fractals generated by each said at least one fractal generator at least at selected times. And a video signal generator having means for generating video signals of different intensities. 54. Having at least one fractal generator as claimed in claim 50 and responding to different amplitudes of the fractals generated by each said at least one fractal generator at least at selected times. And a video signal generator having means for generating different color video signals. 55. Having at least one fractal generator as claimed in claim 50 and responding to different amplitudes of the fractals generated by each said at least one fractal generator at least at selected times. And a video signal generator having means for generating video signals of different intensities.