JPH03128583A - Method and apparatus for spatially deforming image - Google Patents

Abstract

PURPOSE: To apply a designated horizontal transformation to already vertically transformed data by controlling a vertical and horizontal transposing memory and a horizontal transformation system. CONSTITUTION: This device is provided with a horizontal and vertical transposing memory 18, vertical transformation system 20, vertical and horizontal transposing memory 22, and horizontal transformation system 24, and a digital Y video output component is generated. A transform composer and factorizer 26 receives an operator input command, and generates different vertical and horizontal transformation information according to this, and this information is respectively transferred to a vertical address generator 28 and a horizontal address generator 30. The vertical and horizontal transformation information is also transferred to an I component processor 13 and a Q component processor 14.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method and apparatus for transforming a data array representing input data values for movement from a source position to a destination position represented in a multidimensional coordinate system. Regarding. The invention also relates to a method and apparatus for spatially transforming an image, particularly with respect to data samples corresponding to pixels of the image, for display on a visual display device such as a cathode ray tube. Furthermore, the present invention relates to an apparatus for performing spatial transformations in a multidimensional coordinate method using a separate transformation for each coordinate of a coordinate system, and more particularly to a two-dimensional transformation in a rask scan television system. The present invention relates to a method and apparatus for spatially transforming an image.

[Prior art]

Methods for performing multidimensional spatial transformations have been developed, such as the Principles by William M. Niemann and Robert F. Souffleur.
Op Interactive Computer Graphics McGraw-Hill Book Company 1979 g2
Edition, Transmission by D.E. Pearson
and Display Op Victorian Information, A Holstate Press Book, 1
975, as well as Ronald Taflier, Siefa Button, and Lawrence Earle.

Rabiner, Proceedings of “A Digital Signal Processing Approach to Interbolation”, I4-E, Volume 61, No. 692
~702 pages, June 1975, etc. However, rotation, perspective display, and
or other transformations, or the transformation process for performing spooling includes multidimensional spatial filtering and interbolation operations. Therefore, the video transformation process required complex and time-consuming processing for each pixel of the transformed video. Therefore, transformation has been impractical due to the high cost of data processing time for complex images, such as for example, scanned television displays. Due to the long required processing time, it has been difficult to substantially process a series of television frames in real time using current technology.

Nevertheless, practical systems for transforming multidimensional visible images are useful for producing special effects when producing television programs, or for converting satellite images of the Earth distorted by the Earth's curvature into flat image displays. There are admirable demands for various purposes such as transforming.

[Summary of the invention]

The system for spatially transforming an image in accordance with the present invention greatly reduces conventional processing time and satisfies this need by sequentially transforming the image separately for each direction of the coordinate system in which the image resides. be. In the case of video, the multidimensional filtering required by complex operations can be performed in real time, one direction at a time, simultaneously with separate sequential transformation operations. In one example, typified by video transformation systems used in real-time television applications, each image component of a rask-scanned video signal passes through a series of processing devices, which performs horizontal and vertical transport. It has a memory, a vertical transformation system, a vertical and horizontal transporting memory, and a horizontal transformation system, and produces as an output a transformed component of the video signal. Each video component of the video signal is operated on separately and in parallel, and this operation is essentially the same, but with some exceptions, such as when one color component has a narrow bandwidth compared to the other color components. The difference is that in some cases, slower and cheaper circuits can be used. The basic principle of dividing an image into unidirectional serial transformations is the same for all image components.

For video television signals, a transformer 7 ohm composer can provide, for example, X, YTh and 2 pretranslations, X, YTh and 2 size controls, X, Y and Z axis rotation angles and A composite three-dimensional affine transformation is generated in response to a command that identifies a subtransformation such as. This three-dimensional composite affine transformation is transformed into a two-dimensional projective transformation by division based on the Z coordinate. The 7 acturizer then decomposes this projective transform into two one-dimensional projective transforms, thereby controlling the two units of the data processing path through the vertical address generator and the horizontal address generator. The factizer generates the required unidirectional vertical transformation characteristics for each vertical column of the display in response to input commands and forwards this information to the vertical address generator. This generator then controls the horizontal and vertical transposer memories and the vertical transformation system to perform the directed video transformation in the vertical direction. Similarly, the factizer also generates the necessary horizontal transformation information, which is forwarded to the horizontal address generator, which controls the vertical and horizontal transposition memories and the horizontal transformation system to transform the already vertically transformed data. Perform horizontal transformation as directed by

〔Example〕

Referring now to FIG. 1, a spatial transformation system 10 in accordance with the present invention operates separately for each direction in dimensionally interdependent spatial transformations, and provides a specific implementation of a standard scan television video signal transformation system. Shown as an example. Transformation system 10 includes three color component processors 12-14, each corresponding to the Y, I$-, and Q color components of a color television video signal. Among others, other methods of displaying television signals can be used, such as red, green, and blue or Y, U, V signals. Color component processors 13 and 14 If
i may be implemented as the same color component processor 12, which is shown in detail in FIG. 1 and described in detail below.

Y component processor 12 receives as input the Y digital video component of the video in rask scan television order and passes it serially to signal processing path 16 . This signal processing path includes a horizontal/vertical transposition memory 18, a vertical transformation system 20, a vertical/horizontal transposition memory 22, a button and horizontal transformation system 24f, and generates a digital Y video output component. This component has been completely transformed in two directions simultaneously - and in one dimension. A transformer 7 ohm composer and factorizer 26 receives operator input commands and responsively generates separate vertical and horizontal transformation information that is applied to a vertical address generator 28 and a horizontal address generator 50, respectively. be transferred. Since the video transformation for each color component is substantially the same, the vertical and horizontal transformation information 4I component processor 15j? and Q component processor 14, and a transformer 7 ohm composer 26 must be provided twice for each color component! ! There isn't.

Timing and control circuit s2 generates basic timing and control signals that are used throughout spatial transformation system 10 in response to input synchronization signals.

Spatial Transformation Theory A procedure for spatially transforming a two-dimensional sample image according to dimensionally interdependent spatial transformations will be described. A common example of spatial transformation is
Translation, construction and expansion, rotation and perspective
It is a projection. However, this concept is very general and includes any strange distortions such as those caused by fisheye lenses or funhouse mirrors.

Mathematically, there are 5 degrees of all points inside the image area.
The image is determined by three position functions that give the brightness of the color components. Here, the original video, that is, the source video is described as follows.

5i (u, v) where i, = 1.2.3 (2)
Here, U and V are independent coordinates applied to the entire image area to indicate the position applied in each coordinate direction, and l is selected as one of the three primary colors. The transformed target image can be viewed as follows.

ti(''*y) (4) However, X and y indicate independent coordinates applied to the entire target image.The spatial transformation is expressed by the following relationship KI
hru. That is, X and y are related to U and V in such a way that the relationship between them is the same.

'i (X,)') = Si (u, Y)
(6) The color separation luminance at each point (x, y) in the target image depends on the luminance at a certain point (U, V) in the source image. For each (x, y), there is only one (u, v) and one should specify or avoid two intensities for the same separation applied to the same point;
Therefore the relationship between them is in the form of each component (x, y)
is a function of

('', v)=f(X+Y) or u=fu(x, y) (8)V
Fukufv (x, Y) Any spatial transformation has its U and V
It can be fully specified by giving the components and fv. These functions simply tell you where to look at the source video and find the separated color intensities of a single point to apply to the destination video. Many spatial transformations can be inverted and are given by Rigi's equation.

(xty) wealth f (u, v) z-ix (u, y) (g) y=f
, (up 1) These functions indicate where to move each source luminance in the destination image. Since the transformation is the same for each separation, the subscripts are omitted and it is actually one group of three. will be explained using one formula. Therefore, t(xty)=s(u,v)=s(fu(xty
) tfv (x, y)) When a transformation is given in the form of the aa expression (g), the relationship in the form of equation (8) is obtained by inverting Kazuzu rl, and the target point is determined by equation (2). Must be able to calculate.

The problem of two-dimensional spatial transformations becomes very complicated when it is realized that many transformations can be factorized into the product of two one-dimensional transformations. This factorization is derived like a rig.

What is sought here is an intermediate image r that looks like a ripple.

t (xty)=ar (upy)-s (upy)
Calculation of Ol can be done by a two-step process.

f (u#Y)=4 (ulg(u,Y)
04t(x,y)=r(fu(x,y),y)
(JfJ However, g(u+y)=v Image r is generated from (rewrite fl)% by moving only in the direction of the secondary coordinates. This is because the primary parameter applied to the equation relating these two is the same. .Similarly r
By moving only in the direction of Fi linear coordinates (rewrite &
) Convert to 1.

Do something like Rigi to find g2.

r(upy)=s(u,v)=s(u,f(x,y)
) and f (X, y) soU For each y, the following 01-dimensional function can be defined.

fu, (x) = fu (x, y) = u
@If this function is invertible, it can be written as follows.

-1 x = f (u) y If this is replaced by f, the following equation is obtained.

1 g (u, y) = v = f (x, y) = f (f (
u), y) 0171v v u
Two important examples of y-space transformations are affine transformations and projective transformations. The affine transformation in two dimensions is given by the following formula.

f (x, y)=a2. x+a22y+a2° In three dimensions, it is given by the following formula.

f, (x, y, z)=a,,x+a,2y+a,,z+
a, 4fv(x, y, z)=a2. x+a22y+a2
3z+a24tW(xe y Hz)=a s, x +
a s2y + a ss z + a sa Generally, it is given by the following formula.

@Affine transformation of dimension N is isomorphic to the N-)-1-dimensional matrix of the form:

Therefore, combining two affine transformations can be computed by taking the product of each of these matrices. Therefore, a general affine transformation can be obtained by a simpler matrix product. Also, the inversion of the transformation is obtained by inverting this matrix.

In order to use a matrix of N vectors X, this matrix is first converted into an N+1 vector CX*t) by adding 1 as the coordinate of its N+1 eye. So matrix Mt-apply to this new vector, M
Obtain a +1-dimensional result. M-, which is not affected by M□
By eliminating the coordinates in the 1-1 dimension, this t-Ng
! Project back in between. As a two-dimensional example, transformation is performed using equation (e). In matrix form, this is a 3x3 matrix.

Converting (X, 7) into three vectors ("*)'*') and applying matrix M eliminates this third equation, leaving ("tV).

If M is invertible, then (xsy) can be expressed as a function of (u, v).

This typically indicates how the transformation is specified. However, in order to calculate this, we need to calculate the individual target coordinates (
xsy) and must find which (u, v) applied to the source video affects the brightness at that location.

Translation, scaling, rotation and shearing are all spatial cases of affine transformations. When these four are performed together, all possible affine transformations can be performed. These matrices and formulas for the two-dimensional case are shown below. This transformation is sequentially described from the source video to the destination video, and we will first show M-1 corresponding to the description. Each source point (u, v) is defined as a vector (Txj 'r
, ) to convert it like Rigi.

The source matrices as a function of the target are: The magnification of the magnifications Sx and S, The clockwise rotation of the angle 0, The rightward shear of the X coordinate of the angle ψ, Among these matrices and their inverse The relationship between each of b is simple. Give a sequence of motions defined by the direction from the source to the target, corresponding to the composite transform from the target to the source. This M can be found by chaining in the reverse order according to the expression % expression % of the substitute si nirigi. For example, if you want to load a source, translate it. This is the product of M-Harigi.

Since this is the determinant M-ml, it can be obtained by direct calculation using cofactors. This same result can be obtained by inverting the inverse matrix.

The five-dimensional affine transformation works in the same way, but X,
The difference is that there are three matrices for rotation around Y> and 2, and three matrices for shear along these axes. Projective transformation is given by the following general formula.

Σ J=l N-1-f, jXj+aN+1. Ni1
- a These transformations are isomorphic for all N1-dimensional square matrix sets. Affine transformations are therefore a special case of projective transformations.

Distance distortion that occurs when a three-dimensional image is projected onto a flat plane using a lens can be expressed by projective transformation. In fact, the analysis of this distortion, called perspective, was the momentum for the generation of the projected configuration.

Projection distortion is extremely familiar to those involved in art, architecture, photography, drafting, computer graphics, etc. Two-dimensional perspective projection of a five-dimensional scene is performed by dividing the X> and Y coordinates of each button point on the original image by their two values, where Z indicates the axial direction of the lens. Therefore, compresses all points on a line through the focal point of the lens into a single point in the field plane.

A two-dimensional projective transformation can be constructed from a five-dimensional affine transformation. This transformation loads, shears, and loads positions across five dimensional spatial coordinates.
It is modeled after an image formed by a camera that captures a flat image that has been scaled and translated. U
.

Start with an image applied to the V plane, and set three spatial coordinates (u
, v, o) and apply the affine transformation of 2〇 to obtain (x', y', z').

By dividing this by t-z', we obtain the equation of rigi.

Since a51u+a52V +a54 and W are 0 in this case, there are no terms "fil 1 "25 and "ss."
, V) and f y −' (u # v ). By inverting and factorizing this transformation, we can obtain the fu required for formula Q4 button and (2).
We want to obtain (x+y) and g(u,y). This factorization procedure is somewhat different from the previous one, since we started with an inverted form. Solving the formula for izuV, directly g(u,
sy) is obtained.

``32F'' ``22 Substituting V into equation (2), solving for U, and slightly transforming it yields the following equation.

(2) Section a5. If $- and ``32'' are 0 and s'' 34 is 1, this projection is reduced to an affine transformation in that plane, yielding the following equations.

X÷a11u+112V+1147=a21u+jj22V+824 A three-dimensional affine transformation from a source array with three-dimensional variables u, vk and wt- to a destination array with five-dimensional variables x, y> and 2 is defined by the following general formula.

X ””111 u + a12 V +a15 W+
1114 @7 ”aHu+a22V+a
25 W+124 (15K”!31
u+a32 v+a3s W+as4 匈This is extremely complicated to solve, so I will omit it here, but it turns out that if you solve for 2〇iu, you can obtain the following equation.

Uyog1 (vew*z) @V, W
Find U for each possible combination of the values of & and 2.
``x'' as a source address and obtaining the data corresponding to each source address, a five-dimensional first-order intermediate data array is established, which has loci svsw> and 2. The desired dimension 2 is now the source dimension U. has been replaced by

Next, by substituting the expression (to) into the expressions ■ and (to) and eliminating U, the result is xmg2 (vs
wsz) ellyko fcv＊”l
Z) (to) Solving the equation for t-V here, we get the following equation.

v=h1(vswsz) (Foundation)w
, yTh, and V for each possible combination of values of 2.
, and use this value as the array address location to determine the primary intermediate V, W.

Obtaining data from the 2nd array, a secondary intermediate data array is established, which has dimensions W, 7 and 2, and whose coordinate points correspond to the addressed locations of the 1st order array □. It has the value of dying.

The final target data matrix with dimensions x, ysp and 2 is obtained by substituting equation (c) into equation (2) and eliminating V. This result is as follows.

X=h2C”eY*engineering) (6)
Solving equation (6) for W gives the following equation w = t
1 (x e Y * ”)
Find the value of W for all possible combinations of values x, yk, and 2, use it as a source address location to pass to a secondary intermediate w, y, z array, and obtain data from the secondary intermediate array; value x.

W for each possible combination of Y> and 2, respectively.

2 to the location specified by yb and 2
This five-dimensional target array T(xayrz) can be established as the values obtained from the next intermediate array.

Description of the Real-Time Video Transformation System The preferred embodiment of the apparatus includes a left-to-right horizontal scan;
and receives separated digital signals of Y, Ik and Q color components of an NT8C color television signal that performs vertical scanning from top to bottom. This signal has 525 scanning lines, uses a 2:1 interlaced scanning method, and has a field frequency of 60 Hz. For each component, each pixel has b8 bits. Y or luminance signal is 1579545MH
It is sampled at four times the NT8C color subcarrier frequency (f, , ) of z. The Ik and Q components are sampled at the subcarrier frequency. The transformation of the Y component will be explained. Ik and Q are treated similarly.

The period for Y data samples (pixels) is 1/(4'sc
), or approximately 70 nanoseconds. In a horizontal scan of 655 microseconds, there are approximately 910 pixels. 486 of 525 scan lines in one frame
The book is the only valid image data; the rest is used during the retrace period.

The samples are arranged in 8-bit parallel and byte series, and this data stream Fi is input and stored in the primary transposing memory as shown in FIG. 1 (□). This memory has three field memory modules, each large enough to hold one valid data field. Successively received image data fields are stored sequentially in three field memory modules, with each input field period having a field memory module containing the oldest data and a buffer storing the currently received fields. The previous two fields are simultaneously read from the other two field memory modules and processed. This arrangement prevents time conflicts that occur when attempting to write new data to a memory that at the time contains portions of previously received fields that have not been processed. Only that data representing the visible image is stored, so that each memory contains 243 rows of 768 data samples. In addition to being used to store fields, the primary function of transposing memory 18 is to change the scanning direction of the fields stored therein. Each field memory can be written to in horizontal order as shown in Figure 2A, but read out vertically as 768 columns of 243 pixels as shown in Figure 2B. The memory, of course, has separate addressable memory locations for storing each data sample. This memory location tItFi is arranged in rectangular coordinates, where the horizontal columns can be considered as rows and the vertical columns as columns, and can be thought of as corresponding to data samples arranged in order. By reading the data samples written in the row direction and read out in the column direction, a digital data stream is generated representing a vertical scan signal of the input data. The horizontal and vertical dimensions of the image can be interchanged by this means. Things that were in the left to right direction in the original video will be from top to bottom 9, and things that were in the top to bottom direction will be from left to right. The output data stream is a horizontal scan of the original image mirrored about its vertical centerline and rotated 90'' counterclockwise about its Z axis as shown in FIGS. 2A-2D. Vertical processing of the input data Fi can thus be done by manipulating the output data by a device capable of performing only transformations along the scanning direction.The original horizontally scanned signal Vertical processing is difficult because the vertically aligned samples are widely separated in time. However, after transposition, the vertically aligned samples are close to each other in time and the horizontal ones are are widely separated.

Referring now to FIG. 5, two 70 nanosecond luminance data streams representing the previous two fields of the current input field are output from the tra/spasing memory 18 and are input to the deinterlayer of the vertical transformation system 20.
Enter it in Sfiltalo 00. Both fields contain information representing the entire video space, but one field is scanned 91/40 seconds faster than the other. Deinterlacing filter 00 combines the two fields to form a new frame, which appears to have been scanned at an intermediate point between the two. This filter effectively operates at twice the original data frequency of 4 f,c. Deinterlacing filter 00 is implemented with two filters in parallel, and the data from these filters is sent as two 70 nanosecond data streams. Throughout the device, data paths, memory modules, and arithmetic sections are provided in parallel to prevent the required data frequency in any single path from exceeding 4 f3c, and to provide the overall high speed required for real-time processing. It still retains many unique frequencies. The device is constructed with commonly available Schottky TTL logic elements, which can respond appropriately to Fi70 nanosecond clocks. Predecimation filter 700 has triple line buffer memories, one memory absorbing the current data column from the dinterlacing filter and the previous column being read from another memory. A third memory stores predetermined intermediate results received from the dinterlace filter. Predecimator 700 provides a twice coarse size change in the scan direction. Each column is processed by the filter multiple.

Each pass through this filter reduces the column length by 172, with a housing that is only one pixel long.

Each pass thus takes half the time and generates half the number of pixels as the last, so the entire ilt! of generated pixels including the original! This is twice the number contained in one column. That is, 1+1/2+1/4+1/8+...=2
It is. Therefore, one redecometer output frequency a is twice its input frequency, and four 70 nanosecond data streams are required to transfer its output to the interbolation-decimation filter 800 of the vertical transformation filter 20. do.

Filter 800Fi has double line buffers, each long enough to contain one column and all its predecimated copies.

This filter has one m-element 1/ between two iii*
64 resolution and can vary its low-pass frequency response point by point over a range suitable to smoothly compress a column to half its normal size. Compression to less than half the size is accomplished by selectively interpolating and filtering one of the predecimated signals received from the predecimator. For example, if it is desired to compress an image to 1/15 of its normal size, select a decimated copy of size Fil/8, which is then interpolated and further processed. 8/15f? ! Shrink this. This number is between 1 and 1/2.

Now, referring to Figure 4, transposing memory,
That is, the frame door 18 has three field buffer sections 50-52, each of which has a field buffer 0. The two multiplexers 1 and 2 are shown as Field No. 1 and Field No. 2.
4.56 is coupled to the memory address and control circuit 5
field/<tufa part 50 according to the selection signal from 8.
to 52 output a byte of video field information. Memory address and control circuit 58 also provides address and control information to each of the eight portions of field controllers 50-52.

The field buffers 50-52 operate in continuous rotation, with one of the five field buffers receiving a field of input data and the other two field buffers each receiving a new field multiplexer 54 or an old field multiplexer. 56 with the newest complete data field and then the oldest complete data field. The frame start signal indicates the start of a frame period, and the pixel clock signal provides the basic tally signal at the input data frequency.

This can be better understood by noting that the rotation and multiplex selection operations of field buffers 50i-52 occur during three consecutive field periods beginning at an arbitrarily selected field time N. After a field period NK, field buffer 0 is selected and has an input byte of video data committed therein, and field buffer 1Fi outputs the oldest field it has through the multiplexer 56 of the old field;
Field buffer 2 outputs the new field through new field multiplexer 54. During the next field period N+1, field buffer 1 becomes the write field buffer, field buffer 2 outputs the old field through old field multiplexer 56, and field buffer 0 outputs the new field through new field multiplexer 54t-. Output the field of.

During the next field period N+2, field buffer 2 becomes a write/read buffer, field buffer 0 outputs the old field through old field multiplexer 56, and field buffer 51 outputs the new field through new field multiplexer 54. Output.

This cycle is repeated in the next field period N+5, and the field period N+3t1 field period N
is the same as Note that for each cycle of three field periods, each field buffer is written to once and then read out through the newer field multiplexer 54 and then read out through the older multiplexer 56. As a result, old field multiplexer 56 always outputs field N-21-, and new field multiplexer 54 always outputs field N-21-.
1, in which case field N is the field currently being written to one of field buffers 50-52. Therefore, it is also new.
The two fields that have been accumulated are successively output to the next stage and updated with each new field period.

Read and write access to field buffers 50-52 is somewhat complicated in that practically available memory chips cannot read and write at a pixel clock frequency of 70 nanoseconds. To achieve the required bandwidth, each field buffer has 32
It consists of 8 x8 memory modules. By sequentially accessing the eight modules, each individual module has eight pixel clock periods to read and write one byte of data corresponding to the sampled pixel location. However, care must be taken in implementing the addressing scheme to ensure that the memory modules are arranged in the proper order for both the horizontal and vertical accesses required to perform the horizontal to vertical conversion.

One advantageous addressing scheme is shown by way of example in FIGS. 5 and 6 for field buffer 50.

FIG. 5 shows the lower addresses of the address map for field buffer 50. The 1-byte memory storage cell portions O through 7 are shown in vertically descending order from top to bottom, with no.
- The hardware memory hood or chip addresses are shown directly above the map in order from left to right. but,
For convenience of addressing, these memory addresses are further divided into row and column addresses, which are shown above the chip addresses in FIG.

Horizontal access in the first row is straightforward. Horizontal access starts at address 0 of module 0 and proceeds through each module in 1b1 order. When address 0 is written to module 7, the column address is incremented and pixel (row, column) position R(at'
) is accessed. 76 in the first row of one field
Eight pixels are written sequentially into the first 96 word locations of the memory module.

It must be recalled that in the case of vertical access, the two pixels located in column 0 and rows 1 and 2 are accessed in sequence. Therefore, these two pixels Fi
Care must be taken to avoid accumulation in sequential memory modules and avoid accumulation in the same memory module.

This corresponds to storing pixel 1.0 in module 1 and resetting its column address to 0 at address 12.
This is done by skipping the food address at 8. Next, this memory module is accessed cyclically again, returning to module 0, and then chip address 1
The food address is incremented to column address 1 corresponding to 29. Similarly, for the second row, we must store the first pixel of the second row in module 2 and continue accessing these modules cyclically until we access module 1 and then increment its word address. . The starting module for the first pixel in a row is 8
The same steps continue until all three modules have received the first pixel of a row. The process then cycles and module O receives the first pixel of row 8.

When accessing the 7 frames vertically, each module is again accessed in sequence, with the row address incrementing for each pixel.

At the beginning of each new column, the row address returns to 0,
The column address increments to one. Pixel 0°0 occurs at row 0, column 0, module 0, pixel X'eo occurs at row 1, column 0, module 1, and pixel 2,0 occurs at row 2, column 0, module 0. I understand. This addressing device therefore satisfies the condition that each part of the frame buffer can be accessed sequentially for both vertical and horizontal accesses.

An advantageous implementation of this addressing scheme is shown in FIG. 6, where frame buffer 50 has eight 52K.times.8 memory modules, designated as modules 0-7. Each module has a corresponding data latch and address latch.

Lower address bits O to 4F17 bit string counter 70
The upper eight address bits 7-14 are provided by an 8-bit row counter 72.

Row counter 72 is reset at the beginning of each field;
Steps are made at each pixel in vertical mode and at the beginning of a row in horizontal mode. Column counter 72 is reset to 0 at the beginning of a field, and in horizontal mode, at the beginning of a row;
The bit counter 74 advances in accordance with the maximum count output.

Counter 74 is coupled to reset at the beginning of the field and operates synchronously with the pixel clock signal. The count enable input of counter 74 is enabled continuously in horizontal access mode and at the beginning of a column in vertical mode. Therefore, column counter 70 increments every eighth pixel clock in horizontal mode, and every eighth column in vertical mode.

The selection of 32Kxa modules 0-7 is controlled by a 3-bit counter 80, a 5-bit counter 82, and a 3-8 module selection decoder 84. A three-bit counter 82 increments at the pixel clock frequency and controls sequential access of the individual memory modules. The output of counter 82 is decoded by decoder 84, which sequentially selects one of the eight modules and simultaneously loads the data and address latches for the selected module. A 3-bit counter 80 provides the required module offset, staggered at the beginning of the fold or row.

The counter is reset at the beginning of the soq field and increments at the beginning of a row in horizontal mode and at the beginning of a column in vertical mode. The 3-bit counter 82 has the beginning of the row fc.
is loaded with the contents of the 3-bit counter 80 immediately before incrementing at the beginning of the column.

In particular, addressing of field buffers 50-52 will be explained for vertical mode access and horizontal mode access. In many cases, these field buffers are accessed in horizontal mode for writes and in vertical mode for subsequent writes to effect transposition.

However, in some cases, the field buffer may be accessed in horizontal mode for both reading and writing. Since it is not possible to perform transposition on the frame door 18 that is combined with the transposition on the frame door 22 (FIG. 1), the image is 90°
Effectively give rotijohn. As the image is rotated 90 degrees, it is effectively converted to Ofi scanlines and loses resolution. However, the resolution of the image is determined by transposing the image to only one of the frames doors 18 and 22 and then giving a negative rotation between 0 and 45 degrees to achieve the desired rotation angle and frames door 18. By compensating for the difference between the 90° rotation and the 90° rotation caused by the inability to perform the transposition, a large angle rotation can be maintained well.

g I Figure o Transposing frame store 22
is implemented in a manner substantially similar to framesdoor 1B, except that framesdoor 22 requires only two field buffers. One field of data is written vertically into one buffer, and the previously written field is read vertically from the other buffer.

The two buffers are then interchangeable, so that when one buffer is read horizontally, the other buffer is written vertically.

The deinterlacing filter 00 of FIG. 5 is shown in FIGS. 7A, 3, and 7B. The filter 600 includes a 3-stage shift register 602 with a 2-byte ring, and a filter section 604, k
and multiplexers 606 and 608. The even and odd line data from the transposing field puffers 50-52 are clocked out through a shift register 602 at the pixel frequency. This shift register has RO to OsO4, and the number of each stage is the scanning order of the vertical interlaced scan data from the transposing frame store 1B. For simplicity, the connection 1fc
Although not clearly shown, the purpose of the shift register 602 is to allow the filter 604 to utilize the contents of each stage RO to R5. Multiplexers 606 and 608 respond to the vertical scanning signal to select odd and even button outputs, respectively, from filter 604 when data is output from frame door 1B in vertical scanning order. When the data is output in horizontal scan order, multiplexer 608 selects the output of register stage R2 to drive the even byte data stream, and multiplexer 606 selects the output of register stage FL3 to drive the odd data byte stream. . For horizontal accesses of the 7 frame store 18, a similar deinterlace filter following the vertical to horizontal transposing frame store performs deinterlace filtering.

The filter 604 also has substantially the same portions for the even and odd data streams, each i;i-1/8°2/8
, 6/8, 2/8 and 1/8 filtering functions. The two odd and even portions of filter 604 are connected to two-fold multipliers 410 and 4, respectively, as shown in FIG. 7B.
11.4x multiplier 612.4 adders 614-61
7. One subtractor 618. and 1/4 divider 620
can be advantageously configured. Since the multipliers and dividers can be implemented as powers of two, they can be easily implemented by simply shifting the relative positions of the data bit lines of the input and output data streams. The inputs of the filters for the even and odd data streams are represented by the information shown in the even and odd columns of the table for the output of shift register 602 in FIG. 7B.

Each element to be applied to this table is one in the shift register 602.
Two shift register stages are shown, the outputs of which are connected to the filter inputs as shown.

Referring now to FIG. 8, predecimator 700 has five line buffers, designated as line buffer 0 through line buffer 4, each having a 2567-do
It has a storage capacity of 2 pits. line buffer o-sB
Two 8-bit data at-receive from respective multiplexers 702-705. multiplexer 70
Each of 2-705 can select one of the four input signals and pass the selected input signal t->< onto one of the eight-pit buses to its corresponding line buffer. In one mode of operation, the two 8-bit path inputs of the line buffer are driven in parallel. Multiplexers 702-705 therefore select two of the four input byte streams.
It must be possible to select one of the four input byte streams or one of the four input byte streams depending on the mode of operation. Line buffer 4 receives two 8-bit data streams t- as even and odd outputs from filter 708.

A 32-bit wide 5-to-1 multiplexer 710 generates a 32-bit output that is divided into four 8-bit data streams and transferred to a 4-byte wide 5-stage shift register 712. Loads the data into the line buffer in such an order that, when read, the shift register 712012 bytes can be filled with serial pixel information for one scan line.

That is, each register stage of the shift register 712 stores information for one pixel, and this pixel information is stored in registers RO to B, 1.
They are arranged in the order of rask scans indicated by numbers 10. Registers R, 8-R11 not only provide data outputs to the next stage of the transformation system, but also provide data outputs to the second stage of shift registers including registers 114-R7t. The purpose of the shift register 7120 is to filter 12 bytes of serial pixel information in a predetermined order.
8. Although not explicitly shown for simplicity, the outputs of the registers RO to R11 are transferred to the respective output Fi filters 70&.

Filter 708 actually has two separate parallel-operating filters. One of these filters generates even pixel data at the pixel frequency and the other generates odd pixel data at the pixel frequency. The even and odd output cuffs 16.718 therefore produce combined feedback data at twice the pixel frequency. The deactivation signal is used to drive the output deactivation input of multiplexer 710 and load shift register 712 with a zero at the end of processing a scan line. This loading of 0 causes the filter 7 to load at the end of the scan line.
Full compositing by 0.8K is performed to ensure that information from the end of a scan line does not affect the information applied at the beginning of the next scan line. Six extra lock signals are generated each time the end of each scan line passes through filter 708 before the next scan line's data is input through multiplexer 71G, and is used to control the pipeline of the predecimator system, and in particular shift register 712. to restore.

The line pack 70 is designed to operate in various operating modes.
Although the wide distribution of the four scan line signals accumulated by ~4 makes predecimator 700 seem complicated, its operation is actually quite simple. In a normal mode of operation, vertical scan line information from corresponding vertical scan lines of a pair of sequential fields is received from even and odd input lines and gated into line buffer 0. These even and odd input lines represent data from a series of fields, each carrying alternating pixels of a frame. That is, for a given scanline column, pixel information for rows 0 and 1 appears on the even and odd buses, respectively, then pixel information for columns 2 and 5 appears on the even and odd buses, respectively, and then pixel information for columns 4 and 5 appear on the even and odd buses, respectively. The pixel information of 5 and 5 appears on the even and odd buses, and so on. multiplexer 702
connects the upper output stream 720 to the even input bus and simultaneously connects the output stream 722 to the odd input bus. The first, or column 0, pixel information is provided to byte position 0 of the input da-ranch by gating line buffer 0 through the input latch, and the pixel information of column 1 of bus 722 is gated to byte position 1 of the input da-launch. be done. On the next pixel clock period, the pixel information for frame column 2 appearing on bus 720 is gated into the input data latch at position ta12, and the pixel information for frame column 3 appearing on bus 722 is gated into the input data latch at position tjIt3. Ru. The first four pixel bytes are thus input to the data latch sequentially in scan order at the end of the two pixel clock times.
This data is stored in address word position 0.
I admire you. Input data puffer 2 is 3rd and 7th
Column position 4 ~ at 1ii1i prime clock time of %4
7 #J cumulative information is loaded, address 2)' position f &
It is accumulated to 1. Therefore, as we will see, the vertical scan columns from a pair of sequential fields are deinterlaced and stored in the line buffer O in raster scan order during a vertical line scan period, which scan period is a scan time N. shown, giving one frame of reference.

During this same vertical scan time, at the same time that a frame scan line is written to buffer O, the previously written vertical scan line information is simultaneously read out from the four bytes of line buffer 2 and is transferred to a 5-to-1 multiplexer. The signal is output through 71-0 to the first stage of a shift register 712 consisting of registers R8 to R11. The next four byte foods are read from line buffer 2 and shifted through shift register 712 each pixel clock time. The data read from line buffer 2 and shifted through shift register 712 includes a 4-byte parallel data stream, and the effective bandwidth of this data transfer operation is four times the pixel frequency. The filter 708 responds to the data contents of the individual byte registers RO to R11 to be applied to the shift register 712,
Two bytes of data represented by even and odd numbers are output to pass lines 716 and 718 at the pixel frequency. Input scan line information of line buffer 0 and filter 708
The even and odd output information of contains two bytes each in parallel, and the information 1l read from line buffer 2
Containing t4 bytes in parallel, the line buffer output information has twice the effective bandwidth of the other two data streams.

Line buffer 4Fi is gated to provide alternating bytes to its input data latch from the even and odd data streams from filter 70B, as well as gate even and odd seven-frame data to line buffer 0.

Therefore, when a 4-byte sequence of input pixel information is loaded into line buffer 0, a filtered 4-byte sequence of information from filter 708 is loaded into line buffer 4. Half of the pixels of the input vertical scanning line are line buffer 0
At the point when the scan line cycle is loaded and the button is pressed,
Half of the scan line corresponding to the pixel information from filter 708 will be loaded into line buffer 4. This is because the bandwidths of the two data stream inputs of line buffer 0 and line buffer 4 are the same, ie twice the pixel frequency. However, line buffers 0 and 4 are loaded at twice the pixel frequency, and line buffer 2Fi outputs at four times the pixel frequency, so when half the scan line's pixel information is loaded into line buffers 0 and 4, Complete pixel information for one scanning line is stored in the shift register 71.
2t- will be passed and processed by filter 708. Therefore, half a scan line of data stored in line buffer 4 represents a 2:1 compression ratio, which means that by processing one complete scan line of information, one half scan line of information is stored. To become.

Note that during the first half of the scan line period, uncompressed pixel information is transferred through shift register 712 and provided to the circuitry in the lower path, thereby providing shift register stages R8 to R8.
It can be used by the output of R11. Therefore, even if two-to-one data compression is performed, the original data is stored and retained for further use by circuits in the path below. 1/4 of scanning line period
(time 1/2 to 3/4), line buffer 0 receives pixels of video input information in scan line order;
Line buffers 2 and 4 are exchanged. This 2:1 compressed data is read out from the 2-in-buffer 4 at four times the pixel clock frequency, passed through the shift register 712, sent to the filter 708, compressed, and written to the line buffer 2. The 2:1 compressed data is read from the line buffer 4 and transferred to the shift register 71.
2, it is also stored by the lower path circuitry through the data outputs of registers R8-R11 and is available for later use. At the end of 3/4 of the vertical scan line period, a scan line of 4:1 compressed data is loaded into line buffer 2. In the next 1/8 of one scanning line period, data compressed at 4:1 is read from line buffer 2, and then data compressed at 8:1 is stored in line buffer 4. . This process of alternately accumulating and sequentially doubling line buffers 2 and 4 continues until the end of the vertical scan line period, when a complete vertical frame line is loaded into buffer 0 and filter 708 The scan line circulating through the image is compressed into a single pixel or byte.

This bridecimate processing therefore provides the lower path circuit with a selection of one scan line information, which is processed by sophisticated filtering and has a compression ratio of 2. This bridecimate process can thus do much of the work that would otherwise be done by the vertical transformation circuitry, providing an improved final fully transformed image to the data transformation system. data resolution.

For example, if a compression ratio of 17:1 is required, the transformation system selects from the predecimated data that has a compression ratio of 16:1, and then selects the very small amount needed to increase this ratio to 17:1. Only additional compression needs to be performed.

At the end of vertical scanning line period N, a new vertical scanning line period N+1
Beginning, multiplexer 704 gates the field data for the next pair of even and odd vertical scan lines into 2-in buffer 2 in the same order that the previous scan line was written to line buffer 0. At the same time, the exchange of 7 rip 70 tb data begins between 2 in-buffer O and 2 in-buffer 4, and the scanning line data is pre-decimated.
Data stored in line buffer 2 is sequentially compressed by a factor of 2 as the scan line data circulates through shift register 712 and filter 08 as previously done during vertical scan line periods NK&. In the next vertical scanning line period N+2, this cycle is repeated,
The input scanline pixel data stream is loaded into line buffer 0 and the contents of 2 in part, 2 are predecimated.

In operating modes where data is received on the even and odd input buses in horizontal scan line order rather than vertical scan line order,
The datapacking process must be a little different. This is because each even and odd input carries its own complete series of pixel lower information rather than alternating pixel position information as in the case of interlaced vertical scan line information. Complete even column data is on the even lines, complete odd column data is on the odd lines. In this mode of operation, multiplexers 702 and 705 operate to select and gate even and odd input horizontal data streams into 2 in-buffer 0 and line buffer 1, respectively. Multiplexer 702 alternately routes the even 2-in input data stream to upper path 720 and lower path 72.
2 and input pixels in line buffer 0 in scan order.
4-byte input data buffer. Similarly, multiplexer 705 may operate to alternately gate input odd horizontal scan line information to upper pass line 724 and lower pass line 726 to load the odd horizontal scan line information into line buffer 1 in scan order. .

Each of line buffers 0 and 1 is now loaded at the pixel frequency rather than twice the pixel frequency in the vertical scan mode of operation, and the overall input data frequency is pixel because the two line buffers are used in parallel instead of one. Stays at twice the frequency. As the horizontal scan time interval progresses, previously loaded data is read out from line buffer 2 at four times the pixel frequency and passed through shift register 712 and filter 708 into line buffer 4 with a compression ratio of 2:1. Accumulated. This data is read from line buffer 2 at four times the frequency at which data is written to each of line buffers 0 and 1, so 1/4 of the data for one line is stored in each of line buffers 0 and 1. One complete scan line of data is read out from the line buffer 2 and filtered by the filter 70.
Pass 8.

The original contents of line buffer 2 are fully predecimated by the time line buffers 0 and 1 are each loaded with half a line of information. In the second half of the horizontal scan line time interval, the already written contents of line buffer 5 are predecimated. In the next horizontal scanning line period, horizontal scanning line information is sequentially written to line buffer 2 and line buffer 3 for even and odd scanning line column information, respectively, and the contents of line buffer 0 that have already been accumulated are used for that scanning line period. The first half is pre-decimated, and the already accumulated contents of line buffer 1 are pre-decimated in the second half of the scan line period. Clearly, therefore, this predecimation process is substantially the same for vertical and horizontal scanning. However, the input data buffer is somewhat more specific, resulting in a difference between interlaced and non-interlaced input video data streams.

Filter 708 has two parallel filters, which are -
1/16 y Op 5/16 t 1/2
t 5 / 16 * Osl /' 16 filter functions, and these input connections are connected to the shift register 7.
They are the same except for the points in 12.

A highly advantageous embodiment of filter 708 is shown in FIG. 9 and will be described. Although only one filter 708 is shown, it can be seen that dual even and odd filters are used to connect their inputs to the inputs of that filter to each of the even and odd registers shown. Obviously, this filter is conveniently implemented with four adders 730-753 and a single subtractor 734.

Although no actual multiplication or addition is required, this is done by the multiply block 736 button and 737, as well as the divide block 758.
is realized as a power of 2, and these operations can be performed simply by shifting the relative bit positions of input/output data information. Due to the lack of actual multiply and divide operations, filter 708 can be implemented very economically like a conventional 7-point filter;
It can operate at nanosecond pixel clock frequencies.

Interbolation decimation filter 8001 shown in FIG. 3! ? and 906 are basically the same, and are representatively illustrated in an interbolation decimation filter 800 as shown in FIG. 10, which will now be described. Filter 800 provides the final functional relationship between source or input video data and target data in the vertical dimension.

A vertical source address generator 912 (FIG. 5) calculates a vertical pixel source address sequence corresponding to an output target video data sequence in response to a vertical target address counter 914 and a transform combiner/factorizer 916, and performs interbolation. Decimation filter 80
Supply to 0. The addresses provided by vertical source address generator 912 have a resolution of 1/64 pixel;
Contains a 4-bit scaling parameter between 0 (for 1/i, 99 sized or such large images) and 15 (for predetermined data compressed to 215 or more). Interbolation decimation filter 800 provides video data values computed from the four uhi tree locations that appear on either side of the source address. 16 to calculate the value of this output video data.
filter functions are available. One is selected according to a 4-bit parameter, alpha, according to the desired compression ratio provided by the interbolation decimation filter 800 in addition to the selected predecimation compression.

2 line double buffer 809 has 8 segments 80
R8 to R8 of the predecimator 700 (Figures 3 and 8)
Received from R11 data output. For each vertical scan line of a frame, the received data includes one complete line of video data plus all predecimated copies of that complete line, which copies the second complete line of video data. Occupies line data. Therefore, two lines of data need to be stored in each half of double packer 809.

This double buffering allows two new lines of video data to be received, and the previous two lines of data are manipulated to provide one line of video data for the target image.

When the double buffer 809 receives video data, the first four bytes are divided into four segments 801 to 804, respectively.
The first four bytes are stored in each of the four segments 805-808, the third four bytes are stored in each of the four segments 801-804, and so on. Like this double person cover 77801-8
By dividing 08 into eight parts, four adjacent pixel locations on each side of the address point (a total of 8
) can be reliably read out in parallel from the double cover 7a.

Kahatsu 77809-8 with double barrel shifter 810
Bytes of pixel data are received, this data is circulated to a desired position according to the last three bits of the non-mantissa part of the source address, and the calculated video data is transferred to segments 821 to 821.
828 to an eight segment multiplier 820 with 828. This data is circulated such that the pixel data corresponding to the non-mantissa portion of the source address is provided to the central multiplication segment 824. Pixel data for three pixels is provided substantially to the left in segments 823, 822, and 821, and pixel data for four pixels is provided in segments 825-828, respectively, to the right. Thus, eight multiplication segments 821-828 receive as initial inputs 8 bits of video data for each of eight sequential pixel locations centered on its source address point.

Multiplication segments 821-828 each receive an 8-bit coefficient, or weighting function, from a 6-segment coefficient memory 830 having segments 851-858 as inputs @2. Each segment is 1024 bits each
Constructed as a hood.

Coefficient memory 83G receives the 6-bit mantissa portion of the source pixel address as a partial address. These 6 bits give the phase factor φ, which is 1/1 of the source address.
Define one of 64 sub-vixel points for 64 pixel resolution. A filter function can thus be centered on this sub-vixel source address, and the pixel data is weighted according to its position on the filter function curve for the sub-vixel address.

Coefficient memory 850 further receives a 4-bit address in accordance with the scaling factor related parameter, alpha, output by intervolator decimation filter 800. Therefore, coefficient memory 850 can have 16 different filter functions for each of the 64 sub-vixel source addresses. Therefore, this filter function C, interpolation decimation filter 8
The magnification (compression) degree given by 00, the mag factor, can be designed.

For example, if the output destination image is at least as large as the selected original or gridimated copy of the source image, it may be desirable to use a filter function that deeply weights the video data at pixel locations closest to the source address. There is. On the other hand, 1
If compression close to /2 is desired, a filter function that gives at least some weight to all eight pixel locations near the source address is desirable. th, predecimator 700 performs virtually all 1/2 compression, so any further compression performed by interbolation decimation filter 800 will always be by a factor greater than 1/2.

Addressing circuitry is represented by segments 841, which correspond to each of the eight double buffered memory segments 80.
One of eight segments giving address inputs 1-808. Address segment 841 includes adder 851, multiplier 7 actor ROM a 61 and carry RO
M 871.

Adder 851 receives as a first input the non-mantissa portion of the source address divided by eight. This division by 8 is of course performed by simply shifting the last five digits of the integer part of the source address. The 4-bit mag factor parameter is an RO that generates address shifts according to the scaling factor.
Provided as address input of M861. If the destination image is half the size of the source image, the mag factor is 0.
A full-size copy of the source image is output to barrel shifter 810. 1/4 and 1 of the size of the source image
For the target image compressed between /2, ROMa6
1 converts the source address to a half-size predecimated copy of the source image, and so on.

The carry ROM 871 receives the lower three bits of the exponent part of the source address, and when the lower three bits indicate a number from 4 to 7, it generates a carry output and stores the converted backup memory 809. make progress. By this selective step, the desired eight pixels are transferred to the backup memory 80901.
Generates a position that intersects two word boundaries. Among them, the addresses of segments 806 to 808 must be selectively decreased because increasing them would be dangerous.

For example, if the source address of a full-size destination image is 25
-(binary value 00011001.0.00101) and 4. Therefore, the pixel address input to the adder 851 divided by 8 becomes 3 (binary value 00011). MAG7Actor=0 specifies a full size image, and the output of the ROM 861 to the adder 851 becomes 0. For a given address, the backup memory 809 is located at pixel location 22~
It is desirable to read out 29 video data. pixel 24
~29 data is stored in word location 3, buffer segments 801-806, and pixel location 2
Data of 2 and 23 are stored in buffer segment 8, respectively.
Stored in word location 2 at 07 and 808. Therefore, carry ROM871 is 1 (binary 001)
buffer address word S is provided to segment 801 by adder 851. Similarly, segments 802-806 receive address word 3 from their respective address circuit segments 841, and segments 807 and 808 receive decremented address word 2.

The pixel data (pixel 25) defined by the exponent part of the source address is output from segment 802 and is
digit address pick) (barrel shifter 8 according to 0(1)
10 cycles down two places (as shown) and provides the data for the designated source pixel to multiplier segment 824 . Therefore, coefficient memory 830 can be programmed so that eight pixels of video data for one source point are always applied in sequence to multiplication segments 821-82B. The same effect can be achieved by eliminating barrel shifter 810 and adding three address inputs to coefficient memory 830, with each segment programmed separately to yield eight possible locations where the data for a given source pixel occurs. can do.

Therefore, multipliers 821-828 of arithmetic circuit 812 receive 8-pixel video data from barrel shifter 810, multiply these pixels by appropriate coefficient 7 actors from segments 831-838 of coefficient memory 850, and send the result to the adder circuit. Output to 881-887. This adder circuit sums these eight products to generate video data for the pixel corresponding to the input source address. The output pixel data stream from the interbolation decimation filter 800 is fully processed in the vertical dimension and then provided to a vertical and horizontal transposition memo + 7900 (Figure 3) to separate the horizontal dimension from processing in the vertical dimension. Start processing to apply.

Referring now to FIG. 3, an interbolation decimation filter 800 receives a vertical scan line of a source image. Even when this video data is read out horizontally from the horizontal/vertical transposition memory 18, this video data is still treated as a vertical scan. The net result is a 90° rotation and mirror operation, which transform combiner factorizer 9
16.

Recall that X and y are used to identify the pixel location to be applied to the destination or output image, and U& and V are used to identify the pixel location to be applied to the source image. In the interbolation decimation filter 800, each vertical scan line corresponds to a constant value of U, which starts at 0 and increases with each sequential vertical scan line, moving from left to right.

For each vertical scan line, interbolation decimation filter 800 receives a V address input sequence from vertical source address generator 912, which generates a sequence of pixel addresses to be applied to one scan line of the sequence of video data pixels. It is something that specifies. The interbolation decimation filter 800 has V
It responds to each received V address by outputting a pixel of video data as a function of the pixel located at the dot.

2 defines V as a function of U and y and defines a number of constants from the raJ matrix (Table 1 below) that defines the desired relationship between the destination and source images. During each vertical retrace period between fields, the transform convoser/factorizer 916 calculates the necessary matrix constants in response to operator input commands and provides them to the vertical address generator 912. Vertical address generator 9
12 itself calculates uh and y by actually starting at 0 for the first pixel of the first scan line, increasing y for each successive pixel, and increasing U for each successive vertical scan line. The term is generated.

Similarly, for the horizontal dimension, the horizontal address generator 908 receives the appropriate raJ matrix constant from the transform convoser factizer 916 and
and y for each horizontal scan line. In practice, X and y are obtained by starting at 0,0 for the first pixel of each field, increasing X for each pixel, and increasing y for each horizontal scan line.

Of course, the vertical and horizontal addresses v> and U could be generated by a microprocessor from the formulas therefor, but this would be very difficult to do at a pixel frequency of 70 nanoseconds. Vertical source address generator 912
The horizontal source address generator 908 is a dedicated circuit that calculates Vi and the U equation 30°31 at the pixel frequency.

It should be noted that since no interlaced scanning is performed, the video data enters the interpolation decimation filter 800 at twice the pixel frequency and passes through the remainder of the system at the pixel frequency. Vertical and horizontal source addresses therefore occur only at the pixel frequency,
It does not occur at twice the pixel frequency.

Referring now to FIG. 11, the vertical source address generator 912 includes a numerator calculation circuit 915, a denominator calculation circuit 916, a divider circuit 918 that divides the numerator by the denominator, and various timings used throughout the vertical source address generator 912. It has a timing control circuit 920 that generates a control signal.

Previous V register 924 receives and buffers each vertical address V. Subtractor 926 subtracts the previous stored V address from the current shift, address and outputs 18 on signal path 928.
Generate bit difference parameters. The most significant bit of the 18-bit difference parameter is the sign bit, and the six least significant bits represent the mantissa portion. This difference parameter is V
is used as the value of the derivative of .

The mag factor ROM 930 receives the exponent part of the difference parameter and outputs the term of the mag factor as the base 2 exponent part of the exponent of the absolute value of the difference parameter. Mag factor is 0~
For difference parameters of 199, set to 0; for difference parameters of 2.00 to 599, set to 1; for difference parameters of 4.00 to 7.
For a difference parameter of 99, it is equal to 2, and so on.

Consider only the absolute value. The mag factor instructs the interbolation decimation filter 800 to use the particular predecimated copy and is forwarded to the barrel shifter 934. This shifter shifts (divides) the vertical source address by a number of pit positions equal to MAG7 actors to generate an adjusted source address.

If the predecimated copy of one line of data is chosen to have a given 2x compression ratio, the source address must be divided by the same 2 for compatibility, and the barrel shifter 934 perform a function.

The difference parameter is the reciprocal of the magnification of the destination image relative to the source image. For example, a double-size target image yields a difference parameter of α5, and a half-size target image generates a difference parameter of 2.0.
The difference parameters are generated, and this process is repeated below. This difference parameter is therefore a measure of the magnification (including compression) of the destination image relative to the source image. Barrel shifter 936 receives the difference bacmeter and shifts it toward the lower bit positions by the number of pit positions indicated by the parameter magfactor, producing an intabolator difference signal on signal path 938. This represents the expansion (reduction) that must be performed by the interbolation decimation filter 800 over and above that performed by the predecimated copy selected by the parameter magfactor.

Alpha ROM952 difference between parameter intervolator
This ROM operates to generate a 4-bit parameter alpha, which is 16
one of the filter functions is selected for use by the interbolation decimation filter 800. In order to improve the quality of the target image, it is desirable to use different filter functions with different scaling factors (reduction factors) of the target image by means of an interbolation decimation filter. The P wave of the predecimated copy is performed by a predecimation filter 700 and an interbolation decimation filter 8.
The only problem in this respect is that 00 causes a P wave.

For example, if the target image is full size or so large, a narrow filter function with high peaks should be used. This places greater weight on source pixels that are closest to the vertical source address point. If the target image is compressed very heavily, the filter function will become flat and wide.

Therefore, the pixels closest to the source address point have less weight, and the pixels farther from the source address point have more weight.

The interbolation decimation filter 800 performs any degree of video enlargement, but the maximum compression rate is t99.
It is. Any additional compression ratio can be obtained by selecting a small predecimated copy. For example, compressing the target video by 1/16 can be achieved by selecting the fourth predecimated copy (mag factor equal to 4) and by introducing a compression ratio of interbolation decimation filter 800iC1. (no more compression) can be done. The mag factor term is 4, the difference parameter is 16, and the intavolator difference parameter is 1.

To compress the original image to 1732, select the fifth predecimated copy, set the mag factor to 5, the difference parameter to 32, and the intabolator difference parameter to 1. To compress the original image to 1/15.4, select the third predecimated copy, set the mag7 actor to 3, and set the difference parameter to 15.4 (
1111011001 ) in binary, and the intavolator difference parameter is 192 (t111011 in binary).

The exponent portion of the intervolator difference parameter on signal path 938 has a maximum value of 1, and its mantissa portion has a precision of 6 bits. Therefore, the interbolation difference parameter has 7 bits, and the Alpha RIOM932 has 128X
It can have a size of 4. Since a single filter function is adequate for all degrees of image enlargement, full size and slight reduction, we divide the range of the interbolation difference parameter between too and 199 into 16 equal parts and apply the difference to each part. It is desirable to match the alpha parameter and the corresponding filter function 1:1.

Therefore, it is loaded into alpha ROM932, and 0 for addresses 0 to 104 (binary t000011).
, the input address toOS~109 (binary toooo1o
.

to 1000110), input address 1
10~114 (binary 1000111~t(11N]0
For 1), output 2, and input addresses 191 to 19? (Binary 1111010~111
1111), repeat this until 15 is output.

Thus, a different filter function can be provided for each of the 16 values of alpha ranging from a narrow and steep alpha equal to 0 to a wide and flat alpha equal to 15. Therefore, the same filter function is used for a very large group of full size images, scaled images) and scaled down images.

The vertical source address generator 912 has a numerator circuit 915, a denominator circuit 917, a k and a divider circuit 918, which divides the output of the numerator circuit 915 by the output of the denominator circuit 917, and then calculates the quotient. After denormalization, the vertical address V is output to the barrel shifter 934. Timing control circuit 920 is responsive to commands received from vertical target address counter 914 on signal path 940 indicating that the end of the frame time interval is not the end of the frame time interval and is received on transfer path 942 from transform deposer/factorizer 916. Display information and vertical source address generator 91
Generates various timing control signals used throughout 2. The actual circuit of the source address generator is shown in a simplified form for ease of explanation. For example multiplexers 944, 946 and 948
can be realized by selectively gating 3-state logic circuits, as well as in separate integrated circuits called multiplexers, which simultaneously store 32-bit (4-byte) data registers 950, 951, 952, one byte at a time.
,955,954. and 955 sequentially. In this case, transfer bus 942 includes, for example, an 8-bit data bus from an 8-bit microprocessor.

Data register 956 can also be implemented as a 32-bit register (1), and bias data register 957 can be implemented as an 8-bit register.

Recall that the vertical source address generator 12 solves the equation ω to achieve the vertical source address at the pixel frequency. During each vertical retrace interval, the transform composer 7 actuator 916 transfers the contents of Equation 30 to the register of the corresponding vertical source address generator 912 on path 94.
Load through 2. For example, the molecular constant “311”
341"21" and "24" are loaded into 32 bit registers 950.951, 952 and 953, respectively.

Timing control circuit 920 forces the select high inputs of multiplexers 944 and 946 to logic 0 during this time interval and transfers this data to the inputs of registers 951 and 953. The select large input is then set to logic 1, register 951 receives data from 32-bit adder 960 through the A input of multiplexer 944, and register 953 receives data from 32-bit adder 962 through multiplexer 944.
Receives data through the 460A input.

Similarly, on vertical retrace, a vertical constant "52" is loaded into a 32-bit register 954, and a constant "22" is loaded into a 32-bit register 955 through the B input of multiplexer 948. The select large input of multiplexer 948 is then set to logic 1, and 32-bit adder 964
Data can be transferred from the A input of multiplexer 948 to the data register 9550 input.

The adder 960 has 5 registers 950 and 95 registers.
It can be seen that inputs are received from the outputs of 1 and the sum of these inputs is provided to the main input of multiplexer 944. Similarly, adder 962 adds the output of register 952 to the output of register 953.

Further, the molecule circuit 915 has an adder 966, which adds the output of the register 951 to the output of the register 956, and
The sum is returned to the input of register 956.

The subtraction circuit 968 outputs the output of the register 956 to the register 95.
3 to produce a difference signal that is the solution of the numerator of equation (to), which is provided to divider circuit 918. The adder circuit 964 sends the output of the 32 register 954 to the register 95.
Add to the output of 5. The output of register 955 is the solution to the denominator of equation 30, and is also provided to divider circuit 918.

One frame of the reference pixel time interval is at the vertical address v(
defined as a function of u and y corresponding to u, y),
The data at the pixel address provided at the output of the numerator circuit 915 and the output of the denominator circuit 917 becomes valid upon the occurrence of the corresponding pixel clock transition. For example, pixel clock time t. ,. Vertical source address V.

,.

The data of the pixel corresponding to v2,2 is valid, and the data of the pixel source address v2,2 is valid at pixel clock time 2,2, and so on.

It can be seen that in the vertical source address generator 912, a vertical address is determined for pixel location y of the target image, and a vertical address is determined for pixel location U of the initial image.

During the vertical retrace period, register 956 is cleared and other registers are loaded with constants. Looking at the expression (to),
First pixel clock time t. ,. It can be seen that the variables U and y are both 0, and the solution for v is a24 divided by -''22.

Register 953 is preloaded with a constant "24," and register 956 is preloaded with a constant "24," and register 956 is preloaded with a constant "24."

Since the subtracter 968 is cleared in the molecule circuit 91
An appropriate numerator term "24" is generated as the output of Eq.

The output of the adder 966 is loaded into the register 956 at each pixel clock time by the clock signal CK3. Therefore, at pixel clock time t□, orc*, register 956 is loaded with the sum of O+(1) (a34). The output of register 956 therefore represents the appropriate value of u=Ok and y=1 for the first part of the numerator of the equation - at the second clock time to,1. Clock signal CK3 is active at this time and at each separate pixel clock time, and the constant "34" stored in register 951 is added to the contents of register 956 at each pixel clock time.

Since y increases at each pixel clock time, the next result is 34 times 1 by performing a series of additions. That is, )'= of the first part of the numerator of formula ■
Output for 0.1.2.5.4 etc. is in register 956
The output □ is generated by adding the value of "31 u+A34 to the register 956 0 times, 1 time, 2 times, 3 times, 4 times, etc., respectively.

Similarly, register 951 is synchronized with clock signal CK2 in the time intervals between successive line scans, and register 951 is constant ``54'' for the first two in-scans of line 0.
For the 102nd vertical line scan, the value "34+"
(1) (a31) are accumulated, and a34+(2) (a31) is accumulated in the third line, vertical line 2, and this process continues thereafter. Therefore, the output of register 951 is continuously the term a
Represents u+a34. This value 1 is added to the contents of register 956 at each pixel clock time, the effect of which is to multiply the output of register 951 by y as y steps through successive pixel locations during the scanning of a vertical line. is the same as Between each series of line scans, register 956 must be cleared or reset to provide a new vertical line scan starting position for y=o.

This general idea of repeatedly adding terms at the pixel clock frequency, i.e., accumulating and multiplying by y, and repeatedly adding terms at the line clock frequency and multiplying by y, is the vertical source address. It is used throughout generator 912. In the horizontal source address generator 908, a similar method is used to perform a series of additions and multiplications by X at the pixel clock frequency;
Perform a series of additions and multiplications by y at the horizontal line clock frequency.

The second term of the numerator is generated at the output of register 953. This register is initially filled with the constant a before the start of each field period.
24 is loaded, and then the signal CKs4c is synchronized at the vertical line clock frequency between each series of vertical scan lines, and the output of register 953 represents "24+"21.Similarly, the clock signal CK7 of register 955 is loaded. energizes to first load the constant 2a2□ into register 955, then add term a52 to the contents of register 955 at the pixel clock frequency, so that the output of register 955 becomes the value a
3°.

"22. This is the denominator of the formula. Barrel shifter 970 receives a series of 32-bit words of video data for a series of pixel addresses, works with exponent detector 972 to convert the numerator to floating point, and converts the numerator to floating point. The output of 970 provides 16 bits of data representing the mantissa of the numerator, and the exponent detector 972 outputs 8 bits of data representing the exponent of the numerator term.Conversion to floating point format eliminates the need to carry leading zeros. Instead, the 16-bit output of the barrel shifter 970 can carry the upper 16 bits of the actual numerical data.In a similar manner, the barrel shifter 974 and exponent detector 976 convert the denominator term into floating point format. Reciprocal circuit 97B receives the 16-bit mantissa of the denominator term and generates its reciprocal. One method for performing this reciprocal operation at a pixel clock frequency of 70 nanoseconds is to The 8-bit solution of the denominator term is used to address a conversion table that stores reciprocal values, and to generate a linear interpolation of adjacent values that is applied to the reciprocal table.

The mantissa of the reciprocal of the denominator is multiplied by the mantissa of the numerator by a hardware multiplier 980, and the product is provided to a barrel shifter 982. Subtractor 984 performs a division function by subtracting the denominator exponent from the numerator exponent, and adder 986 adds the difference to the bias ring. This is stored in bias register 957 before each field scan period begins. To optimally utilize the 32-bit capacity of the numerator circuit 915 and denominator circuit 917, the @a1 constant is selectively shifted before the start of each field scan period in the corresponding register 95.
Load from 0 to 955. Constants corresponding to the number of shift positions of these constants are loaded into bias register 957 and added to the output of subtractor 984 to denormalize its exponential term and correctly represent the actual value of the vertical address. This denormalized exponent term is output by adder 986 to barrel shifter 982, and is converted back to 16-bit fixed point notation as the output of barrel shifter 982 by performing an appropriate shifting operation. This output of barrel shifter 982 is the actual fixed point representation of the actual vertical address without any predecimation adjustment. As explained above, barrel shifter 934 receives this vertical address and adjusts it by dividing it by a selected power of two to output a particular selected predecimated copy of the video data. Make appropriate adjustments. In addition,
The bias ring stored in bias register 957 can be positive or negative depending on the value of each term from the matrix.

These values change with the specific manipulation of the video specified in the command.

An advantageous configuration of horizontal source address generator 908 for solving Equation 31 is shown in FIG.

horizontal source address generator 908 is a molecular circuit 1002;
Denominator circuit 1004, a divider circuit 100 that may be the same as the vertical source address generator 9120 divider circuit 918 in FIG.
6, and a timing control circuit 1008. Horizontal source address generator 908 also has an adjustment circuit 1010, which is substantially the same as the adjustment circuit of vertical source address generator 912 and converts the horizontal source address U output of divider circuit 1006 into an RM'd horizontal source address. uad
Convert to JJc.

Adjustment circuit 1010 also generates the parameters MAG7 actor and alpha for horizontal interpolation decimation filter 906 . The molecular circuit 1002 is a register 101
2,1014j? and 1016, which are preloaded with data from the transform composer and factorizer 916 before the field scan period. This data is received from transfer path line 42. Adders 1020-fi7' (are alternately loaded from transfer path 942 into registers 1016 by multiplexer 1018. Register 1024 is selectively loaded with the output of adder 1026. The numerator of Equation 31 has the general form A
+B has 10, but A:': a22 a3a
a2aa32゜y B""11a32112a34'"!biC=a1
2"24"14a22. At the beginning of the prefield scan period, parameter C is loaded into register 1016 and B is loaded into register 1014. Clock signal CK21 is generated by timing control circuit 1008 at the horizontal line clock frequency and is clocked into register 10.
The 16 outputs continuously represent the value of C+By. These are the last two terms of the numerator of 201).

The register 1024 uses the timing [pixel clock according to the clock signal CK23 from the ff circuit 1008.

is continuously updated in synchronization with the frequency and generates the value Ax,
This is added to the value C+By by adder 1028,
The numerator of 2C31) is output and divided by the normalization division circuit 1006.

Denominator circuit 1004 is almost the same as numerator circuit 1002, except that constants A, B, and C are replaced by constants Ei and F. However, D”a a
a a ”””12a31 ”11”321 j
P and 21 32 22 31'""11"22-a12a21. Adder 1030
outputs the value of the denominator to the division circuit 1006. Denominator circuit 1
004 is basically the same as the molecular circuit 1002, so further explanation will not be given. Clearly, therefore, the 1lIJ arithmetic circuit 1006 outputs the denormalized horizontal source address U to the adjustment circuit 1010. Adjustment circuit 1010
then generates signals uadJ%, horizontal magfactor parameter, horizontal alpha parameter, and horizontal alpha parameter in a manner similar to the operation of vertical source address generator 912 of FIG. 11 described above.

Returning to FIG. 3, the vertical/horizontal transmission memory 900tJ) is substantially the same as the spacing memory 18. It requires only two field buffers and always writes vertically and reads horizontally.

Horizontal deinterlacing filter 902 is typically filter 6
Since deinterlacing is being performed at 00, it is not operating. However, when reading horizontally from transposing memory 18, deinterlace filter 902 must perform a deinterlace function. Therefore, only one filter circuit is required, which may be the same as either of the two filter circuits of the deinterlacing filter 00.

Predecimation filter 904 receives the 8-bit video data stream from deinterlacing filter 902 and performs substantially the same predecimation operation as performed by predecimation filter 700. Predecimation filter 904 requires only three line buffers.

Interbolation decimation filter 906 receives a two-byte information stream from predecimation filter 904 . This would be essentially the same as a vertical interbolation decimation filter, only that it receives data at half the data rate of filter 800 for adjustment.

The rate of data passing through the system is half the rate of interbolation decimation filter 8001'1m. At this point 1, the system processes two fields simultaneously and maintains a composite frame available for interbolation. Interbolation decimation filter 800 only needs to generate one field every 1/60 second.

Horizontal source address generator 908 implements the function of defining source addresses along horizontal scan lines as a function of fill pixel matrix arrangement. Horizontal target address counter 91
0 gives target position information in the order of horizontal raster scanning. This makes it possible to process the intermediate video stored in the transposing memory 900.

Vertical address generator 912 generates source addresses along vertical scan 1IsVc. Vertical target address counter 914 provides vertical scanning target position information to intermediate transposing memory 900.

The transformer 7 ohm composer factor line f916 receives the y format command, generates the transformer 7 ohm parameters by realizing the formula shown in Table 1, and generates the vertical source address by the horizontal source address generator 912. Control generator 908. These parameters are calculated by a data processor within the transformer 7 ohm composer and factorizer 916 for each field.

Horizontal intervolator decimator filter 906 implements the following function.

however, S is the source at each sample point The value of the data is Quantity is the source of points to be intervoluted In the integer part of the address, φ is the source of the points to be interbolated The decimal part of the address is h is the impulse of the interborate function The response is determined by the following formula: It will be done.

π(k-φ) 8thα"(k-φ) aia[3 h(α, φ, k) = π2 (k-02α is a number between 1/2 and 1 representing the cutoff of this low-pass response It is.

Horizontal source address generator 90B calculates the function shown in equation r3υ, where X is the target pixel number and y is the scan line address. Vertical source address generator 912 calculates the function shown in equation (2).

ra7koko□1koo Ii 10・10・i 100 Referring now to FIG. 13, a digital special effects system 1300 for color television video signals is connected to a play processor 1300 for channel 1 as well as input video signals for each channel. Channel 2 coupled to receive
, 3 and 4 array processors 1304. Video switcher 1306 receives transformed video signals for each of these four channels and outputs them in a command-specified combination. For example, all four channels may be combined to form a single output channel, channels 1 and 2 may be combined to form output channel C, and channels 3 and 4 may be combined to form output channel D. moyo<,t
+ indicates a transformed switcher 130, respectively.
The six channel inputs may be output with separate channels.

Panel processor 1308 is implemented as a zaooo microprocessor-based microprocessor system and operates in conjunction with control panel 1310 to receive operator commands.

These commands are forwarded to a high-level control unit 1314, which is also a ZAOOO microprocessor-based processor and has a multiplier 1316 coupled thereto to enhance its computing power. High level controller 1514 receives and stores transformation state programs from panel processor 130B. In operation, high level controller 1314 provides transcomposition/commands to transform composer factor 2izer 131B at field frequency. The high-level controller 1314 outputs the accumulated command states at appropriate set times, and interpolates between the immediately preceding and following states of each control parameter during these set times. .

Thus, the high-level controller 1314 allows the digital special effects system 1300 to perform smooth, controlled, repeatable special effects that cannot be achieved by an operator operating in real time. Ta.

By defining special effect states as set points and performing interpolation between set points, smooth video manipulation effects can be achieved. There is no need to specify them separately.

High level control 11 device 13t4Fi panel processor 1
308 and stores data for a plurality of setpoints. More than 25 set points are available and these are referred to herein as knots.

For each knot, parameters defining the state of that knot for each video manipulation variable are stored. Also stored for each knot is a number indicating the relative time between the current knot and the next knot. Initially, this number represents the number of field periods. However, the total time the effect takes place can be modified. The interbolation equation for each parameter is a function of a single independent variable.

When performing an effect, the value of this single variable is sent from panel processor 1308 to high-level controller 1514. The value of this variable is modified for each field. Controlling the overall time the effect performs adjusts by the amount of this modification.

High-level controller 1314 provides data indicating each variable to transform composer/factorizer 1318 for each field as the variable is accessed during a given field. At each knot, the accumulated parameter state is indicated. Between knots, each parameter is intercollated by a third-order polynomial between its state over the previous knot and subsequent knots, whose coefficients are the values of the parameters over the current knot and subsequent knots, and current knots)
> and the value of the slope or first derivative of that parameter with respect to the time spent in subsequent knots.

The slope of each parameter at each knot is determined by first testing whether its value changes with respect to the immediately following knot. If not, the slope is set to 0 and the parameter is considered constant between the current knot and subsequent knots. If a parameter is changing, a cubic approximation interpolation method is used to obtain its slope. Regarding cubic approximate interpolation, see Carl de Bois, A Practical Guide Tok Spline, No. 49.
~57, Published by Springer Barrag (New York,
(1978). Also, the slope of each parameter is set to 0 for the initial and final knot effects.

By using knots for interbolation between knots, extremely complex and continuously changing video effects can be obtained. This is done by simply specifying the desired video transformation state to a relatively small number of key knot points, without the need to specify each field transformation condition. Also, by presetting precise conditions and times, much greater accuracy is obtained than could be obtained with real-time operator control, and by defining the overall effective time, e.g. The effect can be precisely aligned to a given time slot, such as a 30 or 60 second commercial. This programming also allows multiple video channels to be accurately synchronized. Otherwise, the parameter at a given nine knots will take the value of the corresponding parameter at the previous knot, unless the current knot is the first knot, in which case the value of this parameter will be its normal value. The time between knots is set to 0.

In practical applications, it may be desirable to give two adjacent knots zero time between them. for example,
It may be desirable to perform image rotation over a given time interval and then perform an abrupt, gradual change in the axis of rotation without a corresponding abrupt change in the image. This can be done, for example, by specifying the first knot and the second knot with a given gradual rotation function between them. The third knot can then be set at the same time as the second knot by specifying the zero time of the second knot with the translated axis of rotation.

Then, a smooth transition occurs around the new rotational axis between the third and fourth knots, and the final, fp, can set an intermediate rotational state.

The channel 1 array processor is generally similar to that shown in FIG. 3, with some modifications designed to reduce cost without significantly compromising transformation quality. Specifically, the rainbow and Q chroma components of the video signal are sampled at 1/4 of the approximately 70 nanosecond sampling frequency of the Y or luminance component. As a result, it is not necessary to use low-cost, low-speed integrated circuits, but it also realizes economical efficiency, such as requiring less data storage capacity to perform maintenance so that various video components can be reliably processed. be able to.

The channel 1 array processor has a luminance or Y processing system 1320, a first color or I processing system 1522, and a second color or Q processing system 1324.

Vertical source address generator 1526 > and horizontal source address generator 1328 provide common addresses to y, r > and Q processing systems 1520, 1322 and 1324, respectively. Address generators 1326 and 1328
may be substantially identical to the corresponding vertical and horizontal source address generators 912 and 908 as shown in FIG.

The horizontal and vertical transposition memory 1330 has five field stores that operate in cyclic rotation, with one of these stores receiving and storing input video luminance data and the other four storing the output Road A
, B, Cp, and D, the video data of the four most recently received fields are output, and a new field appears on the output path, and a fourth new field appears on the output path. Individual field buffers in memory 1330 are written to as data is received in normal horizontal rask scan order, either in the same order or in an alternating order that performs a vertical rask scan of the data from top to bottom and left to right. is read out. In normal operation, memory 13
30, data is written horizontally and data is read vertically, and this mode is used unless otherwise specified.

De-interlacing filter 1332 receives the four data streams from transposing memory 1330 and generates at least one new field of data by outputting a second field of data that alternately completes the missing line of at least new field of data. into a complete frame of data that is dinterlaced.

The deinterlacing filter 1332 has a motion detector that allows 2 if there is no detected motion.
The data of the newest field is output as the middle 2-in of the newest field. When motion is detected, the average of the pixel positions in the most new field immediately above and just below a given midline of the new field is used to define the middle two ins. Although this interpolation, or averaging, of data between lines of a new field has the effect of reducing the spatial resolution of the output frame of video data, it is possible to To eliminate the double-image effect that occurs when a single frame of data or two series of fields of data occur at a single point in time. In contrast to the device of FIG.
Deinterlacing filter 1332 operates regardless of whether or not 30 operates in transposing mode.

Among them, the non-transposing mode is used for rotation around two axes of 45° to 135° and 225° to 335°.

A pre-decimation filter 1334 receives the video signal from the de-interlacing filter 1332 and makes full size copies of it (1/2, 1/4 and 1/8 size copies are also provided to the vertical interlacing decimation filter 1336). A vertical interbolation decimation filter 1336 receives an appropriately sized copy of the video data for each field from a predecimation filter 1334 and in response to a vertical source address from a vertical source address generator 1326 The vertical interbolation decimation filter 1336 outputs a video that has been transformed in the vertical dimension by selecting data points or interpolating between data points in the vertical direction. If the specified scaling factor results in an output image that is larger than the input image, an output image that is the same size as the input image, or an output image that is larger than 1/2 the size of the input image, a full-size copy of each field is used. . Use half size copy for 1/4 to 1/2 size images, 1/4 size copy for 1/8 to 1/4 size images, and 178 size copy for normal size image. Transposing memory 133 Used for images smaller than 1/8 of
0 is operating in non-transposing mode,
Vertical interbolation decimation filter 133
6 treats the image as if it were scanned vertically even if it was actually scanned horizontally.

The operation is therefore essentially the same for both modes of operation, except that the completely vertically scanned image is
The difference is that the horizontally scanned video has 25 pixels and has a shift of 68 pixels per line in NTSC format. Filter 1336 is essentially filter 800 (FIG. 3).
An economically advantageous arrangement for lower band chroma components is described below with reference to FIG. 19.

A vertical/horizontal transposition memory 1338 receives the partially transformed video array data from the vertical translation decimation filter 1336 and performs vertical/horizontal transposition. Data is read into transposing memory 1338 in vertical raster scan order and read out in horizontal raster scan order at a single field frequency of approximately 70 nanoseconds per pixel.

Predecimation filter 1342 may be configured substantially the same as filter 1334. It receives data from U-H) transpose memory 1338 and horizontal interbolation decimation filter 1334.
Full size copy and 1/2, 1/4 size and 1/2 size copy
Output both 8 size copies. The horizontal interpolation decimation filter 1344 completes interpolation decimation filtering in the horizontal direction in response to the horizontal source address from the horizontal source address generator 1328, and outputs the luminance component of the transformed video signal.

Horizontal interbolation decimation filter 134
4 may be configured substantially the same as the vertical interbolation decimation filter 1336.

An advantageous configuration of the control panel 1310 is shown in FIG.
, two status displays 1412 and 1414 to provide feedback to the panel operator, and several groups of push buttons or keyswitch controls. By using this group of keyswitches to specify modes, channels, D, and functions, a relatively complex set of controls can be achieved with a single three-axis frequency control joystick 1410. Placing the joystick in the return or neutral position causes no change in state. Moving the joystick to the right increases the selected X parameter and continues to increase as long as the joystick is held to the right. The more you move the joystick to the right, the faster the parameter increases. Similarly, this parameter decreases by moving the joystick to the left.

y> and the two axes operate similarly. When the joystick is tilted upward as shown in FIG. 14, the Y-axis parameter increases, and when moved downward, it decreases. In the case of Z-axis control, the parameter increases with counterclockwise rotation and decreases with clockwise rotation.

Although electrical connections are omitted for simplicity, the joystick as well as the respective key switches and status displays are also connected to the panel processor 1308.

Channel selection switches 1418 allow one of the four available channels to be selected to control the corresponding video. Selecting the last channel key determines the channel to which the transformation command is associated. Clear switch group 1420 allows you to clear the selected axis or set all axes to the normal,
In other words, it is possible to perform master clear to return to the input video state. For example, if translation is selected and the joystick is moved to the right to move the image to the right, the image can be returned to its normal position by operating the Clear X key. The mode selection key group 1422 determines the overall operating mode of this transformation system, making it easier to realize special effects. By selecting the program key the system enters program mode and at the first knot #
Transformation commands can be entered for each available knot at any time.

Operating the arrow pointing to the right will increase the number of selected knots, and selecting the arrow pointing to the left will decrease the current number of knots.

When the run key is operated, the system enters run mode and executes a series of accumulated knots. Actuation of the test key places the system in a test mode of operation in which diagnostic programs within the various microprocessor subsystems test and display system conditions. When the duration key is operated and one or more keys of the numeric key group 1424 are operated, the entire time that can be sung for each field of the action sequence is specified.

In program mode, the turation function specifies the transition time of the field from the current knot to the following knot. Store effect and recall effect and the entire effect by a pair of keys displayed,
That is, a series of knots is stored on a floppy disk, which can then be recalled. Number/loop 1424 also has an input and recall key. The number selected by this input key is input and accumulated, and the numerical input is completed.

The recall key can change the input value to 0 and erase the work 2-.

Parameter selection group 1426 determines the meaning of the various axes of the joystick. The aspect/skinny key selectively enlarges or reduces the size of the image in the horizontal and vertical directions by moving the joystick in the X and Y directions, respectively. At the same time, a two-axis control joystick 1410 is used to skew the image. That is, the top of the image is translated relative to the bottom of the image, turning a square into a parallelogram.

The axis selection keys determine the position of the center point at which image rotation occurs in three dimensions.

When you select this function, a cursor will appear to help you locate the rotation center point. All rotations pass through the center point of this rotation3
Occurs around one of the mutually perpendicular axes of the book.

The locate key is used to determine the position in three dimensions of the input image.

Plaquey is for selectively defocusing images. This key can be activated simply by controlling the joystick 14100z and the θ-axis.

The position/size keys are used to horizontally and vertically translate the output image relative to the input image using the X and Y axes, and the two-axis control of the joystick allows the size of the output image to be translated relative to the size of the input image. When you control it, you can do it.

The rotate key controls the three-dimensional rotation of the image around the center point. Each joystay axis controls the rotation of the corresponding axis.

Moving the joystick vertically controls rotation around the X axis, moving it horizontally controls rotation around the Y axis, and rotating the joystick rotates the image around the two axes. Any reasonable number of rotations can be specified.

For example, a zero rotation may be specified for one given knot of nine, and a rotation of ten for the next knot. The interpolation function of the high level controller 1314 can then cause 10 rotations to occur between a given knot and the next knot.

Multiple rotations are performed by manipulating the joystick to rotate around the desired axis and continuing to manipulate the joystick until the desired number of rotations has been counted and completed.

The perspective depth key is only active when the joystick is in the Z axis, and becomes smaller as the subject moves towards the back of the initial image plane, or becomes smaller as the subject moves towards the front of this plane. The speed at which the image increases is controlled by rotation, such as tossing around two axes.This can be achieved visually by imagining an image rotating around the X axis at the bottom of the image. Yes, as the image rotates away from the viewer, the top of the image moves away from the initial plane, and therefore becomes smaller. The perspective depth key allows you to control how quickly the image shrinks relative to the rotation angle. can.

The LUM HUE SAT key specifies the color of the background of the output video in areas not occupied by the first video. For example, in the perspective rotation example above, when the top of the image loads away from the plane of the display screen, the top of this image becomes smaller and the top right and top left corners of the display screen are no longer occupied by the first image. . LUMlHUE
8AT key to move joystick 141°y, z
> and X axes can each control corresponding components of the background image. This background video control is particularly useful when used in conjunction with switcher 1506 (FIG. 13), which can be used in response to color or brightness keys.
It is programmed to replace video data from one channel with video data from another channel to assemble a single channel composite video.

Program key IFP 1428 is for programming various knots of a given video effect. Actuation of the insert knot key inserts a new knot between the current knot and the previous knot, and the remove knot key is similarly programmed to remove nine knots from the series of knots. When the Save Knot key is operated, all parameters applied to a given knot are stored for later recall by operating the Recall Knot key, except in the case of rotation. This save and recall function is used when the parameter state at a given knot is duplicated at the next knot. Of course, some or all of these parameters can be changed after duplication. When you operate the pause knot key,
Halts at the current knot in run mode and waits for the next user command. When you operate the loop key and select the duration value using the numeric key group 1424,
Loops back from the last knot of the effect to the first knot. The transition time from the last knot to the first knot is
After selecting the loop key, take the input value. This loopback causes a series of intermediate knotted sFi sequences to be executed sequentially until the continuous looping sequence is interrupted by operation of the stop key.

The freeze-update rate key is used to specify the number of fields to be held until the frozen video is updated using a group of numerical keys 1424. That is, when the key with the number 8 is operated after the freeze update key, two new video fields are sampled every eighth field and are held until the next update time. In fact, the horizontal and vertical transposition memory 13504-j is inhibited from receiving new input video fields until the specified number of input video fields has occurred.

As an example of applying an effect to a given channel, reduce a full size image to the size of Vc 1/2 in the center of the screen,
Consider an example of displaying a perspective view, rotating it 360 degrees around the Y axis, and then returning to full size. Switch group 1418 selects a desired channel, for example channel 1.
After selecting , the program switch in group 1422 is operated to set all states to the initial state for generating a full-size image, and no operations are performed. This initial image state is then the first knot point of the effect. Here, the save not key in group 1428 is operated to maintain the initial state, and later, at the end of this effect, this effect is used to return to the initial state.

Therefore, the duration time is specified using the numerical key 1424, and the time of the next knot, that is, the second month, is defined. For example, the number 600 indicates the initial knot time of 6.
00 field period, or 10 seconds. During this first 10 second period, the full-size to half-size
"Zoom" occurs. This number of knots is displayed on status display 1412 and appears on status display 1414 when a knot time value is entered. - In general, the status display shows the status of the selected parameter as well as the current knot position.

If the arrow pointing forward or to the right on group 1422 is operated here, it will move to the next or second knot state. By operating this key, the programming of the first knot event is closed and the programming of the second knot is opened.

Now operating the 2D position size keys from group 1426, the joystick can now be used to change the position of the image on the screen according to the XY movement of the joystick, or to You can change the size of the image by moving the rotary knob on the joystick. In this example, the joystick knob is rotated until the casing image becomes 1/2 the size while keeping the XY position constant. Here, the duration until the next knot, ie, the 30th knot, is specified, and in this case, this specifies the time for size reduction.

Operate the duration button to enter a 300 field period, or a 5 second period. If the programming of the 20th knot is complete, operate the ford key again to set the 20th knot.
Close the 30th knot and open the 30th knot. Note 30 specifies a 360° rotation of the half-size image around its Y axis and adds some three-dimensional perspective effects. The rotate key in group 1426 is now operated to enable the joystick and rotate the image about any of its three axes. In this example, moving the joystick horizontally to the right rotates the image about its Y axis. By moving the joystick vertically, the image can be rotated about the X-axis, and by rotating the joystick knob about the 2-axis, the 0-axis, the image can be rotated about the 2-axis. In this example, move the joystick to the right and hold it until the image has been rotated to a sufficient angle to create a perspective effect, for example 30-45 degrees. This rotation is necessary because the perspective effect cannot be seen in 1, where the image is rotated from the plane of the display screen. If you want to partially rotate the image, restore the joystick and press group 1426.
Operate the perspective depth key in . Now manipulate the joystick 0 control to control the amount of perspective needed to add the desired amount of perspective to the image. The desired full 360° image rotation is then achieved by operating the rotation button again and holding the joystick to the right until rotation is seen on the screen. Here, the duration of knot 3 is specified by operating the duration key and a set of numeric keys in group 1424. In this example, assume that this period is entered as a 600 field period corresponding to 10 seconds. In this case, this 10 seconds defines the time of knot 4, which is a single, ie unaltered, video state. Therefore, during the last 10 seconds, the video is zoomed back to full size.

Now select the step arrow key to close knot 5 and open the last knot 4. The recall knot button from programming group 1428 is operated to store the first full size or 1 parameter to be applied to the previously stored current knot point 4.

You can now complete this effect and store it to disk by selecting the store effect button from mode control 1422. Further editing of effects, such as changing or adding duration and operations, can also be done by reverting to another knot, inserting another knot at a selected location, or deleting a knot.

Alternatively, the total operating time of the entire effect can be modified without changing the relative duration between each knot point. For example, the specified operation time for the effect is 25 seconds. However, the entire operation time is as follows: by operating the duration key applied to group 1422, and then pressing the keyboard 1422.
For example, a 30 second commercial can be easily increased to 30 seconds by inputting 1800 by 41C. Thus each respective knot time is effectively increased by 50/25. That is, the first knot time effectively increases from the 600 field period to the 720 field period, the second knot time effectively increases from the 300 field period to the 360 field period, and the third knot time effectively increases from the 300 field period to the 360 field period. The knot time effectively increases from 600 field periods to 720 field periods. This brings the total operation time to the specified 50 seconds.

Referring now to FIG. 15, the horizontal and vertical transposing memory 1530
, 5 field stores 1510 labeled OH2
~1514.5: 4 multiplexers 1520,! ?
and an address control circuit 1522 connected to provide address and control signals to and other portions of transposing memory 1330. field store 1
Although 510-1514 are shown separately for each luminance component, they operate in common synchronously and advantageously address the I& and Q power 2-component field stores as described below. .

Distributor 1502 may have Y as an input, for example.
That is, the standard power 2 - one component of the television video data, such as the luminance component, is received and stored in the field store 1510.
This series of fields of input data is stored cyclically in a series of .about.1514. When all five field stores are full, 150 distributors
2 continues to send input field data to the field store which stores old field data. As a result, the five field stores 1510-1514 always store at least four new field data, and the fifth at least new field data is overwritten by new input data.

A multiplexer 1520 receives the outputs of the five field stores and then cyclically outputs data from the four newest stored complete fields to the four outputs 2-in, so that any new field is routed to the second The new field is output to path B, the third new field is output to path C, and the fourth new field is output to path C. Therefore, the four most recent video data fields are sequentially applied to the deinter and lace filter 1332.

In the horizontal/vertical transposing memory 18, a transposing memory 1330 constantly receives and stores data in the horizontal scanning direction. In the normal operation mode, this accumulated field data is transposed and output in the vertical scanning direction, and in the special operation mode, the stored field data is transposed and outputted in the memory 133o.
operates in non-transposing mode, outputting video data in the exact same horizontal scan direction in which it was read.

In FIGS. 16 and 17, there is a memo for field store 0 corresponding to store 1510 in FIG. 15! J1
600, > and I death and Q processing system 1322.13
An advantageous example configuration of 24 corresponding stores is shown.

This luminance signal component memory has eight storage modules labeled YO to Y7. Each of these modules is 32 hoods deep and 1H element or 8 bits wide. Memory 1600 operates in 140 nanosecond cycles and stores two luminance signal pixels simultaneously. In each memory cycle, storage modules YO, Y2 .
Y4. Or one of Y6 stores the previous pixel, and the four later storage modules Y1. Y3. The next pixel, that is, the next pixel, is stored in one of Y5"! or Yl. Before writing to memory, the first luminance signal pixel data is stored in the Y input first strobe signal YIE8. 1602.Then, the next pixel is stored in the Y-input second register 1604 in response to the Y-input second strobe signal YIL8.In these same two pixel periods, the row and column addresses are stored in the storage module Yo~
When Y7 is strobed and Y input second register 1604 receives the next pixel, the memory is prepared so that two pixel data can be written immediately.

The storage module is used in a four-phase rotating configuration because it has an economically viable cycle time of 1400 nanoseconds or more. During the first 14Q nanosecond memory cycles K, data is stored in storage modules YO and Yl by the phase 1 signal. In the second phase, data is stored in storage modules Y2 and Y3, in the third phase, data is stored in storage modules Y4 and Y5, and in the fourth phase, data is stored in storage modules Y6> and Yl. Ru.

During the 5'#rth cycle, the address input increments and repeats the rotation cycle to input the modules YO and Yl.
In Phase 1, information begins to accumulate. So clearly, for each memory module, 4X140 nanoseconds or 5
A period of 60 nanoseconds is available for each data access cycle, which can be fully realized with economically available memory chips.

Even if a read operation fails, these storage modules operate in substantially the same way, and the 140 nanosecond memory cycle KTh allows the earlier storage devices Yo, Y2 . Outputs data from one of Y4 or Y6 as first strobe signal YO
E8, the Y output image is accumulated in the register 1606, and is stored in the subsequent module Y1. The difference is that data from one of Y, Ys, or Yl is stored in the Y-output second register 1608 in response to the Y-output second strobe signal YOL8. Next, 2
The two pixel data are serialized and made available sequentially on the Y output signal line YO.
energize with OEBS, then after 70 nanoseconds, Y output 2nd
The output of the register 1608 is the Y output second energizing signal YOLE.
This is done by energizing with S. For reading, storage devices YO-Y7 continue to operate in the same manner in a four-phase rotary cheating operation. Reading in the row scanning direction is substantially the same as a write operation, except that the storage device receives a read command instead of a write command.

The storage device shown in FIG. 16 further includes (2) two storage modules E2 and F for color video signal components, and two storage modules Q2 and Q7 for Q color video signal components. Power 2 - Signal power is sampled at 471 of the frequency of the luminance signal component, so each color signal component requires only two memory modules, compared to eight memory modules for the luminance signal component. I need. I
The i and Q luminance signal storage modules operate exactly in parallel except for the multi-readout fl:, which receives data, and the I
2 and Q2 storage modules operate in parallel with the Y2 luminance signal storage module, while the I7 and Q7 storage modules operate synchronously and in parallel with the Y7 luminance signal storage module. By operating synchronously and in parallel in this way,
The color signal storage module receives both the address signal and the timing signal generated by the luminance signal storage module. Since the I2 and Q2 storage modules are synchronized with the Y2 storage module of phase 2, and the F and Q7 storage modules are synchronized with the Y7 storage module of phase 4, the color signal field stores each have a 180° phase difference. It will now operate as two 1120 nanosecond memories. In any case, each of the four pixels of luminance signal data and one pixel of KI power 2-signal data and one pixel of Q color signal data will be accumulated. The color signal storage module is configured to read out the luminance signal data at a constant frequency of 1/4 of the 70 nanosecond frequency of the luminance signal in both horizontal and vertical scan readout modes in synchronization with the appropriate luminance signal storage module. This is necessary for proper operation of Field Store 0. This can be understood by referring to Table 1.

The mi table ti address table shows how data is stored in the Y storage module. Although not shown separately for each luminance signal component, the Y storage module C2Th
The color signal data of the corresponding pixel for each luminance signal data of each pixel stored in the color signal storage module I2. Q2Th and I7. This is shown collectively for the two stores by the luminance signal pixels Co, o, and CO21 in the right two columns of Table 1.

For synchronization and timing purposes, it is advantageous to start operations before the actual initial address storage location. Therefore, to avoid identifying negative addresses, data begins to accumulate at address locations of 16×112=1792. When writing data to field store 0 in horizontal scanning mode, the data of pixels po, o> and POll sequentially reach Y input line YI,
They are stored in the Y-input register 1602 and the Y-input second register 1604, respectively. The first two pixels of these data are in registers 1602 Th and 1604
is written to the memory module Y whose matrix address is phase 1.
o> and Yl. As the first phase 1 memory cycle continues, pixels PO12 and PO13 are sequentially
Input image register 1602: and Y input second register 1
604 respectively. A phase 2 memory cycle then begins and two pixels are stored in storage modules Y2 and I3, respectively. This process continues through the first raster scan line until the memory phase is in phase 1.
After recycling pixels PO26 and PO17 to storage modules Y6> and I7 at address 1792 in phase 4, pixels PO,8 and PO19 are stored at memory address location 17X112=2016. The address map allocates 112×8=896 pixels to the address space of the memory module for each horizontal scan row. This is 768 times applied to the NT8C horizontal scanning line.
This is sufficient to handle not only pixels but also a larger number of pixels in a PAL scan line without changing the memory configuration. Note that the ■ and Q color pixels are simultaneously luminance signal pixels P0.2. Po, 7. *Accumulated together with Pa, 10, etc. After all the pixels of the first raster scan line have been accumulated, the next raster scan line is prepared for accumulation during horizontal retrace. Regardless of which phase the last pixel of the first row was accumulated, the phase returns to phase 1. However, the field store sequence starts one pixel time at the beginning of row 2. Therefore, the Y input register 160
2 is strobed for one pixel period before actual video data is available, and don't care information, indicated by X in Table 2, is loaded. After 70 nanoseconds, the Y-input second register 1604 is strobed to receive the data for pixel P1,0. Data accumulation then continues in the normal manner,
Data is stored in the color signal storage location of the field store during phase 2 and phase 4 operating times.

Upon receiving the fifth rask scan row of data, the timing cycle begins with two pixel periods and stores the don't care data in phase 1 between storage modules YO and Y.
Write to l. In phase part 2, pixel P2. O$p and P2,1 are written to storage modules Y2 and Y5.

In the same phase 2, color signal pixels 2,0 are written to color signal memories I2 and Q2.

This same method of operation continues with the memory start time incrementing by one pixel period with each row until the eighth rask scan row is accumulated. Upon receipt of the ninth rask scan row (row 8), the address input is incremented to 2,688, the start time is returned to the initial time relationship, and only valid pixel data is accumulated, pixel P8,0 and P8. , 1 are stored in the modules Ya> and Yl in the interphase 1. This time stagger process is then repeated, writing one pixel's don't care data at the beginning of column 9, writing two pixels'don't care data at the beginning of column 10, and so on.

Pixels of video data from different rows of one column are stored in nine memory modules staggered by modulo 8 during the readout period for a series of rask scan rows. , these can be taken out in order when reading out in column scan mode.

For example, during the first vertical scan memory cycle, time address 1792 is provided to the Y input first module YOK and address 1904 is provided to the Y output second module Y1. During the phase 2 memory cycle, time addresses 016 and 2128 are applied to M1 and the second module, respectively, and pixel P2.0 is read from module Y2 and pixel P3.0 is read from module Y3. Between the next phase, pixels P4゜0 and P
5.0 is read out and so on.

Once the pixels of the seventh and eighth vertical rows have been read out, this cycle is repeated, returning to phase 1 to read out pixel P8,0 from module YO and read out pixel P9,0 from module Y1.

For the second column, memory operation begins one pixel period earlier, just like the second row. As a result, during the first phase 1 cycle, don't care information is read from module Yo and pixel PO11 is read from module Y1. During the next phase 2, pixel P1,1 is mosier Y2
Pixel P2,1 is read out from module Y3. This process continues with recycling of module 8 until all data in column 1 has been read.

The first two pixel periods are then read out in the third column, indicated by column 2, and the don't care data is read out from the modules YO and Yl in phase 1;
Pixels P2,0 and P2,1 are read out from modules Y2> and Y3 in phase 2. In addition, between phase parts 2
By appropriate synchronized operation of the color signal memory module by pressing buttons 4 and 4, every 4th luminance signal pixel □ color signal pixel is read out, and the color signal pixel is read out at a sampling frequency of 1/4 in row scan and column scan memory operation. Preserves color signals.

At the same time, the selected field store configuration makes the hardware configuration of the address control circuitry relatively easy.

This interphase is simply reset to position at the beginning of each row or column scan readout, and then cycles modulo 4 (two of them operate in parallel, so the entire storage is modulo 8). Modulo 8 operation automatically staggers pixel storage locations by starting memory operations for each successive row or column one pixel period earlier, and each memory The module's stored pixel data can be accessed in any suitable order.

A slight problem that must be considered is that address boundaries cross between staggered phases during readout in the 11 column scan mode. Reading column 0 generates a series of pixels in a series of module locations, each corresponding to a memory address location in a row of addresses. That is, each series of addresses is incremented by 112, and addresses f792°1904,
2D16.2128.2240 etc. occur. However, when reading column 1, it is appropriate to continue incrementing the address in this way by 112 only until pixel P1,7 at address location 1905 must be read out from module YO in locator 1 f 19040s. be. This deviates from the direct addressing scheme and requires incrementing the normal addresses that would otherwise read pixels such as the 7th, 15th, 23rd, etc. Similarly, column 2 is the 6th and 7th,
The address must be incremented to read pixels such as the 14th and 1511@, the 22nd and 23rd pixels. For column 3, the 5th, 6th, and 7th
The address must be incremented to the th pixel, the 13th, 14th, and 15th pixels, the 21st, 22nd, and 23rd pixels, and so on. So clearly, as each column progresses, incrementing the address starts one pixel period earlier in mod c1B until we have read out the pixels at -1, 8th, 16th, 24th, etc. . For columns 0.8.16, etc., this increment is not necessary. As previously mentioned, this staggered nine-step operation is performed by address control circuit 1522, which is set sequentially one pixel period earlier in module 8 for successive columns during vertical scan memory operations, and is always set one pixel period earlier in module 8. This is done by setting an increment signal that terminates at an address boundary.

Referring now to FIG. 17, field store 0 address timing circuit 1700 is shown. In addition,
Field stores 1 to 4 are essentially field stores 0
is the same as The address timing circuit 1700 includes a timing generator 1700 and a timing control circuit 170.
It includes a 4.7-bit horizontal address counter 1706, a 9-bit vertical address counter 1708, and an address map circuit 1710. Synchronizing the field store to the input data is accomplished by the line erase clock signal, which goes high immediately after the last pixel of each vertical or horizontal scan line and goes high at the time of the first pixel of the next scan line. Just before it goes back to low level. Further, the aforementioned synchronization is performed by the vertical clock signal V CLOCK,
This produces a one pixel wide pulse immediately after the last pixel of a field.

Therefore, at the end of the field signal V-- CLOCK, the 3-bit modulo 8 counter 1720 is asynchronously reset during the vertical retrace interval following each field. This O
The output is sent to a continuous memory (ROM) 1722,
This is a counter 1 that can preset a 4-bit count value.
It responds by outputting to the four load inputs of the 724.

Counter 1724 is responsive to a 70 nanosecond pixel frequency clock signal. Counter 1724 is filled with signal line blank CK until this signal ends just before the start of each scan line.
In response to K, the count value 5 is loaded. Next, counter 1
720 immediately begins counting up to 15. Count value 1
5, the counting end output is the timing control activation signal T&CE
NBL is generated, which prevents further counting during the next line erase period until counter 17-4 is loaded again.

The end of the line erase signal is synchronized with the input video data, and the 31'0 pixel clock period required to count from 5 to the final count value of 151 is the period when the field store 1600 is connected to the register strobe signal and the phase 10 matrix address strobe signal. equals the system pipeline delay time required by timing control circuit 1704 before energizing.

Memory 1600 is thus properly synchronized to receive and store the first pixel data of the first scan line and subsequent pixel data.

After the end of the first scan line signal, the line blank clock signal goes high and the counter 1720 is incremented by 1.
is counted and a count value of 6 is loaded into the counter 1724. This means that when the count value of the counter 1720 becomes 1, R
Output from OM1722. Since counter 1724 starts at a level one count higher, the count output at its terminal occurs one pixel period earlier, and memory 1604
starts operation one pixel period before valid data is received. In the case of writing, don't care data is written to unit 0 of memory 1600. When data is read from memory, the output data is simply ignored because the data output arrives before the time when valid video data is recognized.

Following the second scan line, the counter 1720 increments again, and the ROM 1722 sets the count value of 7 to the counter 172.
4, and the don't care data for the two pixels has been written to or read from memory 1600 before the valid data period. This operation continues until the counter 1720 increments to a count of 7 before the 8th scan line (scan line 7 if starting from 0) and a count of 12 is loaded into the counter 1724. . As a result, 7 pixels of don't care data are stored in memory 1600.
The first valid pixel occurs in phase 4 corresponding to module 7. After the 8th scan line and before the 9th scan line, the counter 1720 synchronizes to the clock and opens the count value 0.
0- and repeat the above cycle.

This process, which repeats modulo 8 for each scan line and starts one pixel period early, automatically reduces the memory required for transposition when reading or writing at high speeds in vertical or horizontal scan modes. Stepping or staggering of locations will be performed. The operation of the address counting timing circuit is essentially the same as the timing generator 1702 providing the necessary stepping of the starting address location.

Since the eight modules of field store memory 16000 store eight pixels for each address location, horizontal address counter 1706 increments once for each eighth column position horizontally. It is driven by the signal CIG, which occurs at 1/8 of the pixel frequency every 560 nanoseconds in horizontal mode. In vertical mode, signal CKH is taken as the 2-in-4-7 output of counter 1720;
This means that counter 1706 increments after every eighth vertical scan line. This is equivalent to every eighth pixel in horizontal scan mode. The D input of horizontal address counter 1706 is connected to a logic OK connection, and the load input is connected to be reset to 0 by signal LDH.

The signal LDH is a V clock in the vertical mode, and is a line blank CK in the horizontal mode. Thus, in vertical mode, horizontal counter 1706 is reset at the end of each field, and in horizontal mode, after each scan line.

Vertical address counter 1708 is a 9-bit counter/reader whose clock input is connected to signal CKV, which is taken from the 70 nanosecond input hold CK signal in vertical mode and from the line blank CK signal in horizontal mode. It will be served.

Therefore, regardless of mode, each new horizontal scan line (vertical position) is stepped.

Signal LDV periodically resets counter 1708, the four least significant bits are fetched from ROM 1722, and the upper bits are reset to zero. At the beginning of the field, vertical counter 1708 is preset to 16, providing a small offset that can avoid using negative numbers in some situations.

In the horizontal mode, the ROM1722 receives the address input signal H.
In response to the mode, the counter 1708 is always counted as 1.
Preset to 6.

However, in vertical mode, the preset state of counter 1706 depends on the force count value stored in counter 1720. Vertical address counter 1708 is preset to 16 in the first column.

The second column is preset to a count value of 15.

Note that in the second column in vertical mode, the first pixel represents don't care data. Counter 1708 operates at the pixel frequency, so by the time the second pixel arrives: vertical address counter 1708 (representing the first pixel of video data) has incremented to a starting address count of 16.

In vertical mode, this operation continues, with counter 1708 being preset to progressively smaller counts for each new vertical scan line until a count of 9 is loaded before the start of the eighth scan line. With the start of the ninth scan line, counter 1720 recycles to 0 and the process repeats.

The address map 1710 has counters 1706 and 1708.
, and corrects errors in the number of pixels of scanning lines at modulo 2 boundaries in order to eliminate wasted address space. This address map is easily constructed by an adder, and the functional address = H/8 + 128V - 1dV + c:H
/8+112V+C is generated. Since the multiplication is performed on modulo 2 boundaries, it can be performed by a binary shift. The C or carry input is connected in this case to increment the lowest address and create the special condition of vertical mode. A spacing of 112 in the vertical direction produces 8.times.112 or 896 pixels in the horizontal scan line. This satisfies not only the NT8C but also the PAL standard.

The carry input is generated by the Q output of the 7 rip 70 tube 1726, the D input of and is connected to the signal H mode, the preset input is connected to the output of the decoder 1728, and the clock input is 560 nanoseconds (8 pixel time). Connected to a clock signal.

This clock signal is synchronized with the start address for each scan line memory operation, regardless of whether it is don't care or actual video data. 7 lip-flop 1726 operates only in vertical mode and not in horizontal mode.

In vertical mode, the 7-rip 70-tube 1726 is loaded with a logic 0 to generate a carry every 8th pixel starting at the start of deposition. This is preset and vertical counter 1
The carry input ends every eighth pixel when 708 intersects the modulo 8 boundary. Decoder 1728 is powered by ICCKV K every pixel time in vertical mode, which is driven by the 70 nanosecond input hold CK signal. In horizontal mode, encoder 1728 is energized during each retrace period by the line blank CK signal.

When column 0 is scanned in vertical mode, the 560 nanosecond signal CK18 clocks the 7-rip 70-tube 1726, while the counter 1708 clocks a count of 16, i.e., 6t on the modulo 8 boundary, and the decoder 1728 clocks its output. 7 rip 70 just before becoming valid and incrementing the address
Preset knob 1726. This is repeated every 8th pixel. Clip 70 tubes 17 for row 1
26 is driven at the cycle start and counter 1708 is set to 15. Therefore, when the carry input is valid, don't care pixels are read out during the retrace period. At the next pixel time, the counter 170B counts up to 16, the Aritub 70 tab 1726 is preset, and the carry command ends. However, after pixel P7.1 (eight pixel period or 50 nanoseconds after the start) has been read out, knob 1726 is driven and reset, and the address of pixel P7.1 is incremented. Looking at Table 1, it can be seen that this address path properly addresses the data for this pixel.

For column 2, the operation of memory 1600 is two pixels earlier so that the last two pixels of each block of IC1a receive a stepped address.

The last 3 pixels in every block of 8 for column 3 receive the incremented address until the last 7 pixels in every 80 groups for column 7 (the 8th column) receive the incremented address.

The cycle is then repeated and no increments are commanded for column 8.

Although the memory 1600 operates at a two-pixel differential 140 nanosecond clock frequency, the addresses of each of the two operated memory modules in a memory cycle may be different. Therefore, address map 1710 must alternately provide fast and slow addresses at the pixel frequency. Every 140 nanosecond cycle, the early address is loaded into the early address hold buffer 1730. After 70 nanoseconds, the late address is loaded into the fast address hold buffer 1750 and the carry address buffer register 1732. At the same time, the early address loaded in the 1 fold buffer 175Ofc is loaded into the early address buffer 1734 and provided to the memory 1600. At the next 070 nanosecond clock period, the late address loaded into hold buffer 1730 is loaded into buffer 1, and the next early address is buffer 1.
It is simply lost when loaded into 73Ω. In this way, the correct addresses are provided in memory 1600 for each of the two modules, and these modules operate for about 140 nanoseconds.

In horizontal mode, there are relatively few scan lines, but the number of pixels in the scan line dust is large. In vertical mode, there are many scan lines, but the number of pixels in the scan line dust is small.

As a result, there are many flyback periods, but the duration of each period is short. As a result, memory 1600 can be configured with dynamic memory chips that perform one refresh cycle during each retrace period in vertical mode and two refresh cycles in horizontal mode.
It turns out that it is advantageous to perform a refresh cycle.

Referring now to FIG. 18, the dinterlace filter 1332 includes a motion detector 1802 & a deinterlace or frame generator circuit 1804, which outputs a complete frame of data at the field frequency. Each field period, the most recently accumulated field is always output as half of a frame of video data, and if motion detector 1802 detects no motion, the middle scan line of this frame is
Sourced from the newest field.

When two different fields sampled at 1/60th of a second apart are mixed into a frame representing a single point in time, the occurrence of motion results in a double image of a moving object. Cheap. Thus, when motion detector 1802 detects motion, the scan line between the old field and the new frame outputted on the displayed data path is taken as the average of the pixels above and below each series of pixels in the intermediate scan line. Generating pixels in the middle scan line by averaging the pixels above and below in this way reduces the bandwidth by approximately 1 in the vertical direction.
/2, but gives a satisfactory image as the double image effect occurs when two successive fields are combined during the occurrence of motion.

Subtractor 1810 receives the first new field on input C, and receives the third newest field on input C;
For each pixel, the data of the third newest field is subtracted from the data representing the newest field of the next pixel, and the difference is stored in pit register 1812. Threshold detector 1814 is responsive to the difference output of register 1812 to generate a logic one signal when the difference exceeds a selected threshold, eg, 8 of 256 possible states. 1
Bit register 1816 stores the motion indicating output of threshold detector 1814 and provides it to OR gate 1820 which in turn provides to one pixel communication circuit 1818 whose output is also provided to OR gate 1822. Similarly, subtractor 183
o subtracts the pixel data of the fourth newest field in the input path from the equivalent second newest field pixel data of input B and provides this difference to an 8-bit register 1832. Threshold detector 1834 is responsive to the output of the difference stored in register 1832 and outputs a logic one signal when the difference exceeds a given threshold, eg, 8 of 256 states.

The value output during this time provides an indication of the motion stored in a 1-bit register 1836, the output of which is provided to an OR gate 1820 through an 11 pixel delay circuit 1838.

Registers 1812, 1816, and 1852.183
The 12 pixel delay times by 6 and the additional delay times by delay circuits 1818 and 1838 are synchronized with the delay circuits inserted in the video data path and are applied to the new field by detecting motion in the pixel position. 2 in the new field vertically above and below the pixel that is generating the pixels above and below it.
generated as an average of two pixels.

When motion is detected at the position of a pixel in the second most recent field, the position of that single pixel is generated as the average of the pixels immediately above and below the generating pixel. Delay circuits 1818 and 1838 generate a delay of 1N elements in response to a pixel signal during vertical scanning, and generate a delay of 1N elements in response to a line signal during horizontal scanning.
Gives scan line delay. This is because vertically adjacent pixels are separated by line scanning time in horizontal scanning mode.

The most recent field of pixel data in the input field passes through two 8-bit registers 1840 and 1842 to a delay circuit 1844. These registers compensate for the delay of registers 1812> and 1816 in the motion detector. Delay circuit 1844 is responsive to a pixel/scanline delay input from timing control circuit 1850 to provide a one pixel delay for vertical scan normal operation mode. The output of delay circuit 1844 represents video data at the newest field position of the frame data output at the field frequency.

Addition circuit 1846 adds input and output to delay circuit 1844,
Clear the least significant bit of the sum, divide it by 2 to get the average, and transfer this average to the multiplier 18480A input. The B input is coupled to the output of multiplier 1866.

The select A input of multiplier 1848 is coupled to the output of OR game 1820 to receive the motion detection signal. Thus, in the presence of a motion signal, alternating scan lines of seven frames of output data are output by multiplier 1848 as the average of the video data above and below the pixel of data being combined. This output of multiplier 184B is shown as the old field.

The data of the new field at No. 2 g appearing on input BK is shifted into two 8-bit registers 1860 Th and 1862, which are shifted into 8-bit register 183 corresponding to the input of delay circuit 1864 of motion detection circuit 1802.
2 and 1816. In a normal vertical scan mode of operation, delay circuit 1864 generates a one pixel delay in response to the pixel/scan M signal from timing control circuit 1850. The output of delay circuit 1864 is multiplier 1
8660A input. Therefore, OR game)
In the absence of a motion signal from 1822, the old field video data is taken from the second newest field of data arriving at input B, interlacing the scan lines of the new field video data to form one complete frame of data.

In a special mode of operation in which the transposing memory 1330 outputs data in the horizontal scan direction rather than the vertical scan direction, the pixel/scan line signals are transferred to the delay circuits 1818, 1858.
．． 1844 and 1864 must be instructed to store or delay one complete scan line of data. This is so that the input pixel data can be aligned with the pixel immediately above it in the input field (an input pixel is aligned with the pixels of the two scanlines above it in a frame).

Accordingly, the appropriate corresponding vertically parallel pixel data is averaged by adder 1846 and provided to the A input of multiplier 1848. Delay line 1864 provides a one scan line delay in the horizontal scan mode of operation, compatible with the one scan line delay that must occur in delay circuit 1844.

Thus, the dinterlacing filter 1332 outputs a complete frame of data at the field frequency, while new frames of data are continuously output on new field paths, and intermediate horizontal scan lines of data are output at the field frequency. If no motion is detected, it appears in the old field output as the second oldest field's data, and if motion is detected, it appears in the new field's data as the average of two vertically adjacent pixels. In the vertical scanning mode, the outputs of the new and old fields in the time series represent vertically adjacent pairs of pixel data. That is, when the even line field is the newest field being received, the scan lines of the new field and the old field occupy pixels PO, OTh, and P, respectively.
l, 0 data, and then P2. (1- and P3,
0, followed by 1CP4.0 and P5,0, etc.

In the horizontal scan mode of operation, the new field and old field carry vertically adjacent complete scan lines of data. That is, if the most recent input field is an even field, the series of data will be the new field data and the pixel positions PO, O$> and Pl of the second most recent field data.

With OK, j) shi, then Po, 1> and Pl
, 1, then PO12 and Pl, 2, and so on until the first two scanlines of one frame of data are output. 0j? and once the first scan line is output, the second and third scan lines are output,
This continues below.

If the new field is an even field representing scan line 0.2.4, etc., then the old field contains scan line 1.3.5, etc., and the old field pixel is the data 1 scan line below the corresponding new field pixel. represents. The time relationship of adder 1846 is such that when motion is detected, the old field is generated as an average of the data in the current scan line and the next scan line. For example, in vertical mode, new field pixel PO1
2 is output, pixel PO93 becomes pixel Pa, 2> and PO
formed as an average of 14.

But if the new field is an odd field,
This time relationship causes pixel PO93 to be outputted not to pixels PQ, ITh and PO13 as required, but also to pixel PO12, which is formed as the average of pixels Foes> and PO25.

This relationship is modified by bypassing delay circuit 1864 if the new field is an odd field. This effectively generates output data pairs such as column pairs, don't care, 0, 1.2, and 3,4. As a result, the proper temporal relationship is restored, such that the old field data is connected to the current pixel and the new field KTh in one scan line below the corresponding new field data. It is extracted appropriately by taking the average with the pixels.

Multiplier 1866 is connected to selectively bypass delay circuit 1864 , with its A input connected to the output of delay circuit 1864 and its B input connected to the input of delay circuit 1864 . The select large input is connected to the signal even field to select the A input for the even field and the B input for the odd field.

Referring now to FIG. 19, chroma pre-decimation and interpolation decimation filter 1
900 is basically the same as the vertical and horizontal portions of the system. This O/chroma stem is connected to Il as well as predecimation filters 1534 and 1342 and vertical interpolation decimation filters 1336.
Although filters can be used, the bandwidth of the chroma data is only 1/4 of the bandwidth of the luminance data.
Since the device of Figure 19 has a correspondingly lower data rate,
This can be achieved at a low price.

The chroma pre-decimation and interpolation decimation filter 1900 includes a pair of line pack memory sections 1902 and 1904, and a white address circuit 1.
906, which assigns a white address to the Batza section 1902, 1904 upon receiving data from the previous transposing memory corresponding to the horizontal-vertical transposing memory 1330 or the vertical-horizontal transposing memory 1338 in the luminance data path. give.

White address circuit 1906 also provides an address when data is stored and written to line buffer sections 1902 and 1904, and then read out and predecimated by predecimation filter 1908. 2-in buffer sections 1902Th and 1904 operate in parallel to double the speed of memory 1600. The line buffer units 1902:lr and 1904 actually store three scan lines of video data, and each scan line storage includes a full size copy and a predecimated partial size copy, which is This includes 1-size, 1/4 size and 1/8 size.

Filter 1900 sequentially operates on three scan lines of data in an interlaced manner. One scanning line accumulation position Vct? Then, the video data of the input scan line is accumulated, replacing the video data of the old scan line. At the same time, the video data of the most recent complete scan line is predecimated by the predecimation filter 190B, and the complete data of the second most recent scan line is processed by interpolation. Output by decimation filter 1910.

Memory portions 1902, 1904 operate in 560 nanosecond cycles consisting of eight 70 nanosecond subcycles. In a given memory cycle, input data is received and stored in registers 1920 Th and 1921.

In the first half of the next cycle, the two pixels stored in registers 1920 Th and 1921 are written to line buffer sections 1902 and 1904 before the data of the earlier pixel in this cycle is received. Similarly, the data of the two pixels processed by the predecimation filter 190B are accumulated by the early register l 924 and the late register 1925, and the line buffer section 19 of the predecimated data accumulated therein.
02. Write to 1904 is suspended. The sequence of eight subcycles that repeat with each 560 nanosecond cycle of line buffer sections 1902, 1904 occurs as follows.

t interpolate. That is, the video data of two pixels is read into early and late pixel interbolation decimation buffer registers 1928 and 1929;
Used in interbolation filter 1910.

The data of two pixels of the two predecimation filter 1908 are read and the predecimated pixel data of one pixel is stored in the previous predecimated data buffer register 1924.

Five interborate. The second pair of pixels is read and stored in registers 1928.1929.

4. The input data of the two pixels accumulated in the registers 1920 and 1921 are transferred to the line buffer memory section 1902.
．． 1904 memory address space is written to the next sequential address storage location for the current input line section.

5. Intervore and load the video data of two more pixels into the buffer registers 1928 and 1929 Kml.

A pair of pixels are read out to a predecimation filter 1908, and data of one predecimated pixel is sent to a subsequent predecimated data pack register 19.
Write to 25.

l Further, two pixel data are read out and stored in interpolation buffer registers 1928 and 19251, and interpolated.

& early and slow predecimation registers 1924
．． 1902.19 Backup memory section 1902.19 to back up data of two predecimated pixels that had been accumulated before 1925.
Write to 04. The explanation of the synchronization and output operations of the buffer register shown in FIG. 19 will be omitted for the sake of convenience. However, such synchronization and gating operations can be easily implemented according to the operations described above.

Predecimation filter 1908 performs 2:1 compression each time data passes through it. This operates cyclically in the same way that predecimation filter 700 operates. First, a full-size copy of one scanline's data is passed through filter 1908 and reduced to half-size.

The second half-size copy is reduced to 1/4 size, and this 1/4 size is further reduced to 1/8 size. Further size reductions are of course possible, but are not done in this embodiment of the invention. Predecimation filter 1908 is 3/32.8/32.10/12
．． It is advantageous to implement it as a 5-point filter using a series of weighting factors of 8/32 and 3/32.

The operation of interbolation decimation filter 1910 is substantially the same as the operation of interbolation decimation filter 800 shown in FIG. 10, except that coefficient store 1932 outputs weighting coefficients to multiplier 1933. This multiplier changes the weight according to the relative position of the data of one pixel among all the pixels, and implements the filter function without using the barrel shifter 810, and pre-arranges the video data to perform the predetermined filter function. Align weights. In fact, this relative pixel data coincides with the frequency of two pixel data received every nanosecond. Since filter 1910 is a 4-point filter, it outputs one pixel of data every 280 nanoseconds, which corresponds to the 1/4 sampling frequency and bandwidth of the chroma data.

At the end of the first memory subcycle, after storing the video data of two pixels in the buffer registers 1928 and 1929, the multiplier 1933 stores the value of the pixel stored in the register 1928 in the second memory subcycle. Multiply the coefficient value from coefficient storage 1932 and write the result to register 194 at the end of subcycle 2.
0K accumulates.

At the same time, the accumulator register 1942 is cleared at the end of subcycle 2. In memory subcycle 3, the line buffer sections 1902 and 1904 output interbolation decimation data for two more pixels, and the multiplier 1933 adds a new coefficient given from the coefficient store 1932 to the value of the pixel data stored in the register 1929. Multiply. At the end of subcycle 3, the data of the two new pixels are transferred to the buffer register 192B, at which time the output of the multiplier 19s5 is transferred to the register 1940, and the output of the adder 1944 is transferred to the register 1940& and the accumulator 1942. represents the sum of the contents of the accumulator 1942
will be forwarded to.

Since accumulator 1942 was previously cleared, the contents of register 1940 are accumulated in accumulator 1942 in this case. This represents the first pixel of a 4 point filter cycle.

In memory subcycle 3, multiplier 1933 multiplies the third pixel of this cycle to Fi register 1928 by an appropriate coefficient, and adder 1944 adds the first pixel of the cycle stored in register 1942 to register 194.
Add to the second pixel of the cycle that has accumulated 0K. At the end of memory subcycle 4 bK, the third pixel is accumulated in register 1940 IF and the sum of the first two pixels is accumulated in accumulator 1942.

Press the button on memory subcycle 5, line buffer 190
2.1904 reads out another pair of pixels, this time multiplier 1933 multiplies the previously stored pixel in register 1929 by its appropriate coefficient, and adder 1944 multiplies the first pixel stored in accumulator 1942. The sum of the two pixels and the third pixel stored in register 1940 is generated. At the end of the fifth memory cycle, the sum of the three pixels at the output of the adder 1944 is accumulated in the accumulator register 1942, and the fourth weighted pixel is multiplied by the register 19404Cil for the next filter cycle of raw paddy. Two pixels are stored in buffer registers 1928.1929.

In memory subcycle 6, multiplier 1933 multiplies the pixel data in register 1928 by the appropriate coefficient from store 1932, and adder 1944 adds the sum of the three pixels accumulated in register 1942 to register 1940. Add to the fourth weighted pixel. At the end of memory cycle 6, the four pixel sum output from adder 1944 is loaded into output buffer register 1946, accumulator register 1942 is cleared, and the first weighted pixel of the second output pixel is register 1
940.

In this manner, the interbolation decimation filter cycle described above is repeated, with two 280 nanosecond filter cycles occurring with each 560 nanosecond memory cycle. The magnitude of the weighting performed by the coefficient store 1932 is selected to provide the desired filter function, which depends on the particular full size t or partial size predecimation t' being utilized as the source data.
The amount of further reduction or enlargement in size by the interpolation filter 1910, the source address for the button and the pixel. Having described various configurations of the digital special effects system and digital transformation system according to the invention, the invention It is not limited to. Therefore, any modifications, variations and equivalent constructions within the scope of the appended claims should be considered to fall within the scope of the invention.

[Brief explanation of the drawing]

FIG. 1 is a block diagram representing a space transformation system according to the present invention, FIG. 2A, FIG. 2B, and FIG.
Figure C and Figure 2D are explanatory diagrams necessary for understanding transposition, Figure 3 is a block diagram representing the spatial transformation system shown in Figure 1, and Figure 4 is a block diagram of the spatial transformation system shown in Figure 1. 5 is a block diagram showing a transposing frame store; FIG. 5 is a diagram showing a memory map of the transposing frame store shown in FIG. 4; FIG. 6 is a schematic block diagram showing an addressing circuit of the transposing frame memory shown in FIG. 4. , FIG. 7A and FIG. 7B are block diagrams showing a deinterlace filter, FIG. 8 is a block diagram showing a predecimator, FIG. 9 is a block diagram showing a filter of the predecimator shown in FIG. FIG. 11 is a schematic block diagram of a vertical source address generator; FIG. 12 is a schematic block diagram of a horizontal source address generator; FIG. 13 is a schematic block diagram of a horizontal source address generator; FIG. 13 is a schematic block diagram of a horizontal source address generator; FIG. 14 is a block diagram showing the control panel of the system shown in FIG. 13. FIG. 15 is a block diagram showing the horizontal transposition memory shown in FIG. 13. FIG. 16 is a block diagram showing the control panel of the system shown in FIG. 17 is a block diagram showing the address timing circuit of the field store memory shown in FIG. 16; FIG. 18 is a motion detection deinterlacing circuit for the system shown in FIG. 13. Block Diagram Illustrating a Filter FIG. 19 is a block diagram illustrating an advantageous embodiment of the chroma fretesimation and interbolation decimation filter of the system shown in FIG. In the figure, 10... Spatial transformation systems 12-14... Color component processor 18... Horizontal/vertical transposing memory 20... Vertical transformation memory 24... Horizontal transformation system 26... Transformer 7 ohm convoser and 7 actuator 28...Vertical address generator 30...Horizontal address generators 50-52...Field buffer 54, 56...Field multiplexer 600...
- Dinterlace filter 700... Bridecimation filter 800... Interbolation decimation filter 900... Transposing memory 1300...
Digital special effects system 1500...Horizontal/vertical tone 2 posing memory 1600.1700...Field store memory 18
00...Motion detection dinterlacing filter 1900...Chroma pre-decimation and interpolation decimation filter Figure 1/w, IH 1310 9\ Procedural amendment (voluntary) 16 Cases 1990 Patent Application No. 152498 2. Name of the invention: Method and device for distorting images 3. Relationship with the case of the person making the amendment. Patent applicant name: Ampex Corporation 4゜ Representative Tanuki Written amendment to the written description of the specification. (Method) % formula % Method and device for spatially transforming an image Relationship with the person who makes 3° correction

Claims (1)

[Scope of Claims] 1. A method of electronically deforming an input data sample corresponding to a pixel of an image, wherein the deformation is carried out dimensionally with respect to each other in a multidimensional coordinate system in which a plurality of coordinates indicate respective coordinate directions. a transformation of a pixel of said image from an original position to a destination position by dependent spatial transformations, said method comprising: transforming said interdependent transformations into transformations for respectively repositioning said pixels in each of said coordinate directions; dividing into a plurality of corresponding elements, at least one of said elements being a function of said plurality of coordinates, and applying each of said elements sequentially and separately to said data sample in the other coordinate direction; generating a deformed data sample according to a respective deformation corresponding to the repositioning of each pixel in the coordinate direction indicated by said element, without relocation, and any successive application of said element is deformed according to the application of a previous element; 3. The method, characterized in that the method is performed on the data samples. 2. A method of electronically transforming an input data sample as claimed in claim 1, wherein a set of electronic signals is generated corresponding to each of said plurality of elements, said elements being elements, the product of which is the interdependent deformation, and the element is applied to the data sample by sequentially and separately electronically applying each of the set of electronic signals to the data sample. The method as described above. 3. A method for electronically deforming an input data sample according to claim 1, wherein the coordinate system is two-dimensional and has first and second coordinates, and the set of electronic signals are first and second sets corresponding to the first and second of said elements, and applying each of said one set of electronic signals includes applying said first set of electronic signals to said input data samples. electronically applied portions corresponding to respective partial deformations corresponding to relocation of respective pixels in respective coordinate directions relative to said first element without relocation in other coordinate directions; generating a partially deformed data sample; and electronically applying the second set of electronic signals to the partially deformed input data sample without relocation to other coordinate directions. , generating fully deformed data samples corresponding to the relocation of each pixel to the destination position in a respective coordinate direction relative to the second element. 4. In the method of electronically deforming an input data sample according to claim 1, the multidimensional coordinate system is a two-dimensional coordinate system in which the first and second coordinates each indicate a position in two coordinate directions. a coordinate system, generating first and second sets of electronic signals corresponding to the first and second elements of the interdependent deformation, respectively;
and a second element is the interdependent transformation, each of the first and second elements being a function of both the first and second coordinates, repositioning the pixel in each of the coordinate directions. applying the first set of electronic signals to the input data sample in a respective coordinate direction for the first element without relocation in other coordinate directions; generating partially deformed data samples according to each partial deformation in response to respective pixel rearrangements; and electronically applying a second set of electronic signals to the partially deformed input data samples. fully deformed corresponding to the relocation of each pixel in its respective coordinate direction to said destination position with respect to said second element without relocation in other coordinate directions. The method includes the step of generating a sample of data. 5. A method for electronically deforming input data samples according to claim 4, wherein the data samples correspond to pixels of the image arranged in columns in each coordinate direction, and the data samples correspond to pixels of the image arranged in columns in each coordinate direction, and Said method, characterized in that the sets are applied to data samples of each column independently of data samples corresponding to pixels of another column in the same direction. 6. A method for electronically deforming an input data sample according to claim 4, comprising: storing an input data sample corresponding to the original position in a first memory; reading the stored input data samples from the Lth memory for each column in each direction; storing the partially transformed data samples in a second memory; reading the stored partially transformed input data samples from the second memory for each column in each corresponding direction; and reading the first set of electronic signals from the first memory. the second set of electronic signals is applied to partially deformed data samples read from the second memory;
Said method. 7. A method for electronically transforming an input data sample according to any one of claims 1 to 6,
The method, wherein the input data samples correspond to pixels of an image arranged in raster scan order, and the directions correspond to vertical and horizontal scan directions. 8. The method of electronically transforming an input data sample according to any one of claims 1 to 7, wherein the coordinate direction of the target image is changed from the coordinate direction of the original image. Said method, characterized in that. 9. A method of electronically deforming an input data sample according to claim 8, wherein at least one of the first and second elements comprises deformation in the coordinate direction; By applying at least one of
The method, characterized in that a coordinate change between the original image and the target image is performed, substantially maintaining the resolution of the data samples as the repositioning occurs. 10. In the method of electronically deforming an input data sample according to any one of claims 1 to 9, by applying one element to the data sample, each direction is changed according to the respective deformation. Said method, characterized in that the data sampling rate and the data position in the data are varied. 11. A method for electronically transforming an input data sample according to any one of claims 1 to 10, wherein each of the pixels corresponds to a coordinate position of an original image and a target image, respectively. and generate deformed data samples by interpolating the deformed data samples in each coordinate direction, and each of the deformed data samples has a coordinate position corresponding to the coordinate position of the deformed data sample in each coordinate direction. The method is characterized in that the filter function of the plurality of data samples is transformed correspondingly to positions adjacent to . 12. A method of electronically deforming an input data sample according to claim 11, wherein the filter function is a function of the coordinate position corresponding to the coordinate position of the deformed data sample with respect to the adjacent position. The method as described above. 13. A method of transforming a data array defining an input data value from an original position to a target position by a plurality of successive transformations, wherein the position is defined by a multidimensional coordinate system in which a plurality of coordinates represent a position in each coordinate direction. electronically deforming the input data value in the defined and selected one coordinate direction to generate deformed data values corresponding to the deformed data array;
Continuously deforming the already deformed data values in each additional coordinate direction until the deformation is performed in all coordinate directions,
generating deformed data values at target locations corresponding to a fully deformed data array, at least one of said data value deformations being a function of said plurality of coordinates of a multidimensional coordinate system; Said method, characterized in that said deformed data values have the same coordinates as they had before said deformation, except in each coordinate direction. 14. The method of deformation according to claim 13, wherein the data values correspond to pixels representing an image, and each deformation of the data values is a function of the plurality of coordinates of a multidimensional coordinate system, and the input data A method as described above, characterized in that each successive transformation of the data value after the transformation of the value is performed on the data value transformed according to the previous transformation. 15. In the deformation method according to claim 14, the coordinate system is two-dimensional and has first and second coordinates, and the input data value is deformed in the first coordinate direction. generates a first deformed data value representing a partially deformed image, and a continuous deformation process generates a second deformed data value with respect to said first deformed data value.
, and generating second deformation data values at a target position corresponding to a fully deformed image. 16. In the deformation method described in claim 14, the deformation from the original position to the target position is a perspective projection deformation that transforms data samples corresponding to pixels of the original two-dimensional image into a two-dimensional target image. , each dimension corresponds to a respective coordinate direction, and the data samples corresponding to the partially transformed intermediate target image are a series of data samples corresponding to pixels along each of the intermediate target columns of the plurality of first coordinates. a series of data samples for each intermediate target column in a first direction, the series of data samples being formed by electronically generating data samples for each intermediate target column in a first direction according to a deformation according to a predetermined perspective projection of said original image. a series of data samples corresponding to pixels in each column of the original image, the data samples corresponding to the fully deformed final destination image being a function of a plurality of second data samples across the columns in the first direction. is formed by electronically generating a series of data samples corresponding to pixels along each of the target columns of coordinates of said original image, with the series of data samples for each intermediate target column in the second direction the second according to the deformation according to the predetermined perspective projection;
said method, characterized in that said method is a function of a series of data samples corresponding to pixels of respective columns of the original image in the direction of . 17. The deformation method according to any one of claims 13 to 16, characterized in that the deformation rearranges data values in respective coordinate directions.
Said method. 18. An apparatus for electronically deforming an input data sample corresponding to a pixel of an image, wherein the deformation is performed by spatial deformation that is dimensionally interdependent in a multidimensional coordinate system in which a plurality of coordinates point to respective coordinate directions; a transformation of a pixel of said image from an original position to a destination position, said apparatus comprising: generating a set of electronic signals corresponding to a plurality of elements corresponding to the transformation for repositioning a pixel in each of said coordinate directions; generating deformation means (26), said elements being elements of said interdependent deformation, the product of which is said interdependent deformation;
at least one of said elements is a function of said plurality of coordinates; and a plurality of application means (20, 20) for sequentially and separately electronically applying each of said set of electronic signals to said data sample.
24, 28, 30), generating deformed data samples according to respective deformations corresponding to relocation of each pixel in the coordinate direction indicated by said element without relocation in other coordinate directions; Apparatus, characterized in that the means are connected in a cascade, so that any successive application of the set of electronic signals is performed on the data samples modified according to the application of previous elements. 19. A device for electronically transforming an input data sample according to claim 18, wherein the multidimensional coordinate system is two-dimensional, and the first and second coordinates are in two respective coordinate directions. a first applying means (20, 28);
and a second application means (24, 30),
applying means for applying said first set of electronic signals to said input data samples, each pixel in a respective coordinate direction for said first element without relocation in other coordinate directions; generating partially transformed data samples in response to each partial transformation in response to the rearrangement of the second set of electronic signals; electronically applied to an input data sample to correspond to repositioning each pixel in a respective coordinate direction relative to the second element to the destination position without repositioning in other coordinate directions; The apparatus is characterized in that it produces fully deformed data samples. 20. A device for electronically transforming input data samples according to claim 19, wherein the data samples correspond to pixels of the image arranged in columns in each coordinate direction, and the data samples correspond to pixels of the image arranged in columns in each coordinate direction, and Apparatus as described above, characterized in that the set is applied to data samples of each column independently of data samples corresponding to pixels of another column in the same direction. 21. A device for electronically transforming input data samples according to any one of claims 18 to 20, wherein the input data samples correspond to pixels of an image arranged in raster scan order; Said device, characterized in that the directions correspond to vertical and horizontal scanning directions. 22. A device for electronically transforming input data samples according to claim 20, comprising first memory means (18) for storing input data samples corresponding to said original positions; first addressing means (28) for sequentially reading out said input data signals from said first memory means in each column in a respective coordinate direction corresponding to an element of said first addressing means (28) for storing said partially transformed data samples; 2
memory means (22); and second addressing means (22) for sequentially reading out the partially transformed data samples from the second memory means in each column in the respective coordinate direction corresponding to the second element. 3
0), said first applying means (20) being connected to apply said first set of electronic signals to data samples read from said first memory means; said application means (24) are connected to apply said second set of electronic signals to partially transformed data samples read from said second memory means. , said device. 23. A device for electronically transforming input data samples according to claim 22, wherein the input data samples correspond to pixels of an image arranged in raster scan order, and the directions are vertical and horizontal scan. Said device, characterized in that it corresponds to a direction. 24. A device for electronically transforming an input data sample according to claim 23, wherein said first applying means (20) is configured to transform data read from said first memory means (18). said second memory means (22) receiving samples and successively producing partially deformed data samples corresponding to vertical columns of said partially deformed image; said second addressing means (30) comprising a vertical/horizontal conversion memory connected to successively receive said partially transformed data samples corresponding to vertical columns of said video; successively reading out said partially transformed data samples corresponding to horizontal columns of partially transformed images; said second application means (24) reading out said partially transformed data samples from said vertical/horizontal transformation memory; the partially-deformed data samples received, and successively generate fully-deformed data samples corresponding to horizontal columns in raster scan order of the fully-deformed video; Said device. 25. A device for electronically transforming input data samples according to claim 24, wherein said first memory means (18) stores data corresponding to horizontal columns in raster scan order of the original video. a horizontal/vertical transformation memory connected to successively receive samples, said first addressing means (28) corresponding to a column of images in a selected direction determined by at least one of said elements; the first application means (20) being connected to receive the data samples read from the horizontal/vertical conversion memory. The device as described above. 26. Apparatus for electronically transforming input data samples according to claim 25, wherein said first addressing means (28) are arranged in said first memory means (1
8) The data samples from 8) are sequentially read out according to the vertical columns of the image for a predetermined transformation, and sequentially read out according to the horizontal columns of the image for other transformations. , said device. 27. A device for electronically transforming input data samples according to claim 22, wherein the input data samples correspond to pixels of an image arranged in raster scan order, and the directions are vertical and horizontal scan directions. corresponding to said first memory means (18) comprising a horizontal/vertical conversion memory connected to receive first video information representing horizontal columns in raster scan order of the original video; The first addressing means (28) reads the video information as vertical columns in raster scan order, and the first applying means (20) reads the first video information output by the horizontal/vertical conversion memory. receiving and performing a vertical transformation thereon to produce second video information representing a raster-scan ordered vertical column of a partially transformed video as a function of the first video information; means (22) comprising a horizontal/vertical conversion memory connected to receive second video information representing a raster scan ordered vertical column of said partially converted video; said second addressing means; (30) reads out the partially transformed video as a horizontal column in raster scan order, and the second application means (24) reads out the second video information output by the horizontal/vertical conversion memory. and performing a horizontal transformation thereon to produce third video information representing a raster-scan ordered horizontal column of the completely transformed video as a function of the second video information. Said device. 28. A device for electronically transforming input data samples according to any one of claims 22 to 27, wherein the second memory means (22) stores at least one frame of video information. said device, characterized in that it has a capacity sufficient to 29. A device for electronically transforming input data samples as claimed in claim 28, wherein said first memory means (18) has a capacity sufficient to store at least one frame worth of video information. The device characterized in that it comprises: 30. A device for electronically deforming an input data sample according to any one of claims 18 to 29, wherein at least one of the first and second elements causes the deformation in the coordinate direction. and the first and second application means (
at least one of 20, 24) comprising means for performing a coordinate change between said original image and a target image and substantially maintaining resolution of said data sample as said repositioning occurs. The said device. 31. In an apparatus for transforming a data array that defines an input data value from an original position to a target position by a plurality of continuous transformations, said position is defined by a multidimensional coordinate system in which a plurality of coordinates represent a position in each coordinate direction. a first deforming means (20, 26, 28) for electronically deforming input data values in a defined and selected one coordinate direction to generate deformed data values corresponding to a deformed data array; another deforming means ( 24, 26, 30),
At least one of the transformations of the data value is a function of the plurality of coordinates of a multidimensional coordinate system, and the first transformation means and the other transformation means are connected in a cascade to completely transform the data. means for generating deformed data values at target positions corresponding to the array, wherein said deformed data values generated by each deformation have the same coordinates as they had before said deformation, other than in each coordinate direction; The device characterized in that it comprises: 32. A deformation device according to claim 31, characterized in that the deformation rearranges data values in respective coordinate directions. 33. An apparatus for electronically transforming input data samples corresponding to pixels of an image arranged in horizontal and vertical columns and ordered in raster scan order, said transformation corresponding to a spatial transformation from an original position to a target position. and the device is connected to receive data samples corresponding to the original positions received successively corresponding to horizontal columns of the original video in raster scan order, and to store the data samples. a horizontal/vertical conversion memory (18); and vertical addressing means for successively reading input data samples stored from said horizontal/vertical conversion memory corresponding to horizontal or vertical columns of the video selected for each transformation. (28) and applying the selected electronic signal to the data samples read from the horizontal/vertical transformation memory according to the vertical transformation element to partially vertical transformation means (20, 26) for successively producing partially transformed data samples; and vertical/horizontal transformation memory (20, 26) connected to receive and store said partially transformed data samples.
2); horizontal addressing means (30) for sequentially reading out said stored partially transformed data samples corresponding to horizontal columns of said partially transformed video; applying selected electronic signals to the partially deformed data samples read from the vertical/horizontal conversion memory to fully deform the image corresponding to horizontal columns of the fully deformed image in raster scan order. Horizontal transformation means (2
4, 26). 34, configured to receive and store data samples corresponding to Y, I and Q video elements of successive fields of an interlaced color television video signal, corresponding to the vertical or horizontal scan direction selected for each transformation; , first, second and third conversion memories comprising address circuits connected to control storage and sequential readout of video data samples in horizontal raster scan order; first, second, and second circuits connected to receive Y, I, and Q video data samples, respectively, from the conversion memory of the converter and output a full frame of video data samples at field rate for each field of the received video data samples. a third deinterlacing filter (600, 1332); receiving the Y, I and Q video data samples and a series of addresses indicating a series of data samples within the video data samples to be selected for output; first, second and third interpolating decimation filters (8) that output Y, I and Q data samples as a function of a plurality of video data samples arranged around the
00, 1326) and sequentially receive and store Y, I and Q data samples of successive fields of video data samples corresponding to vertical columns from said first, second and third interpolation decimation filters; fourth, fifth and sixth transformation memories (900, 1338) for sequentially outputting said data samples corresponding to directional columns; Y, I and Q video data samples selected for output; and a series of addresses indicating a series of data samples within the video data sample, and output and transform Y, I, and Q data samples as a function of a plurality of video data samples arranged around each addressed data sample. fourth, fifth, and sixth interpolating decimation filters (906, 1344) that output a series of Y, I, and Q video data samples in raster scan order representing the video image;
and generating a series of addresses for the first, second and third interpolation decimation filters in accordance with the received command, and further generating a series of addresses for the fourth, fifth and sixth interpolation decimation filters. A control circuit (908, 912, 916; 1326,
1328, 1318, 1314).