GB2246014A

GB2246014A - Capacitors for dram cells

Info

Publication number: GB2246014A
Application number: GB9020480A
Authority: GB
Inventors: Su-Han Choi; Seong-Tae Kim; Kyung-Hun Kim
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1990-07-12
Filing date: 1990-09-19
Publication date: 1992-01-15
Also published as: FR2664742A1; IT1243102B; DE4029070A1; JPH0472757A; IT9021516A1; GB9020480D0; KR930006144B1; DE4029070C2; IT9021516A0; KR920003557A

Abstract

A combined stack-trench type capacitor comprises a substrate 100, a transistor 1-3. a trench 10a, 10b, a conductive layer 13 serving as the first electrode of the capacitor and a diffusion blocking layer 12 disposed between the substrate 100 and the conductive layer 13 formed over the surface of the trench. By using this structure for a capacitor, a punchthrough phenomenon which otherwise could occur between trenches, and possible soft errors resulting from alpha particles may be prevented. <IMAGE>

Description

A- 1 SEMICONDUCTOR CAPACITOR DEVICE AND MANUFACTURING METHOD THEREOF The

present invention relates to a semiconductor device and a manufacturing method thereof, and particularly, although not exclusively, to a semiconductor capacitor device and method of manufacture thereof.

Recently, developments in semiconductor memory devices have led to such devices having a large memory capacity. In particular by forming an individual memory cell having a single capacitor and a single transistor, considerable progress has been achieved in DRAM (Dynamic Random Access Memory).devices allowing increasingly high is device densities to be achieved.

Conventional DRAM devices have developed from using a conventional planartype capacitor cell structure to the use of a three-dimensional stacktype capacitor cell structure or a trench-type capacitor cell structure, thereby enabling the manufacture of 4 Mbit capacity DRAMIS. However, there are several disadvantages in adopting the stacked or planar-type technologies to produce a 16 Mbit or higher capacity DRAM. In particular, a step coverage problem occurs in the conventional stacktype capacitor cell due to the structure of the capacitor which is stacked on a transistor. In conventional trench type capacitor cells, leakage current problems between the trenches occur whenever the capacitors are scaled down in size, so that the trench type capacitor is unsuitable for application in a 64 Mbit DRAM.

Therefore, a three dimensional combined stack-trench type capacitor which is aimed at solving the above mentioned problems in large capacity DRAM's has been proposed. A conventional manufacturing process for the combined stacktrench type capacitor is illustrated in "4..

Figures 1A to 1D of the accompanying drawings, and will now be described below in detail.

Figure 1A illustrates a process for forming a transistor on a semiconductor substrate 100. The transistor is an element of a semiconductor memory cell. Two such transistors are shown adjacent to each other in figures 1A to 1D. An active region is defined by growing a field oxide layer 101 on the semiconductor substrate

100. A gate electrode 1, a source region 2 and a drain region 3 of a transistor, are formed on the active region, and a first conductive layer 4, e.g., an impurity-doped first polycrystalline silicon layer, is formed on a predefined portion of the field oxide layer 101 such that it is connected to a gate electrode of a transistor which is disposed adjacently to the field oxide layer. A first insulating layer 5, e.g., an HTO (High Temperature Oxide) layer having a thickness of about 1500A - 4000A, is formed over the entire surface of the aforesaid structure.

Figure 1B of the accompanying drawings illustrates a process for forming an opening 6, over the source region 2 and substrate 100 to expose a portion of the source region 2. A photoresist pattern PR is formed on the first insulating layer 5 through steps of coating the aforesaid structure with a photoresist masking, exposing and developing the photoresist. The opening 6 is then formed by etching the first insulating layer 5 using the photoresist pattern PR.

Figure 1C of the accompanying drawings illustrates a process for forming a trench 10 in the source region and substrate. Referring to Figure 1C, after the photoresist pattern has been removed, the trench is formed by etching i 3 - is the substrate using an anisotropic-etching process. the first insulating layer 5 is used as a mask.

Figure 1D of the accompanying drawings illustrates a process for forming a second conductive layer 13 to serve as a first electrode of the capacitor. The secondconductive layer 13 is formed by forming a second polycrystalline silicon layer having a thickness.of about 500A - 4000A inside the trench and over the first insulating layer 5 by means of a low pressure chemical vapour deposition (LPCVD) reactor and thereafter implanting impurities into the second polycrystalline silicon layer. The impurities implanted into the second polycrystalline silicon layer are then diffused into the substrate around the trench 10 during an annealing process, thereby forming an impurity diffused region 14.

After the process illustrated in Figure 1D has been performed, a first electrode pattern of the capacitor is formed by etching the second conductive layer, and a dielectric film is formed to cover the surface of the first electrode pattern. A third conductive layer, serving as a second electrode of the capacitor, is formed on the dielectric film, whereby formation of the conventional combined stack-trench type capacitor is completed.

In the manufacturing method for the conventional combined stack-trench type capacitor described above, because the second conductive layer, which is used as the first electrode of the capacitor, is formed by an annealing process after implanting impurities into the polycrystalline layer, the impurity diffused region is formed around the trench. Accordingly, a punchthrough phenomenon occurs between trenches due to the impurity diffused region and a depletion region is formed in the region between the trenches where the punchthrough occurs. As a result, the breakdown voltage between devices is lowered.

According to one aspect of the present invention, there is provided a capacitor for an integrated circuit, in which an electrode of the capacitor is covered or partially covered by a barrier material for the prevention of diffusion out of said electrode or out of a surface thereof.

Preferably said electrode is formed on a semiconductor substrate, and the barrier material is arranged there between for prevention of diffusion between said electrode and said substrate.

Preferably said capacitor is arranged in a recess or trench in said substrate.

Preferably said recess or trench has a depth substantially in the range 1 to 3pm.

Said diffusion may be diffusion of dopants and/or impurities, and/or charge carriers.

Preferably said barrier material is a nitride.

The capacitor may be formed by chemical vapour deposition.

Preferably said barrier material has a thickness substantially in the range of 50 to 500A.

Preferably a gap in the barrier material is provided for connection of said electrode to a source, drain, gate, channel, emitter, base, or collector region of a transistor.

Preferably said electrode is of polycrystalline' silicon.

Preferably said electrode has substantially in the range 1000.k - 2000A.

a thickness According to another aspect of the present invention there is provided a method of manufacturing a capacitor for an integrated circuit, said circuit having a semiconductor substrate and one or more active regions, said method comprising the following stages a to e; a) forming a first recess or trench in an active region of said semiconductor substrate; b) forming a protective layer on and/or over exposed parts of the active region in said first recess or trench; C) removing a portion of said protective layer; d) forming a second recess or trench connected with said first recess or trench; e) forming a barrier material on a surface of said second recess or trench and on a remaining portion of said protective layer; and f) selectively removing said remaining portion of the protective layer.

Preferably said protective layer is formed on sidewalls of said first recess or trench, and on an upwardly facing surface of said first recess or trench, and a portion of said protective layer is then removed from said upwardly facing surface.

Preferably the removal of said portion of the protective layer is performed by anisotropic etching of the protective layer.

Preferably said protective layer is a nitride.

Preferably said protective layer has a thickness substantially in the range 50 to 200A.

Preferably said first and/or second recess or trench has or have a depth substantially in the range 1 to 3pm.

Said active region may include a source, drain, gate, channel, emitter, base, or collector region.

Preferably said barrier material is an oxide layer having a thickness substantially in the range 50 to 500A.

Preferably the method further comprises the steps of forming a first electrode layer in said first and/or second recess(es) or trench(es).

Preferably said electrode layer is a polycrystalline layer having a thickness substantially in the range 1000 to 2000A.

Preferably the method further comprises the steps of forming a dielectric layer on said electrode layer, and forming a second electrode layer on said dielectric layer.

The invention includes a semiconductor device comprising: a field oxide layer selectively formed on a first conductivity type semiconductor substrate to define an active region; a gate electrode electrically insulated on the active region; a source region and a drain region 1.

7 - 7 formed at respective sides of said gate electrode and'on the surface of said semiconductor substrate; a first conductive layer formed to connect with a gate electrode of an adjacent memory cell on any predetermined portion of said field oxide layer; a trench formed in said semiconductor substrate and within said source region; af irst insulating layer to insulate said gate electrode and said first conductive layer; and a second conductive layer formed inside said trench and on said first insulating layer; wherein a diffusion blocking layer is provided between said semiconductor substrate and said second conductive layer formed over the surface of said trench.

Preferably said diffusion blocking layer consists of an oxide layer.

Preferably said first and said second conductive layers consists of impurity-doped polycrystalline silicon layer.

The invention also includes a method for manufacturing a semiconductor device comprising in the cited order the steps of:

defining an active region by growing a field oxide layer on a first conductivity type semiconductor substrate; forming a gate electrode, a source region and a drain region of a transistor on said active region, forming a first conductive layer on any predetermined portion of said field oxide layer, and forming a first insulating layer on the resultant structure; forming a f irst trench by applying a mask on said first insulating layer disposed over said source region; 8 - forming a nitride layer on the resultant structurb; leaving said nitride layer only on the walls of said first trench; forming a second trench to connect with said first trench; forming a diffusion blocking layer; removing said nitride layer formed on the walls of said first trench; and forming a second conductive layer on the resultant structure.

Preferably said step of forming a first trench by applying a mask on said first insulating layer disposed over said source region comprises the steps of:

forming a photoresist pattern on said first insulating layer and forming an opening to expose a portion of said source region by etching of the first insulating layer with the application of said photoresist pattern; and anisotropic etching of said semiconductor substrate as deeply as the depth of said source region by using said first insulating layer as a mask, after removing said photoresist pattern.

Preferably said nitride layer is formed by low pressure chemical vapor deposition, thereby forming a thickness of about 50K - 200A.

Preferably said step of leaving said nitride layer only on the walls of said first trench is performed by etching of the nitride layer on the resultant structure obtained by the preceding steps.

Preferably said step of forming the second trench'to connect with said first trench is carried out by anisotropic etching of said semiconductor substrate having said first trench therein, with a predetermined depth.

Preferably said predetermined depth is about 1pm 3pm.

Preferably said step of forming diffusion blocking layer is carried out by thermal growing of the oxide layer having a thickness of about 50A - 500A.

Preferably said step of removing said nitride layer is carried out by a wet etching process.

The invention includes a capacitor comprising: a field oxide layer selectively formed on a first conductivity type semiconductor substrate to define an active region; a gate electrode electrically insulated on the active region; a source region and a drain region formed at respective sides of the gate electrode int he surface of the semiconductor substrate; a first conductive layer formed to connect with - a gate electrode of a memory cell adjacent to any predetermined portion of the filed oxide layer; a second conductive layer formed on both the surface of the trench and the first insulating layer; and a diffusion blocking layer provided between the semiconductor substrate and the second conductive layer formed over the surface of the trench.

The invention also includes a method of manufacturing a capacitor, said method comprising:

a first process of defining an active region by growing a field oxide layer on a first conductivity type semiconductor substrate; a second process of forming a gate electrode, a source region and a drain region of a transistor which is an element of a memory cell on the active region, forming a first conductive layer on any predetermined portion of the field oxide layer, and forming a first insulating layer on the resultant structure obtained by the above; a third process of forming a first trench by applying a mask on the first insulating layer disposed over the source region; a fourth process of forming a nitride layer on the structure obtained after performing of the third process; a fifth process of leaving the nitride layer on the inside walls of the first trench; a sixth process of forming a second trench to connect with the first trench; a seventh process of forming a diffusion blocking layer after performing of the sixth process; kl.

11 - an eighth process of removing the nitride laer formed on the inside walls of the first trench; and a ninth process of forming a second conductive layer on the structure obtained by performing the eighth process.

By way of example, a specific embodiment according to the present invention, and a specific method according to the present invention will be described with reference to Figures 2 and 3 of the attached drawings, in which:

Figure 2 is a sectional view -of a combined stacktrench type capacitor according to a specific embodiment of the present invention; and Figures 3A to 31 are sectional drawings which show an example of a process according to a specific method of the present invention for manufacturing a combined stack- trench type capacitor.

Referring to Figure 2 of the accompanying drawings, the combined stacktrench type capacitor comprises a field oxide layer 101 selectively formed on a first conductivity type semiconductor substrate 100 to define an active region; a gate electrode 1 formed over, and electrically insulated from, the active region; a source region 2 and a drain region 3 formed on the active region at respective sides of the gate electrode 1 in the surface of the semiconductor substrate; a first conductive layer 4 formed on a predetermined portion of the field oxide layer 101 such that it is connected to a gate electrode of a memory cell disposed adjacently to the field oxide layer; trenches 10a and 10b formed in the source region 2 and the semiconductor substrate 100; a first insulating layer 5 1 1 1 k formed over the gate electrode 1 and the first conductive layer 4; a diffusion blocking barrier layer 12 formed on the surface of the trench lob in the semiconductor substrate loo and on the f irst insulating layer 5, but not on the surface of the trench loa in the source region 2; and a second conductive layer 13 formed on the diffusion blocking barrier layer 12 and on a side or sides of the source region 2 in the trench loa.

Figure 3A illustrates a process for forming a transistor on a first conductivity type semiconductor substrate 100, wherein an active region is defined by growing a field oxide layer 101 on the semiconductor substrate loo by means of selective oxidation. A gate oxide layer, having a thickness of about 100A - 200A, is formed on the active region, and a first conductive layer, e.g. an impurity-doped first polycrystalline silicon layer, is formed to serve as a gate electrode 1 of a transistor on the gate oxide layer, and at the same time, a first conductive layer 4, which is for example also the impurity-doped first polycrystalline silicon layer, is formed on a predetermined portion of the field oxide layer 101 to be connected to a gate electrode of a memory cell which is adjacent to the field oxide layer. A source region 2 and a drain region 3 are formed by ion implantation into the surface of the semiconductor substrate on respective sides of the gate electrode 1. A first insulating layer 5, which is for example a High Temperature oxide (HTO) layer having a thickness in the range of about 1500A - 4000A is formed over the entire surface of the above described structure.

Figure 3B illustrates a process for forming an opening 6 in the first insultating layer 5. Firstly a photoresist pattern PR is formed on an upper surface of 9 1 the first insulating layer 5 through steps of photoresist coating, mask exposure and development. Then the opening 6 is formed by etching the first insulating layer 5 using the photoresist pattern PR, thereby exposing a portion of 5 the source region 2, Figure 3C illustrates a process for forming a first recess or trench 10a in the source region 2. After the photoresist pattern PR is removed, a surface of a first trench 10a having upright sidewalls and a horizontal upwardly facing bottom surface is formed by anisotropicetching of the substrate to a depth equal to that of the source region 2, using the first insulating layer 5 as a mask.

Figure 3D illustrates a process for forming a protective nitride layer 11. The nitride layer 11, having a thickness of about 50 - 200A is formed by means of low pressure chemical vapour deposition (LPWD) onto the surface of the structure obtained by the processes described hereinabove with reference to Figure 3C. The nitride layer covers the surface of the first trench 10a, as well as the surface of the first insulating layer 5.

Figure 3E illustrates a process for etching the nitride layer 11, on the bottom surface of the trench 10a, and on the upper surface of the first insulating layer 5. The nitride layer is etched by an anisotropic etching process, such that the nitride layer 11 is left only on the side walls of the first trench 10a, i.e., on the side walls of the exposed source region, as shown in Figure 3E. Portions of the nitride layer which were formed on the upper surface of the first insultating layer 3 in Figure 3D are removed. Nitride which covered the upwardly facing i bottom surface of the first trench loa is also removed'so that the substrate loo is exposed.

Figure 3F illustrates a process for forming a second recess or trench lob in the substrate, at the bottom of the trench 10a. The second trench lob, having a depth ofabout lpm - 3pm, is etched in the semiconductor substrate loo such that the second trench lob is connected to the first trench loa. The protective nitride layer 11 formed on the side walls of the first trench remains intact.

Figure 3G illustrates a process for forming a diffusion blocking barrier layer 12 on a surface of the second trench lob and on an upper surface of the first insulating layer 5, after the trench lob has been formed, as shown in Figure 3F. The diffusion blocking barrier layer 12, which is for example an oxide layer having a thickness of about SOA - 500A, is thermally grown. The protective nitride layer 11 which remains on the side walls of the first trench prevents thermal growth of an oxide layer on the side walls of the trench 10a and source region 2. The diffusion blocking barrier layer 12 grows only on the surface of the second trench lob and on the first insulating layer 5.

Figure 3H illustrates a process for removing the remaining nitride layer formed on the side walls of the first trench. The nitride layer formed on the side walls of the first trench is selectively removed by a wetetching method, thereby exposing the walls of the first trench, i.e., the source region 2 is exposed on the side walls of the trench 10a.

Figure 31 illustrates a process for forming a second conductive layer 13 for serving as a first electrode of the capacitor. The second conductive layer 13 is provided by forming a second polycrystalline silicon layer having a thickness of about 1000A - 2000K, and thereafter implanting dopants or impurities thereinto. In the above process, the second conductive layer 13 also covers and is connected to the side walls of the trench i0a and sourceregion 2, from which the nitride layer has been removed by the previous process.

is The combined stack-trench type capacitor is completed by further stages (not illustrated) of forming a dielectric film and a third conductive layer, which serves as a second electrode of a capacitor, over the second conductive layer.

With a capacitor structure according to the specific embodiment of the present invention, it is possible that the formation of an impurity diffused region around a trench formed in a semiconductor substrate can be blocked by forming a diffusion-blocking barrier layer over the surface of the trench. In this manner, the above described specific embodiment of the present invention may have an advantage that the diffusion blocking layer provides a barrier material to the diffusion of dopants inot the substrate and a punchthrough phenomenon occurring between adjacent trenches and errors resulting from alpha particles can be prevented. Therefore, the reliability and the electrical characteristics of a capacitor according to a specific embodiment of the present invention may be improved.

It will be appreciated by a person skilled in the art, that a diffusion blocking barrier layer as described in the afore said specific embodiment and/or method may not only prevent the out-diffusion of dopants and/or impurities from an electrode, but may also 'or alternatively prevent diffusion of charge carriers into out of the electrode.

Further, because a diffusion blocking layer is not formed on the source region where the first trench is formed, the source region and the second conductive layer may become connected to each other when the. second conductive layer is formed. The second conductive layer can connect electrically to the source region, enabling the second conductive layer to serve as the first electrode of the capacitor.

The specific embodiments and methods of the present invention may have an advantage of providing a capacitor having a combined stack-trench type structure wherein, to solve the above described problems of the conventional capacitors and/or manufacturing techniques, an oxide layer is formed over the surface of a trench, thereby preventing occurrences of a punchthrough phenomenon between trenches and reducing soft errors due to alpha particles in a depletion region of a memory cell.

Whilst the specific embodiment and method hereinbefore described refer to a transistor having a source and drain region, it will be understood that the invention may equally be applied to a transistor having an emitter, collector or base region, or a functionally equivalent region of - for example a diode, or other electronic device. Additionally, the active region may include a connection to a resistor, other capacitor or other electronic device.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to 1 1 k 1 this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims

1. A capacitor for an integrated circuit, in which an electrode of the capacitor is covered or partially covered by a barrier material for the prevention of diffusion out of said electrode or out of a surface thereof.

2. A capacitor according to claim 1, wherein said electrode is formed on a semi-conductor substrate, and the barrier material is arranged there between for prevention of diffusion between said electrode and said substrate.

3. A capacitor according to claim 2, which is arranged in a recess or trench in said substrate.

4. A capacitor according to claim 3, in which said recess or trench has a depth substantially in the range 1 to 3pm.

5. A capacitor according to any one of the preceding claims, wherein said diffusion is diffusion of dopants and/or impurities, and/or charge carriers.

6. A capacitor according to any one of the preceding claims in which said barrier material is a nitride.

7. A capacitor according to any one of the preceding claims, which is formed by chemical vapour deposition.

8. A capacitor according to any one of the preceding claims in which said barrier material has a thickness substantially in the range of 50 to 500A.

9. A capacitor according to any one of the preceding claims in which a gap in the barrier material is provided for connection of said electrode to a source, drain, gate, channel, emitter, base, or collector region of a 5 transistor.

10. A capacitor according to any one of the preceding claims in which said electrode is of polycrystalline silicon.

11. A capacitor according to any one of the preceding claims, wherein said electrode has a thickness substantially in the range 1000A - 2000A.

12. A method of manufacturing a capacitor for an integrated circuit, said circuit having a semiconductor substrate and one or more active regions, said method comprising the following stages a to e; a) forming a first recess or trench in an active 20 region of said semiconductor substrate; b) forming a protective layer on and/or over exposed parts of the active region in said first recess or trench; C) removing a portion of said protective layer; d) forming a second recess or trench connected with said first recess or trench; e) forming a barrier material on a surface of said second recess or trench and on a remaining portion of said protective layer; and f) selectively removing said remaining portion of the protective layer.

13. A method according to claim 12, in which said protective layer is formed on sidewalls of said first recess or trench, and on an upwardly facing surface of j said first recess or trench, and a portion of said protective layer is then removed f rom said upwardly facing surface.

14. A method according to claim 12 or 13, in which removal of said portion of the protective layer is performed by anisotropic etching of the protective layer.

15. A method according to claim 12, 13 or 14, in which 10 said protective layer is a nitride.

16. A method according to any one of the claims 12 to 15 in which said protective layer has a thickness substantially in the range 50 to 200A.

17. A method according to any one of claims 12 to 16, in which said first and/or second recess or trench has or have a depth substantially in the range 1 to 3pm.

18. A method according to any one of claims 12 tO 17, in which said active region includes a source, drain, gate, channel, emitter, base, or collector region.

19. A method according to any one of claims 12 to 18 in which said barrier material is an oxide layer having a thickness substantially in the range 50 to 500A.

20. A method according to any one of claims 12 to 19 further comprising the steps of forming a first electrode layer in said first and/or second recess(es) or trench(es).

21. A method according to claim 20, in which said electrode layer is a polycrystalline layer having a thickness substantially in the range 1000 to 2000A.

21 -

22. A method according to claim 20 or 21 further comprising the steps of forming a dielectric layer on said electrode layer, and forming a second electrode layer on said dielectric layer.

23. A semiconductor device comprising: a field oxidelayer selectively formed on a first conductivity type semiconductor substrate to define an active region; a gate electrode electrically insulated on the active region; a source region and a drain region formed at respective sides of said gate electrode and on the surface of said semiconductor substrate; a first conductive layer formed to connect with a gate electrode of an adjacent memory cell on any predetermined portion of said field oxide layer; a trench formed in said semiconductor substrate and within said source region; a first insulating layer to insulate said gate electrode and said first conductive layer; and a second conductive layer formed inside said trench and on said first insulating layer; wherein a diffusion blocking layer is provided between said semiconductor substrate and said second conductive layer formed over the surface of said trench.

24. A semiconductor device as claimed in claim 23, wherein said diffusion blocking layer consists of an oxide layer.

25. A semiconductor device as claimed in claim 23, wherein said first and said second conductive layers consists of impurity- doped polycrystalline silicon layer.

26. A method for manufacturing a semiconductor device comprising in the cited order the steps of:

defining an active region by growing a field oxide layer on a first conductivity type semiconductor substrate; forming a gate electrode, a source region and a drain region of a transistor on said active region, forming a first conductive layer on any predetermined portion of said field oxide layer, and forming a first insulating layer on the resultant structure; forming a f irst trench by applying a mask on said first insulating layer disposed over said source region; forming a nitride layer on the resultant structure; leaving said nitride layer only on the walls of said first trench; forming a second trench to connect with said first trench; forming a diffusion blocking layer; removing said nitride layer formed on the walls of said first trench; and forming a second conductive layer on the resultant structure.

27. A method for manufacturing a semiconductor device as claimed in claim 26, wherein said step of forming a first trench by applying a mask on said first insulating layer disposed over said source region comprises the steps of: forming a photoresist pattern on said first insulating layer and forming an opening to expose -a portion of said source region by etching of the first insulating layer with the application of said photoresist pattern; and anisotropic etching of said semiconductor substrate as deeply as the depth of said source region by using said first insulating layer as a mask, after removing said photoresist pattern.

1 lk-

28. A method for manufacturing a semiconductor device.as claimed in claim 26, wherein said nitride layer is formed by low pressure chemical vapor deposition, thereby forming a thickness of about 50A - 200A.

29. A method for manufacturing a semiconductor device asclaimed in claim 26, wherein said step of leaving said nitride layer only on the walls of said first trench is performed by etching of the nitride layer on the resultant structure obtained by the preceding steps.

30. A method for manufacturing a semiconductor device as claimed in claim 26, wherein said step of forming the second trench to connect with said first trench is carried out by anisotropic etching of said semiconductor substrate having said first trench therein, with a predetermined depth.

31. A method for manufacturing a semiconductor device as claimed in claim 30, wherein said predetermined depth is about 1pm - 3pm.

32. A method for manufacturing semiconductor device as claimed in claim 26, wherein said step of forming diffusion blocking layer is carried out by thermal growing of the oxide layer having a thickness of about 50A 500A.

33. A method for manufacturing a semiconductor device as claimed in claim 26, wherein said step of removing said nitride layer is carried out by a wet etching process.

34. A semiconductor device and/or manufacturing method thereof substantially as hereinbefore described with reference to Figures 2 to 3 of the accompanying drawings.

Published 1991 at The Patent Office. Concept House. Cardiff Road, Newport, Gwent NP9 I RH- Further copies niay be obtained from Sales Branch, Unit 6. Nine Mile Point, Cwnifelinfach. Cross Keys, Newport, NP I 7HZ. Printed by Multiplex techniques lid, St Mary Cray. Kent.