GB2225919A

GB2225919A - Process and apparatus for bus assignment to data processing devices

Info

Publication number: GB2225919A
Application number: GB8926884A
Authority: GB
Inventors: Dietmar Beltz; Detlef Klose; Hans-Juergen Nehler; Werner Rozek
Original assignee: Carl Zeiss Jena GmbH
Current assignee: Jenoptik AG
Priority date: 1988-12-06
Filing date: 1989-11-28
Publication date: 1990-06-13
Also published as: GB8926884D0; DD277778A1; DD277778B5; DE3932863A1

Description

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DESCRIPTION

PROCESS AND APPARATUS FOR BUS ASSIGNMENT TO DATA PROCESSING DEVICES This invention relates to the control of bus transfer by data processing devices in multimaster capable buses.

If in an information processing system a number of data processing devices work together via a common bus with other devices using the same bus then on a time division basis a data processing device is switched on on the common bus and controlled by bus assignment circuits ( "arbi ters").

If a data processing device is to be switched to the bus in order to operate in conjunction with another facility then it sends a request via the bus and this causes a central or decentralised assignment circuit to assign the bus of the device in question in accordance with a stored algorithm so that it can then be assigned to it. After transfer of the bus by the data processing device assigned to the bus, it receives the bus for one or more bus cycles according to the hardware design of its bus control element ("Das 8086/8088 BuchProgrammieren in Assembler und Systemarchitektur, technik marketing, Munich Chapter 10, page (10-12)).

If several devices transmit a request, the assignment algorithm, which generally takes account of priority in processing requests, selects one of the devices requesting a bus ("Das 8086/8088 Buch-Programmieren in 1 Assembler und Systemarchitektur, technik marketing, Munich Chapter 9, pages (9-8) to (9-10), Chapter 10, pages (10-4) to (10-6)), Known technology includes for example central assignment circuits (Winter, W: 'Trogrammierbare Arbiter zur Ressourcenverwaltung" "rfe 34 (1985) H, 7, pages 457-561) and circuits operating on the daisychain principle.

In a priority-based bus assignment in a multi-computer system (DD-WP 144 691)_,a stationary bit pattern is used as an allocation signal which circulates in a closed-ring shift chain., Bus access is to a pre-set pattern dependent on priority.

In DD-WP 238 128 A1 there is an arrangement of a stored program arbiter for facility management which consists of a request register, a control register, a memory store, an output card and a control unit.

In particular applications it is desirable that there be a facility to influence bus allocation in some simple way, ie. by introducing a change in the allocation rules in order to gain access which may be necessary temporarily via one of the data processing devices, whose bus request would not otherwise be processed as a high priority.

In known technology this requirement is only realisable with extra hardware circuits, if at all.

It is one object of the present invention to realise rapid information exchange between the data processing devices in multimaster capable buses with relatively low circuit costs, 1 7be present invention seeks to provide a modifiable bus allocation via one of the data processing devices which is switched to the multimaster capable bus and which is independent of the priority dependency for processing bus requests via the allocation system.

According to a first aspect of the present invention, this task is achieved using a procedure for bus allocation to data processing devices which are connected to multimaster capable buses whereby, within a central bus signal pulse, an allocation signal is generated channel by channel from request signals transmitted by devices, taking into account pre-programmed allocation instructions, and is transmitted to the device with the highest priority. 7he allocation instructions are changed in the first bus cycle of the bus receiving device by resetting a predefined request blocking mask, and optional exclusion of data processing devices by blocking the request signals. Ihis fresh setting of the bus possessing device is cancelled in the last bus cycle.

The present invention also provides an arrangement for bus distribution to data processing devices whose request channels are transmitted via the request signals for receiving the multimaster capable bus and are connected with an allocation device whose outputs lead to allocation channels of the multimaster capable bus. A request blocking exists prior to the allocation instruction for each request channel and at this request blocking selection of the request signals received via an input there is a block request signal which is switched to an active or non- active state.

For mode setting each of the inputs for the block request signal is linked to an allocated output of a request block mask register, to the inputs of which are fed on the one hand the outputs of a multiplexer, both data buses and also a preset unit and the reset channel of the multimaster capable bus, and on the other hand there is a link via an enable input to the output of a logic gate. A link exists to the output of a mask-enable logic element. The logic gate is connected on the input side with the reset channel and with the output of a write request selection on one input of which there is a write channel, which is also fed to the reset input of an acknowledgement signal transmitter. The acknowledgement signal transmitter is connected on the input side via a time delay to the output of an address decoder whose other input is connected to the write request selection, By way of example onlya specific embodiment of the present invention will now be described, with reference to the accompanying drawings-in which:

Fig, 1 is an arrangement for mask programmed bus allocation in accordance with the present invention; and Fig, 2 is a pulse system for the arrangement in accordance with Fig, 1 for three data processing devices, The arrangement as in Fig. 1, which is connected to a multimaster capable bus, contains N request blocks 1, on one input of each of which an allocated request channel AFi, i = 1,.,,, N of a data processing 1 -5device (not depicted) and on the second Input in each case the allocated output of a request block mask register 3 are connected.

The outputs of the request blocks 1 lead to the inputs of an allocation device 2, whose outputs are connected to the allocation channels of the multimaster capable bus.

The m inputs of the request block mask register 3 are connected to the m outputs of a (2 x m to m) multiplexer 4. The enable input CS is connected to the output of a mask enable logic element 5. One input of the mask enable logic gate 5 is fed to the RESET channel of the multimaster capable bus, and the second input is connected to the output of a write request select 7. Logic gate 5 switches over the active condition of the RESET signal or the active condition of the output signal of the write request select 7 to the active condition of the enable input of the request block mask register 3.

One input of the write request select 7 is connected to a write channel WR of the multimaster capable bus which is also switched to the reset input of an acknowledgement signal transmitter 10. The second input of the write request select 7 is connected to the output of an address decoder 8.

The output of the write request select 7 is active when the write connand and the address decoder output are active, The output of the address decoder is also coupled to the input of a delay element 9 the output of which is fed to the input of the acknowledgement signal transmitter 10, The output of the acknowledgement signal transmitter is connected to the acknowledgement signal channel Q5 of the multimaster capable bus and it is active at the very moment when address decoder 8 has selected the address of the request block mask register 3, the write command is active and the setting of the request block mask register 3 is concluded. The acknowledgement signal transmitter 10 is kept in the inactive state when the write command WR is inactive. Address decoder 8 is connected firstly on the input side to the address channels AB of the multimaster capable bus and secondly with the outputs of an address preset unit (not shown).

The (2 times m to m) multiplexer 4 is connected firstly with data bus channels DB of the multimaster capable bus and secondly the outputs of a preset unit 6 for the initial state of request block mask register 3 are at other inputs of multiplexer 4, The choice as to whether the information on data bus channels DB or the outputs of preset unit 6 are multiplexed to the request block mask register 3 is made using the RESET signal. When the RESET channel is at the active level the preset value reaches request block mask register 3 otherwise information from data bus channels DB do so.

The invention will be explained using a computer system with a multimaster capable bus and three data processing devices, When the computer system is switched on, initialisation of the computer system is via a RESET unit by the RESET signal being set at active on the RESET channel of the multimaster-capable bus.

In this way p multiplexer 4 switches the m + 1 width preset value DATO to. DAT m of preset unit 6 for the reset state of the request block mask to the inputs of the request block mask register 3. The enable input CS of the request block mask register 3 becomes active via the mask enable logic gate 5 by activating the RESET signal, so that the preset value is written. The preset value has been selected in this example such that the block request signals SAFv share the inactive state with v = 1... N and N = 3, Depending on the programming details of the computer system it can occur that the data processing device with the third priority level has to finish a program section with information exchange more rapidly via the multimaster capable bus, whereby the data processing device with the second priority level can always request the bus when required and must get it. The third data processing device requests control of the bus via request channel AF3. After permission for bus allocation has been granted to the third data processing device and the device with the bus has given it up, the third data processing device takes control of the bus. In the first bus cycle to be executed it transmits the address of the request block mask register 3 in a write bus cycle and also the new request block mask allocation DBO = active state for SAFI DB1, DB2 = inactive state for SAF2, 3 etc.

This data bus allocation reaches the inputs of the request block mask register 3 via multiplexer 4 when the RESET signal is inactive. The address Is decoded in address decoder 8. The output of address decoder 8 becomes active.

When the write command is active, the enable input of request block mask register 3 also becomes active so that what is now the current input allocation is taken over into register 3.

When allocation to the request block 1,1 becomes active, output AF 1,1 remains in the inactive request state. The active state of the address decoder output is transmitted via the delay element 9 to the acknowledgement signal transmitter 10 which is ready to transmit using the active write command, The acknowledgement signal transmitter 10 transmits the acknowledgement signal only when the request block mask has become effective at the request blocks 1. When the program section which has to be processed more quickly has been concluded, there follows the processing of a write command (which corresponds to a write bus cycle on the bus) to the address of the request block mask register 3, where for example the original request block mask on the data bus of the multimaster capable bus is written. The effect of the arrangement in this invention in this last bus cycle is equivalent to that described in the first bus cycle.

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Claims

A process for bus assignment to data processing devices which are connected to a multimaster capable bus whereby within a bus pulse using signals transmitted by the devices and taking into accoupt pre-programmed assignment instructions, an assignment signal is generated and transmitted to the device with the highest priority, such that to change the assignment instructions in the first bus cycle of the bus receiving device by resetting a preset request block mask, a selective exclusion of data processing devices using blocking of the request signals results and the resetting of the device with the bus in the last bus cycle is abandoned.
2. An apparatus for bus assignment to data processing devices whose request channels are transmitted via the request signals to receive the multimaster capable bus, connected with an allocation instruction, whose outputs lead to allocation channels of the multimaster capable bus, such that a request block exists prior to the assignment instructions for each request channel at which there is a block request channel for toggling the incoming request to the active or non-active state via an input.
3. An apparatus as claimed in claim 2, in which, for setting the state of each of the inputs; the block -10request signal is linked with an assigned output from a request block mask register, the inputs of which are linked firstly to the outputs of a multiplexer, to which both data buses and also a preset unit and the reset channel of the multimaster capable bus are sent, apd secondly there exists a connection to the output of a mask enable logic unit via an enable input, which on the input side is linked with the reset channel and with the output of a write request select, on one input of which there is a write channel which is also fed to the reset input of an acknowledge signal transmitter whose input is connected via a delay unit with the output of an address coder which in turn is connected to the other input of the write request select.
4. A process for bus assignment, substantially as hereinbefore described wi th reference to the accompanying drawings.
5. An apparatus for bus assignment, substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

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