DE3932863A1 - METHOD AND ARRANGEMENT FOR BUS ASSIGNMENT TO DATA PROCESSING DEVICES - Google Patents

Abstract

A process and an apparatus for bus assignment to data processing devices wherein, to change the allocation instructions for the generation of an allocation signal which is transmitted to the device receiving the bus, there is in the first bus cycle of the device receiving the bus, by resetting a preset request block mask, an optional exclusion of data processing devices by blocking request signals which are transmitted by the data processing devices. In the last bus cycle of the device possessing the bus this new setting is cancelled. <IMAGE>

Description

The invention is used to control bus takeover by data processing equipment in multi-master capable buses.

Several work in one information processing system data processing facilities via a common bus with other resources on the bus the activation of a data processing device on the shared bus time-shared and by bus allocation circuits (Arbiter) controlled.

When to turn on a data processing device on the bus is to connect to another resource occur, it issues a request via the bus, whereby a central or decentralized assignment circuit causes the bus according to a stored algorithm assign to the requesting institution, so that this then the bus can be assigned.

After taking over the bus by the data processing device assigned to the bus depending on the hardware configuration of your bus control element the bus for one or more bus cycles ("Das 8086/8088 book programming in assembler and system architecture, technik marketing, Munich chapter 10, p. (10- 12)).

If several institutions submit a request, so causes the assignment algorithm, which mostly has priority dependencies considered processing of requirements, the selection of a bus requesting device ("Das 8086/8088 book programming in assembler and system architecture, technik marketing, Munich chapter 9, pp. (9-8) to (9-10), Chapter 10, pp. (10-4) to (10-6)).

Known technical solutions are central allocation circuits  (Winter, W .: "Programmable Arbiter for Resource Management" rfe 34 (1985, H. 7, pp. 457-561) and circuits according to the daisy chain principle.

In an arrangement for controlling a multi-computer system (DD-WP 1 44 691) becomes a stationary as an allocation signal Bit pattern used in a closed ring Sliding chain revolves. The bus access takes place after a predetermined pattern and is priority-dependent.

In DD-WP 2 38 128 A1 there is an arrangement of a memory-programmed Arbiters on resource management explained that out Claims register, control register, memory and one Output module and a control unit exists.

It is desirable for certain applications in to be able to influence bus allocation in a simple way, d. H., bring about a change in the assignment rule, at z. B. only necessary access for a short time to ensure one of the data processing facilities, whose bus request is not processed with priority.

With the known technical solutions, this requirement not or only with significantly increased circuitry Effort possible.

The aim of the invention is to use in multimaster-capable buses relatively little circuitry effort faster Exchange of information between data processors To ensure facilities.

The invention has for its object one by a multimaster capable bus connected data processing device changeable bus allocation, which is independent of the Priority dependencies for processing bus requests is to be guaranteed by the allocation device.

According to the invention, a method is used to achieve the object for the allocation of buses to data processing facilities that a multimaster-capable bus are connected, whereby within a bus cycle from channel to channel through the facilities sent request signals taking into account a pre-programmed assignment rule an assignment signal educated and sent to the highest priority institutions is transmitted. To change the assignment rule takes place in the first bus cycle of the bus-receiving device by resetting a preset request blocking mask an optional exclusion of data processors Facilities by disabling the request signals. This new setting becomes in the last bus cycle of the bus owner Establishment lifted.

The invention also relates to an arrangement for Bus allocation to data processing facilities, their  Request channels, via the request signals for receipt of the multimaster-capable bus are sent with a Assignment device are connected, the outputs of which Allocation channels of the multi-master capable bus. The allocation device is for each request channel a request lock upstream, on which to select the incoming request signal via an input an in an active or non-active state switchable lock request signal is present.

To set the status, each of the inputs is for the Lock request signal with an assigned output of a Request lock mask register connected to its inputs on the one hand the outputs of a multiplexer to which both data buses and a preset unit and the Reset channel of the multimaster-capable bus, on the other hand, a connection to the via an enable input Output of a mask enable logic element exists. The The logic element is on the input side with the reset channel and connected to the output of a write request selection, on one input there is a write channel which also to the reset input of an acknowledgment signal transmitter is led. The acknowledgment signal transmitter is on the input side via a delay element with the output of a simultaneously to the other input of the write request selection connected address decoder connected.

The invention is based on the schematic Drawing will be explained in more detail. It shows

Fig. 1 shows an arrangement for mask programmed bus arbitration according to the invention,

Fig. 2 is a timing diagram for the arrangement of FIG. 1 for three data processing devices.

The arrangement according to FIG. 1, which is connected to a multimaster-capable bus, contains N request blocks 1 , at each of which an assigned request channel AFi, i = 1,. . ., N of a data processing device (not shown) and the associated output of a request blocking mask register 3 are connected to the respective second input.

The outputs of the request blocks 1 lead to the inputs of an assignment device 2 , the outputs of which are connected to assignment channels of the multimaster-capable bus.

The m inputs of the request blocking mask register 3 are linked to the m outputs of a (2 × m to m ) multiplexer 4 . The enable input CS is connected to the output of a mask enable logic element 5 . One input of the mask enable logic element 5 is connected to the reset channel RESET of the multimaster-capable bus, the second input is connected to the output of a write request selection 7 . The logic element 5 converts the active state of the RESET signal or the active state of the output signal of the write request selection 7 into the active state of the enable input of the request blocking mask register 3 .

An input of the write request selection 7 is linked to a write channel WR of the multimaster-capable bus, which is also connected to the reset input of an acknowledgment signal transmitter 10 . The second input of the write request selection 7 is connected to the output of an address decoder 8 .

The output of the write request selection 7 is active when the write command and the address decoder output are active. The output of the address decoder is further coupled to the input of a delay element 9 , the output of which leads to the input of the acknowledgment signal transmitter 10 . The output of the acknowledgment signal transmitter 10 is connected to the acknowledgment signal channel QS of the multimaster-capable bus and is active precisely when the address decoder 8 has selected the address of the request blocking mask register 3 , at the same time the write command is active, and the setting of the request blocking mask register 3 has been completed. The acknowledgment signal transmitter 10 is kept in the inactive state when the write command WR is inactive. The address decoder 8 is connected on the input side to address channels AB of the multimaster-capable bus on the one hand, and on the other hand to the outputs of an address presetting unit (not shown).

The (2 × m to m ) multiplexer 4 is connected on the one hand to data bus channels DB of the multimaster-capable bus, on the other hand the outputs of a presetting unit 6 for the initial state of the request blocking mask register 3 are present at further inputs of the multiplexer 4 .

The selection whether the information of the data bus channels DB or the outputs of the presetting unit 6 is multiplexed to the request blocking mask register 3 is made with the RESET signal. When the level on the reset signal RESET is active, the preset value reaches the request blocking mask register 3 , otherwise the information of the data bus channels DB .

The invention is based on a computer system with multi-master capable Bus and three data processing facilities are explained.

When the computer system is switched on, a RESET unit initialization of the computer system by activating the RESET signal on the reset channel RESET of the multi-master capable bus.

The multiplexer 4 thus switches the m + 1 wide preset value DATO. . .DAT m of the presettability 6 for the initial state of the request blocking mask to the inputs of the request blocking mask register 3 . Over the mask enable gate 5 of the RESET signal is the enable input of the CS request blocking mask register 3 active so that the preset value is written by the active state. In this example, the preset value is chosen such that the lock request signals SAF v with v = 1. . . N u. N = 3 inactive.

Depending on the program status of the computer system, the situation arises that the data processing device with the third priority level has to complete a program part with information exchange via the multimaster-capable bus more quickly, the data processing device with the second priority level always being able to request and receive the bus as required got to. The third data processing device uses the request channel AF 3 to apply for bus control. After the permission for the bus assignment has been granted for the third data processing device and the bus owner device has released the bus, the third data processing device takes over bus control. In its first bus cycle to be executed, it sends the address of the request blocking mask register 3 and the new request blocking mask assignment in a write bus cycle

DB 0 = active state for SAF1
DB 1 , DB 2 = inactive state for SAF2, 3

out.

When the RESET signal is inactive, this data bus assignment reaches the inputs of the request blocking mask register 3 via the multiplexer 4 . The address is decoded in the address decoder 8 . The output of the address decoder 8 becomes active. With the active write command the enable input is the requirement blocking mask register 3 also active, so that the now current input assignment is transferred to the register. 3

When the assignment at request lock 1.1 becomes active, the output AF × 1.1 remains in the inactive request state. The active state of the address decoder output is transmitted via the delay element 9 to the acknowledgment signal transmitter 10 , which is ready to send by the active write command. The acknowledgment signal transmitter only sends the acknowledgment signal when the request blocking mask on the request blocks 1 has become effective. If the program part to be processed faster is completed, the processing of a write command (which corresponds to a write bus cycle on the bus) follows the address of the request blocking mask register 3 , where z. B. the original request blocking mask lying on the data bus of the multimaster-capable bus is written. The effect of the inventive arrangement in this last bus cycle is equivalent to that described in the 1st bus cycle.

Claims (3)

1. A method for bus assignment to data processing devices which are connected to a multimaster-capable bus, wherein within a bus cycle from request signals sent by the devices channel by channel, taking into account a preprogrammed assignment rule, an assignment signal is formed and transmitted to the device with the highest priority, characterized in that to change the assignment rule in the first bus cycle of the bus-receiving device by re-setting a preset request blocking mask, an optional exclusion of the data processing devices is carried out by blocking the request signals and the new setting is canceled in the last bus cycle of the bus-holding device. 2. arrangement for bus allocation to data processing facilities, their request channels, via the request signals sent to receive the multimaster-capable bus are connected to an allocation device, whose outputs to assignment channels of the multi-master capable Busses, characterized in that the Assignment device for each request channel Requirement lock is connected upstream to the selection the incoming request signal via an input a switchable into an active or inactive state Lock request signal is present. 3. Arrangement according to claim 2, characterized in that for setting the status of each of the inputs for the Lock request signal with an associated output a request lock mask register is connected to the inputs of which are the outputs of a multiplexer are linked to both data buses as well a pre-setting unit and the reset channel of the multi-master capable Busses are led, on the other hand an enable input connects to the output of an Mask enable logic element exists, the input side with the reset signal and with the output one Write request selection is connected, on one of them Input is a write channel, which is also connected to the Reset input of an acknowledgment signal transmitter performed is on the input side via a delay element the output of one to the other input of the Write request selection of connected address decoder connected is.