DD277778B5 - METHOD AND ARRANGEMENT FOR THE BUS AWARD OF DATA PROCESSING DEVICES - Google Patents

Description

For this 2 pages drawings

Field of application of the invention The invention is used to control the bus transfer by dMenverarbeitende facilities in multimastorfähigen buses. Characteristic of the known technical solutions Working in an information processing system more than one dataprocessing facility has a common one Bus together with other resources lying on the bus, so the intrusion of a data processing device takes place

timed on the common bus and controlled by bus arbitration (Arbiter).

If a dataproaching device is to be connected to the bus to communicate with another resource

If so, it issues a request over the bus, causing a central or decentralized allocation circuit to allocate the bus to the requesting device according to a stored algorithm so that it can then be assigned to the bus. After the bus has been taken over by the data processing device assigned to the bus, depending on the hardware configuration of its bus control unit, it holds the bus for one or mochroro bus cycles ("Das 8086/8088

Buch-Programmon in Assembler and System Architecture, technik marketing München, Chapter 10, pp. 10-12 |). If several devices transmit a request, the allocation algorithm usually works Considering the priority dependency of processing requests, selecting a bus requesting device

(The 8086/8088 Book Programming in Assembler and System Architecture.) München, Chapter 9, pp. 9-8 | to [9-101, chapter 10, pp. 10-4 | to [10-6] ).

Bokannte technical solutions are central Vergabeschaltungen (Winter, W .: "Programmiorbaro Arbiter zur Resource Management ", 34 (1985) H.7, p.457-461) and circuits according to the daisy-chain principle. In an arrangement for controlling a multi-computer system (DD-WP 144691) is a stationäies as an allocation signal Bit pattern used, which rotates in an annularly closed Schiebekotte. The bus access takes place after one

given pattern and is dependent on priority.

DD-WP 238128 A1 discloses an arrangement of a memory programmed arbiter for Rossourconvorwaltung, the Demand register, control register, a memory and an output module and a control unit order.

It is desirable for certain applications to be able to influence the bus allocation in a simple manner, that is, to bring about a change in the assignment rule in order, for example, to change the assignment of the bus. to ensure only for a short time necessary access by one of the data processing facilities whose bus request is not prioritized. With the known technical solutions, this requirement is not possible or only with significantly increased circuit complexity.

Object of the invention

The aim of the invention is to ensure a more rapid information exchange between dsn data-processing facilities in multimastorfähigen buses with relatively little circuit complexity.

Presentation of the essence of the invention

The invention has for its object to provide a switched by a multimaster on the bus data processing device variable bus allocation, which is independent of the priority dependencies of the processing of bus requests through the allocation device to ensure.

To achieve the object according to the invention is a method for bus allocation to data processing facilities that are connected to a multimaster bus, wherein within a bus clock from channel-wise by dio devices sent request signals, taking into account a preprogrammed assignment rule an assignment signal is formed and transmitted to the device with the highest priority , To change the assignment rule is done in the first bus cycle of the bus-receiving device by re-setting a preset request barrier masko an optional exclusion of data processing facilities by blocking the request signals. This Ncueinstcllung is repealed in the last bus cycle of businnchabcnden device. The invention also relates to an arrangement for bus allocation to data processing devices whose request channels, via which request signals for obtaining the multimaster-capable bus are sent, are connected to an allocation device whose outputs lead to assignment channels of the multimaster-enabled bus. The allocation device is preceded by a request block for each request channel, to which an access request signal which can be switched to an active or inactive state is applied via an input for selection of the corresponding request signal.

For the state adjustment, each of the inputs for the disable request signal is connected to an associated output of a request disable mask register whose input carries, on the one hand, the outputs of a multiplexor to which both data buses and a default unit and the reset channel of the multimnstorfäliigon bus are routed via an enable input to the output of a mask Enablo gate. The gate is eingangsssitig with dom reset channel and connected to the output oiner Schreibanfordorungsauswahl, on one input of which is a write channel, which is also fed to the Rücksotzeingang anos acknowledgment signal transmitter. The acknowledgment signal transmitter is input-connected via a delay element to the output of an address decoder connected simultaneously to the other input of the write request selection.

Ausführungsbelsplel

The invention is intended to be described in more detail on the basis of the schematic drawing. Show it

Fig. 1; FIG. 2 shows a timing diagram for the arrangement according to FIG. 1 for three data-polluting devices. FIG.

The arrangement of FIG. 1, which is connected to a multimastorfähigen bus, boinhaltot N request sporron 1, at whose one input an associated request channel AFi, i = 1, ..., N oinor datenverarboiiondon means (not shown) and the second respectively Input the associated output of a request Sporrmaskenrogistors 3 are connected.

Dio outputs of the request locks 1 lead to don inputs of an allocation device 2, the output of which are connected to assignment channels of the multimaster-enabled bus.

0 ·) m inputs dos Anfordorungsspnrrmaskenregistors 3 with the m outputs einos (2 χ m to multiplexor ml Λ vorknüpft The enable input CS is connected to the output verschaltot einos mask Er.able-Verknüpfungsgliodos 5 One input of the Mar.. .ken enable gate 5 is connected to the reset bus RESET of the multimaster bus, the second input is connected to the output of a write request selector 7. The gate 5 sets the active state of the RESET signal or the active state of the output signal of the screw request selection 7 in the active state of the enable input dos request blocking mask register 3 order.

An input of the write-forward selection 7 is connected to a write channel WR of the multimotor-capable bus, which also goes to the reset input of an acknowledgment signal transmitter 10 in FIG. The second input of the write request selection 7 is connected to the dom output of an address decoder 0.

The output of the write request selection 7 is active if the write command and the address decoder output are active. Dor output dos address decoder is woitorhin coupled to the input of a delay element 9, whose output leads to don input of the acknowledgment signal ε rs 10. The output of the acknowledgment signal transmitter 10 is connected to the acknowledgment signal channel QS of the multimaster bus and is active when and only if the address decoder 8 has selected the address of the request semaphore master 3, at the same time the write command is active, and the setting of the

Request lock mask register 3 is completed. The acknowledgment signal transmitter 10 w ^: rd when inactive Write command WR kept in inactive state. The address decoder 8 is the input side to one with address channels AB

the multimaster bus, on the other hand connected to the outputs of an address presetting unit, not shown.

The (2 χ m to ml multiplexer 4 is on the one hand connected to data bus channels DB of the multimaster bus, on the other hand

the outputs of a preset unit 6 for the initial state of the request blocking masks register 3 are at another

Inputs of the multiplexer 4 on. The selection whether the information of the data bus channels DB or the outputs of the presetting unit 6 for Request lock mask registers 3 are multiplexed with the RESET signal. With active level on the Reset channel RESET, the preset value. * Arrives at request block mask register 3, otherwise the information of the Data bus channels DB. The invention is based on a computer system with multimaster bus and three data processing facilities

be explained.

When the computer system is switched on, the initial initialization of the computer system takes place via a RESET unit

Activation of the RESET signal on the reset channel RESET of the multimaster bus.

Thus, the multiplexor 4 switches the m + 1-width preset value DATO ... DAT m of the preset unit 6 for the Initial state of the request spool mask to the input of the request inhibit mask register 3. About the Mask enable gate 5 is activated by the active state of the RESET signal of the enable input CS Request inhibit mask register 3 active, so that the default value is written. The default value is in this Example chosen such that the lock request signals SAVvv = 1 ... N and N-3 have the inactive state. Depending on the program-typical state of the computer systems, the situation arises that the data-processing Device with the third priority level, a program part with information exchange via the multimaster-enabled bus

faster to do nat, the data processing device with the second Prioritäisniveau always when needed can request and get the bus. The third dataprocessing organization applies via the AF3o dio Bush membership requirement channel. After the permission for the bus occupancy has been granted to the third data processing device and the bus device has disconnected the bus, the third sound processing device takes over the radio

Bus mastership. In its bus cycle to be executed, it sends the address of the bus in a write bus cycle Request screen mask registers 3 and the new request lock mask occupancy DBO = active state for SAF1; DB1, DB2 = inactive state for SAF2, 3 off. This data bus occupancy arrives at inactive RESET signal via the multiplexer 4 to the inputs of Request inhibit mask register 3. The address is decoded in the address decoder 8. The output dos address decoder 8 is

active.

With the active write command, the enable input of the request scramble register 3 also becomes active, so that

The current assignment is now transferred to register 3.

With Aktivwerdon the assignment other request lock 1,1 the output AF 1,1 remains in the inactive request state. The active state of the address decoder output is sent via the delay element 9 to the acknowledge signal diver 10

carry over, which is sondobereit by the active write command. Dor acknowledgment signal transmitter 10 sends the acknowledgment signal, in which the request blocking mask at the request interlock 1 has become effective. Is the faster to work on

Completed program part, there follows the execution of a write command (the one Schreibbuszyklus on the bus

corresponds) to dio address of the request lock mask canister 3, where z. B. the original on the data bus dos

mullimaster-capable bus lying request blocking mask is written. The effect of the inventive arrangement in this last bus cycle is equivalent to that described in the 1st bus cycle.

Claims (3)

1. A method for bus allocation to data processing equipment, which are connected to a multimaster bus, wherein within a bus clock from channel-wise transmitted by the devices request signals in consideration of a preprogrammed assignment rule an assignment signal is formed and transmitted to the device with the highest priority, characterized in that to change the assignment rule in the first bus cycle of the bus-receiving device by re-setting a preset request blocking mask an optional exclusion of the data processing facilities by blocking the request signals is carried out and the readjustment is canceled in the last bus cycle of the bus-transmitting device. 2. Arrangement for bus allocation to data processing facilities whose request channels are sent via the request signals to obtain the multimaster bus, are connected to an assignment device whose outputs lead to assignment channels of the multimaster bus, characterized in that the allocation device for each request channel upstream of a request Perro is applied to the selection of the incoming request signal via an input in an active or non-active state switchable lock request signal. 3. Arrangement according to claim 2, characterized in that is connected to the state setting of each of the inputs for the lock request signal to an associated output of a request lock mask register, with its inputs on the one hand, the outputs of a multiplexer are linked to the both data buses and a preset unit and the reset channel led the multimaster bus, on the other hand via an enable input, a connection to the output of a mask enable gate is connected on the input side to the reset channel and to the output of a write request selection, on whose one input is a write channel, which also to the Reset input of an acknowledgment signal transmitter is guided, which is connected on the input side via a delay element to the output of an address decoder connected simultaneously to the other input of the write request selection.