SU1709330A1 - Maltioperational system - Google Patents

Abstract

The invention relates to computing and can be used to build high-speed multiprocessor systems. The aim of the invention is to increase productivity by reducing the time required to establish communication with external devices. This goal is achieved in that the system containing k processor blocks, system memory, external device, bus arbiter, includes k elements AND, k triggers, k elements OR, k input drivers, k output drivers, k input drivers. 2 Il.

Description

The invention relates to computing and can be used to build high-speed multiprocessor systems.

A well-known multiprocessor system that contains system memory, processor units of the same type connected to a common bus, a block providing access to the common bus, an external device.

The disadvantage of such a system is low productivity.

A common bus system multiprocessor system comprising processor blocks, a bus arbiter, a system memory, and an external device. The bus arbiter is connected to the outputs. Request of the bus of each processor unit and outputs of the bus occupation signal. Signal Inputs The bus access representation is connected from the bus arbiter to the inputs of each processor unit.

The disadvantage of the system is low productivity due to the time consuming installation of communication with an external device that is common to processors (a common hardware resource). This is due to the need, when accessing an external device, to pre-capture the common bus for reading and setting the semaphore (a sign of an external device being busy) in the system memory. The processor using the external device presets the semaphore, grabbing the common bus for this, and after finishing work with the external device resets the semaphore, grabbing again the common bus. Such organization of access to an external device is necessary to prevent its simultaneous use by several processors. Thus, each processor to use

The external device must first check the semaphore in the bus grab mode. If an external device is occupied, then processors waiting to access it must repeatedly repeat attempts to occupy the external device, each time capturing the common bus for this. This reduces the throughput of the shared bus, and consequently, the system performance.

Due to the unproductive time spent on analyzing and installing the semaphore in the memory, this system also has this drawback, in which the bus arbiter is made in the form of separate circuits that are part of the processor units interconnected by a priority (daisy, chain) circuit. Such an organization of the system simplifies the process of increasing the number of processor units. The functions performed by both concentrated and distributed bus arbitrators are similar.

The aim of the invention is to improve the performance of a multiprocessor computing system.

This goal is achieved by the fact that triggers, signal conditioners, AND elements, and OR elements are entered into a multiprocessor system with a common bus, which contains K processor blocks, bus arbiter, system memory and external device, and the control input addresses (data) of each the processor unit is connected via a common bus to the same inputs / outputs of the system memory and an external device. Bus outputs occupied by processor blocks from the first to the Kth are connected to the bus arbitrator inputs of the same name from the first to the Kth, respectively. Outputs for granting access to the bus from the first to the Kth bus arbiter are connected to the same inputs of the processor blocks from the first to the Kth, respectively. Output A request for an external device of the 1st (, ..., K) processor unit is connected to the first input of the i-ro element I and the reset input of the i-ro trigger, the inverse output of which is connected to the input Providing an external device i-ro of the processor unit. The direct output of the i-ro trigger is connected to the input of the i-ro input signal conditioner and via bus An external device is connected to the inputs of all other input signal conditioners and the outputs of the other output signal conditioners. The output of the i-ro input signal conditioner is connected to the second input of the i-ro element AND, the output of which is connected to the first input of the i-ro element OR, the output of which is connected to the 1st

the bus request bus arbiter input. Output The request for the i-ro bus of the processor unit is connected to the second input of the i-ro element OR, the i-th output Authorization to grant access to the arbiter bus is connected to the input of the i-ro trigger.

Distinctive features in this relationship have never been met before, they are significant, and in their entirety they improve the system performance by reducing the time spent on establishing communication with an external device that is common to the processors.

5 In FIG. 1 and 2 the structural scheme of the proposed multiprocessor system is presented.

A multiprocessor system contains processor blocks 1.1, ... 1, K, associated

0 through a common bus 2 with system memory 3 and an external device 4, bus arbiter 5. Outputs of 1in are occupied by processor units from the first to the Kth are connected to the inputs of the arbitrator of the same name from the first to the Kth

5 tires respectively. Outputs The request for the external device of the processor units from the first to the Kth is connected to the first inputs of the corresponding elements 6.16. K and the reset inputs of the corresponding triggering trigger 7.17.K. Inverse outputs

Triggers 7.1 ..., 7.K are connected to the inputs of the provision of an external device of the corresponding processor units 1.1, ..., 1.K. Outputs Request bus processor blocks 1.11. Connected to the second inputs of the corresponding elements

OR 8.18.К. Element Outputs OR

8.18. To are connected with the corresponding

inputs Request bus arbiter 5 tires.

0 Outputs Permission to grant access to the bus of the arbitrator 5 buses are connected to the corresponding inputs of the processor blocks 1.11.K with the same name and with the corresponding inputs of the trigger setup

5 7.1, ..., 7.К. The direct outputs of the trigger 7.17.K are connected to the inputs of the corresponding output drivers 9.1, ... 9.K signals whose outputs are connected via a bus. The external device is occupied with the inputs0 of the input drivers 10.110.К

signals. Input driver outputs

10.110, K signals are connected to the second

the inputs of the corresponding elements And 6.16K, the outputs of which are connected to the first inputs of the corresponding elements

OR 8.18.К.

Processor units 1.1, ..., 1.K can be built on the basis of commercially available microprocessor sets. When using K589, K1802, K1804, and other partitioned microprocessors, the output control signals are generated in the microprogram memory, and the input signals are logical conditions.

If the processor unit is based on a single-chip processor CK 1801ВМ1, К1801ВМ2, К580ВМ80, К1810ВМ86, etc.), then the corresponding signals of this microprocessor are used as control input and output signals (Bus request, Bus provision, etc.). If the number of signals needs to be increased, this is achieved using input / output ports, for example, standard microcircuits K580BB55, B1802BB1, etc.

The common bus 2 includes conductors that provide for the transmission of address, data and control signals between devices. The number and purpose of the specified conductors is determined by the selected processor. For example, for the processor of the microcomputer Electronics 60, the number and purpose of these conductors is determined in accordance with the EAST. Chip types K565RUZ, K565RU6, as well as K573RFZ, K537RU10, K537RF5, etc. can be used to build system memory 3. Chip 5 can be used as an arbiter of the 1802BB2, K1810VB89idr type.

As elements 6.1, ..., 6.K and 8.1, ..., 8.K standard chips of the K155, K531 series, etc. can be used. In

as shapers 9.19.K and

10.1, ... 10. The signals can be used with 531 APZ, 531 AP4, 559IP1, 559IP2, 559IPZ, 589AP16,

589АП26, etc. Triggers 7.17.K can be

implemented on any triggers, which provide for their installation on the differential signal.

The system in the process of installing the communication of the processor units with an external device operates as follows.

Triggers 7.1, ..., 7.K are set to one state, if the corresponding processor blocks 1.11.К do not

set alarms Request external device. If the processor unit, for example 1.M, sets the signal Request of an external device, then this signal, firstly, goes to the reset input of trigger 7.M and removes the ban on switching it, and, secondly, it goes to the first input of the And 6 element .M. In this case, if external device 4 is occupied, on the bus, external device is occupied in this case, a low level, which through the shaper 10.M signals is fed to the second input

element 6.M., element 6.M does not generate the bus 2 request signal, and the bus request signal does not arrive at; bus 5 arbiter. When external device 4 is released

on the bus The external device is set to a high level, the element AND b.M produces a bus 2 request signal, and the OR 8.M element a bus request signal and the latter is fed to the corresponding

0 is the bus arbiter 5 input. The bus arbitrator 5 selects the next requesting processor block for service and sends it the Bus Access Grant 2 signal. With the arrival

The last 5 to the trigger setup input. 7. The trigger trigger is switched. In this case, firstly, through the driver of the 9.M signals, a signal is set for the Occupancy of the external device 4, a low level on the bus.

0 An external device is occupied, and secondly, a signal appears. Providing an external device at the input of processor unit 1.M. After the end of the exchange with the external device 4, the processor unit 1.M

5 removes the signal. External device request and trigger 7.M again switches to one state. In this case, the signal is canceled. Occupancy of the external device 4, on the bus. The external device is occupied through the driver 9.M signals is again set to a high level.

Thus, due to the presence of a signal line, the External Device is occupied by processor blocks that need

5 communicating with an external device 4, hjeT need to access system memory 3 for analyzing the semaphore in the shared bus 2 capture mode. As a result, the common bus busy time is reduced

0 and unproductive time spent by processors, i.e., the performance of the proposed multiprocessor system increases in comparison with the known ones. In a known multiprocessor system, each processor unit for using an external device must, in accordance with the algorithm, preset the semaphore, and after use, reset the semaphore to the original

0 state. For example, in processor units based on the K1810BM86 microprocessor, this can be done using the commands of the CCS HSNS and MOA. The total average time to complete them when

5 clock frequency of 2 MHz will be equal to 20 μs. Each processor unit only for a single check of the semaphore, if the external device is busy, will spend over 10 ISS. With repeated access to the system memory, in case of an external device being busy, this time is significantly increased for each processor. It should be added that when an external device is occupied, processor blocks that need to work with it will have to practically block the common bus using the LOCK XCHG command.

All the indicated time costs are almost completely absent in the proposed multiprocessor system, which makes it possible to reduce the total program execution time. Indeed, to check the external device is not necessary to capture the common bus. In addition, by setting the External Device Request signal, each processor can, without spending time on waiting, continue calculating if necessary. When receiving a response signal Representation of an external device, the processor interrupt moves to a subroutine to work with an external device. This increases system performance, which is a source of economic efficiency.

For example, in a numerical control system, the calculator calculates the coordinates for different types of interpolation and is a common external device for processors. When controlling by 10 coordinates, the special calculator is occupied by calculations of 3.5 ms per control cycle. Theoretically, during a specified time in a known device, the bus may be blocked by processors requiring access to a special calculator.

The application of the proposed system leads to a decrease in the time of the common bus by approximately 600 µs in each control cycle. This allows control over a larger number of coordinates with a constant control cycle or a reduction in the duration of a cycle, thus improving the quality of control.

Claims (1)

Claims A multiprocessing system comprising K processor blocks, system memory, external device, bus arbiter, the inputs / outputs of the control address (data) of each processor unit are connected via a common bus to the same inputs and outputs of the system memory and an external device; the output bus is occupied by the processor blocks from the first to the Kth inputs to the same from the first to the Kth inputs bus arbitrator accordingly connected to the same inputs of the processor blocks from the first to the Kth, respectively, characterized in that, in order to improve performance by reducing the time to establish communication with external devices, K elements I, K triggers, K elements OR, To input signal conditioners, To output signal conditioners, with output Request for external device 1st processor unit connected with the first input of the i-ro element I and the reset input of the i-ro trigger, the inverse output of which is connected to the input of the external device representation of the i-ro processor block, the direct output of the i-ro trigger is connected to the input of the ith output signal shaper, the output of which is connected to the input of the i-ro input shaper and through the bus. The external device is occupied with the inputs and outputs of the other output shaper, output i-ro input the signal conditioner is connected to the second input of the элемента element of AND, the output of which is connected to the first input of the i-ro element OR, the output of which is connected to the i-th input; Bus arbitrator bus request; output; The request of the i-ro bus of the processor unit is connected to the second input of the i-ro element; OR, 1st access authorization output to the arbiter bus is connected to the input of the i-ro trigger setup.