GB2216304A - Dynamic DMA transfer sizing - Google Patents
Dynamic DMA transfer sizing Download PDFInfo
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- GB2216304A GB2216304A GB8903790A GB8903790A GB2216304A GB 2216304 A GB2216304 A GB 2216304A GB 8903790 A GB8903790 A GB 8903790A GB 8903790 A GB8903790 A GB 8903790A GB 2216304 A GB2216304 A GB 2216304A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4009—Coupling between buses with data restructuring
- G06F13/4018—Coupling between buses with data restructuring with data-width conversion
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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Abstract
A device for dynamic DMA transfer sizing, which finds application in 16-bit computers and microprocessor systems including 8-bit devices enables the performance of DMA byte and word transfer operations. The type of the DMA operation is automatically determined during the transfer in dependance upon an 8-bit-DMA-controller 7 word transfer determining output 15 and signals 25, 27 indicating the bit-widths of memory modules 5, 10 and 3 and of input-output devices 6, 11 and 4 for an arbitrary number of transferred bytes and arbitrary start memory address. The 16-bit data bus 2, 9 of the 16-bit microprocessor system 1 is converted into an 8-bit data bus for byte transfer operation, whereupon the 8-bit DMA controller 7 adjusts its counter by one. For word transfer operation the 16-bit data bus of the microprocessor system 1 is not converted into an 8-bit bus and the 8-bit DMA controller adjusts its counters by two. Advantages of the invention are that the transfer number of digits is automatically determined at the beginning of the transfer operation and is not restricted by the parity of the byte count and start address. …<IMAGE>…
Description
A DEVICE FOR DYNAMIC DMA TRANSFER SIZING
The invention relates to a device for dynamic
DMA transfer sizing and is applicable to 16-bit microprocessor systems and microcomputers.
There has been proposed in Bulgarian
Authorship Certificate Reg. No. 70026"A device for byte sequential DMA transfer", a device for byte sequential
DMA transfer to the memory of a 16-bit microprocessor system. There has been proposedta 16-bit microprocessor system, an 8-bit DMA controller, a bidirectional intermediate data buffer and a system configuration determining block. The system configuration determining block contains a direction determining scheme, a system converting scheme, a memory position determining scheme and a blocking scheme, by means of which is controlled the bidirectional intermediate data buffer. The 8-bit input-output devices and memory modules are connected to the lower or upper half of the bidirectional data bus, and the 16-bit input-output devices and memory modules are connected to the both halves of the data bus. The 8-bit memory position determining input of the system configuration determining block is connected to the corresponding inputs of the 8-bit modules. The memory type input of the system configuration determining block is connected to the corresponding inputs of the 8-bit and 16-bit memory modules. The input-output device position determining input of the system configuration determining block is connected to the corresponding inputs of the 8-bit and 16-bit inputoutput devices. The data transfer in DMA mode is controlled by the 8-bit DMA controller. During the DMA transfer the 16-bit input-output devices and memory modules are considered as two separate 8-bit inputoutput devices and memory modules.
During the DMA transfer the 8-bit and 16-bit input-output devices control their input-output device position determining output, the 8-bit memory modules control the 8-bit memory position determining output, and the 8-bit and the 16-bit memory modules control the memory type output. In dependence on the state of these three outputs, the system configuration determining block transfers the 16-bit system data bus into an 8-bit one. This allows the execution of data transfer between a 16-bit memory module and an 8-bit input-output device, a 16-bit input-output device and an 8-bit memory module, and between a 16-bit inputoutput device and a 16-bit memory module. Therefore the positions of the 8-bit input-output devices and memory modules on the 16-bit data bus are not significant.
A disadvantage of this device is that the data transfer is only byte transfer. This reduces the data transfer rate in DMA mode and leads to minimal usage of the 16-bit system data bus bandwidth.
There have been propose devices for byte and word sequential DMA transfer, which use 16-bit DMA controllers. In the initialization phase it is necessary to assign the number of digits of the devices between which the DMA data transfer will be realised.
When the devices are 16-bit, in DMA word transfer mode only an even number of bytes will be transferred on an even address boundary.
A disadvantage of these devices is that the data transfer is with a static number of digits. The data transfer number of digits is programmed, and cannot be changed during the data block transfer between the memory and the input-output devices.
Another disadvantage of these devices is that the number of the transferred bytes and the address boundary in DMA word transfer mode are always even.
The aim of the present invention is to provide a device which allows during the DMA mode, with regard to the conditions, the data transfer to be dynamically changeable, byte or word sequential, with an arbitrary number of the transferred bytes and start memory address.
According to the present invention there is provided a device for dynamic DMA transfer sizing, which contains a 16-bit microprocessor system, the lower bidirectional data bus of which is connected to the lower bidirectional data bus of a 16-bit memory and of 16-bit input-output devices, to the bidirectional data buses of an 8-bit memory, of 8-bit input-output devices and of an 8-bit DMA controller, and to the data inputs-outputs"A"of an intermediate data buffer, the upper bidirectional data bus of the 16-bit microprocessor system being connected to the upper data bus of the 16-bit memory and 16-bit input-output devices, to the bidirectional data buses of an 8-bit memory and 8-bit input-output devices and to the data inputs-outputs"B"of the bidirectional intermediate data buffer, the address outputs of the 16-bit microprocessor system being connected to the address outputs of the 8-bit DMA controller and to the address inputs of the 16-bit memory, the first and second 8-bit memories, 8-bit input-output devices and 16-bit inputoutput devices, the microprocessor bus request output and the microprocessor bus acknowledge input of the 8bit DMA controller being connected to the corresponding input and output of the 16-bit microprocessor system, wherein the least significant address bit, the DMA address enable output and the word transfer determining input-output of the 8-bit DMA controller are connected to corresponding inputs and input-output of the word transfer control block, the DMA request inputs and the request acknowledge outputs of the 8-bit DMA controller are connected to the corresponding inputs and outputs of the 8-bit input-output devices, and the 16-bit input-output device, the direction determining output and the system converting output of the configuration determining block are connected to the corresponding inputs of the intermediate bidirectional data buffer, the 8-bit memory position determining output is connected to the corresponding output of the 8-bit memories, the memory type output of the 8-bit memories and the 16-bit memory is connected to the corresponding inputs of the configuration determining block and word transfer control block, the DMA mode input-output device position determining output of the 8-bit inputoutput devices and of the 16-bit input-output device are connected to the corresponding input of the configuration determining block, the DMA mode inputoutput device type output of the 8-bit input-output devices and of the 16-bit input-output device are connected to the corresponding input of the word transfer control block, the transfer type determining outputs of the 8-bit DMA controller are connected to the corresponding inputs of the configuration determining block and the word transfer control block, the byte transfer enable output and the 16-bit memory byte position determining output of the word transfer control block are connected to the corresponding inputs of the configuration determining block, and the upper bus enable output is connected to the corresponding input of the 16-bit memory and the 16-bit input-output device.
In a development of the invention the configuration determining block contains a blocking scheme, memory position determining scheme, system converting scheme and a direction determining scheme, the memory type input, 8-bit memory position determining input and the DMA mode input-output device position determining output of the configuration determining block being inputs of the blocking scheme, the memory cell position determining output of the memory position determining scheme being connected to the corresponding input of the system converting scheme and the direction determining scheme, the byte transfer enable input of the configuration determining block being an input of the blocking scheme, memory position determining scheme, system converting scheme and direction determining scheme, the transfer type determining outputs of the configuration determining block being direction inputs of the direction determining scheme, the 16-bit memory byte position determining output of the configuration determining block being an input of the memory position determining scheme, the input-output device determining output of the blocking scheme being connected to the corresponding inputs of the system converting scheme and direction determining scheme, the converting condition determining output of the system converting scheme being connected to the corresponding input of the direction determining scheme, whose output for selected direction is an input of the system converting scheme, the 8-bit memory determining output and the 16bit memory determining output of the blocking scheme being inputs of the memory position determining scheme, and the direction determining output and the system converting output of the configuration determining block being outputs of the system converting scheme and the direction determining scheme.
According to another development the word transfer control block contains a transfer number of digits determining block and a data bus control scheme, the memory type input, the DMA mode input-output device type output, the transfer type determining outputs, the
DMA address enable output and the byte transfer enable output of the word transfer control block being inputs and an output of the transfer number of digits determining block, the least significant address bit, the 16-bit memory byte position determining output and the upper bus enable output of the word transfer control block being an input and outputs of the data bus control scheme, the word transfer determining input-output of the word transfer control block being an input-output of the data bus control scheme, and the byte transfer enable input of the transfer number of digits determining block being an input of the data bus control scheme.
Advantages of an embodiment of the invention are that the transfer number of digits is automatically determined in the beginning of the transfer operation and is not restricted by the parity of the byte count and start address.
For a better understanding of the invention and to show how it may be put into effect reference will now be made, by way of example, to the accompanying drawings in which :
Fig. 1 is a block diagram of a device for dynamic DMA transfer sizing ;
Fig. 2 is a block diagram of the configuration determining block of Fig. 1 ; and
Fig. 3 is a block diagram of the word transfer control block of Fig. 1.
A device for dynamic DMA transfer sizing according to the invention, as shown in Fig. 1, contains a 16-bit microprocessor system 1, the lower bidirectional data bus 2 of which is connected to : the lower bidirectional data bus of a 16-bit memory 3 and of 16-bit input-output devices 4 ; to the bidirectional data buses of an 8-bit memory 5, of 8-bit input-output devices 6 and of an 8-bit DMA controller 7, and to the data inputs-outputs"A"of an intermediate data buffer 8.
The upper bidirectional data bus 9 of the 16bit microprocessor system 1 is connected to : the upper data bus of the 16-bit memory 3 and of the 16-bit input-output devices 4 ; to the bidirectional data buses of the 8-bit memory 10 and of the 8-bit input-output devices 11 ; and to the data inputs-outputs"B"of the bidirectional intermediate data buffer 8.
The address outputs 12 of the 16-bit microprocessor system 1 are connected to address outputs of the 8-bit DMA controller 7 and to the address inputs of the 16-bit memory 3, of the first and the second 8-bit memories 5 and 10, of 8-bit inputoutput devices 6 and 11, and of the 16-bit input-output devices 4. The least significant address bit 13, the
DMA address enable output 14 and the word transfer determining input-output 15 of the 8-bit DMA controller 7 are connected to the corresponding inputs and inputoutput of the word transfer control block 16.
The microprocessor bus request output 17 and bus acknowledge input 18 of the 8-bit DMA controller 7 are connected to the corresponding input and output of the 16-bit microprocessor system 1. The DMA request inputs 19 and the request acknowledge outputs 20 of the 8-bit DMA controller 7 are connected to the corresponding inputs and outputs of the 8-bit inputoutput devices 6 and 11 and the 16-bit input-output device 4. The direction determining output 21 and the system converting output 22 of the configuration determining block 23 are connected to the corresponding inputs of the intermediate bidirectional data buffer 8.
The 8-bit memory position determining output 24 is connected to the corresponding output of the 8-bit memories 5 and 10.
The memory type output 25 of the 8-bit memories 5 and 10 and the 16-bit memory is connected to the corresponding inputs of the configuration determining block 23 and word transfer control block 16. The DMA mode input-output device position determining output 26 of the 8-bit input-output devices 6 and 11 and of the 16-bit input-output device 4 are connected to the corresponding input of the configuration determining block 23. The DMA mode input-output device type output 27 of the 8-bit inputoutput devices 6 and 11, and of the 16-bit input-output device 4, are connected to the corresponding input of the word transfer control block 16. The transfer type determining outputs 28 of the 8-bit DMA controller 7 are connected to the corresponding inputs of the configuration determining block 23 and the word transfer control block 16. The byte transfer enable output 29 and the 16-bit memory byte position determining output 30 of the word transfer control block 16 are connected to the corresponding inputs of the configuration determining block 23, and the upper bus enable output 31 is connected to the corresponding input of the 16-but memory 3 and the 16-bit inputoutput device 4.
The configuration determining block 23 (Fig. 2) contains a blocking scheme 32, memory position determining scheme 33, system converting scheme 34 and a direction determining scheme 35. The memory type input 25, 8-bit memory position determining input 24 and the DMA mode input-output device position determining output 26 of the configuration determining block 23 are inputs of the blocking scheme 32. The memory cell position determining output 36 of the memory position determining scheme 33 is connected to the corresponding input of the system converting scheme 34 and the direction determining scheme 35. The byte transfer enable input 29 of the configuration determining block 23 is an input of the blocking scheme 32, memory position determining scheme 33, system converting scheme 34 and direction determining scheme 35.
The transfer type determining outputs 28 of the configuration determining block 23 are direction inputs of the direction determining scheme 35. The 16bit memory byte position determining output 30 of the configuration determining block 23 is an input of the memory position determining scheme 33. The inputoutput device determining output 37 of the blocking scheme 32 is connected to the corresponding inputs of the system converting scheme 34 and direction determining scheme 35. The converting condition determining output 38 of the system converting scheme 34 is connected to the corresponding input of the direction determining scheme 35, whose output for selected direction 39 is an input of the system converting scheme 34. The 8-bit memory determining output 40 and the 16-bit memory determining output 41 of the blocking scheme are inputs of the memory position determining scheme 33. The direction determining output 21 and the system converting output 22 of the configuration determining block 23 are outputs of the schemes 34 and 35.
The word transfer control block 16 (tig. 3) contains a transfer number of digits determining block 42 and a data bus control scheme 43. The memory type input 25, the DMA mode input-output device type output 27, the transfer type determining outputs 28, the DMA address enable output 14 and the byte transfer enable output 29 of the word transfer control block 16 are inputs of the transfer number of digits determining block 42. The least significant address bit 13, the 16-bit memory byte position determining output 30 and the upper bus enable output 31 of the word transfer control block 16 are input and outputs of the data bus control scheme 43. The word transfer determining input-output 15 of the word transfer control block 16 is an input-output of the data bus control scheme 43.
The byte transfer enable input 29 of the transfer number of digits determining block 42 is an input of the data bus control scheme 43.
The illustrated and described device for dynamic DMA transfer sizing operates in the following manner :
When one of the 8-bit input-output devices 6 or 11 or the 16-bit input-output device 4 activates its
DMA request output 19, the 8-bit DMA controller 7 accepts it and activates its microprocessor bus request output 17. The 16-bit microprocessor system 1, completing the current bus operation, relinquishes the control of the microprocessor bus and activates its microprocessor bus acknowledge input 18. The 8-bit DMA controller 7 becomes a bus master and activates the request acknowledge input 20 of the corresponding input-output device. In dependence upon its number of digits, the input-output device controls its DMA mode input-output device position determining output 26 and
DMA mode input-output device type output 27. The 8-bit
DMA controller 7 selects the memory cell with which the input-output device will exchange data. The memory module in which the cell resides activates its 8-bit memory position determining output 24 or memory type output 25, in dependence upon its number of digits. At even address, the 8-bit DMA controller 7 activates its word transfer determining output 15. In dependence upon the activated outputs from the input-output device and memory module, the configuration determining block 23 controls its direction determining output 21 and system converting output 22, and the word transfer control block 16-its word transfer determining output 15.
The configuration determining block 23 operates when the data transfer is byte-sequential and converts its 16-bit system data into 8-bit by connecting, in according manner, the lower 2 and the upper 9 bidirectional data buses. The word transfer control block 16 operates when the 8-bit DMA controller 7 activates its address enable output 28.
When the source of the DMA request 19 is an 8bit input-output device 6 or 11 and the memory cell selected by the 8-bit DMA controller 7 belongs to an 8bit memory 5 or 10, the memory type input 25 and DMA mode input-output device-type input 27 of the word transfer control block 16 are not active, and it activates its byte transfer enable output 29. The DMA mode input-output device position determining output 26 is active when a source of the request is the 8-bit input-output device 11, and the 8-bit memory module position determining output 24 is active when the selected cell belongs to the 8-bit memory 10. The configuration determining block 23 converts the 16-bit data bus at a difference between the states of the input-output device determining block output 37 of the block scheme 32 and the memory cell position determining output of the memory position determining scheme i. e. when the data transfer is executed between an input-output device and a memory module connected to different halves of the 16-bit microprocessor system data bus 1. The blocking scheme 32 activates its input-output device determining output 37, when it is activated by the DMA mode input-output device position determining input 26 of the configuration determining block 23.
At DMA transfer between the 8-bit input-output device 11 and the 8-bit memory 5 the DMA mode inputoutput device position determining output 26 is active and the 8-bit memory module position determining output 24 is inactive. The word transfer control block 16 activates its byte transfer enable output 29 and turns on the configuration determining block 23. The blocking scheme 32 checks the state of the DMA mode input-output device position determining input 26, the memory type input 25 and 8-bit memory module position determining input 24 and activates only its inputoutput device determining output 37. The memory position determining scheme 33 does not activate its memory cell position determining output 36. The system converting scheme 34 activates its conversion condition determining output 38 and turns on the direction determining scheme 35. It begins to monitor the state of its transfer type determining inputs 28 and when the 8-bit DMA controller 7 activates them, defines the direction of the intermediate bidirectional data buffer 8 and activates its direction determining output 39.
The system converting scheme 34 of the configuration determining block 23 converts the 16-bit data bus of the 16-bit microprocessor system 1 when it activates its system converting output 22. The data can be transferred through the intermediate bidirectional data buffer 8 from the upper bidirectional data bus 9 to the lower bidirectional data bus 2 and vice versa, in dependence upon the state of the direction determining output 21 of the configuration determining block 23.
The transfer number of digits determining scheme 42 does not activate the word transfer determining input 15 of the 8-bit DMA controller 7, whereupon its counters can be adjusted only by one.
At DMA transfer between the 8-bit input-output device 6 and the 8-bit memory 10 the DMA mode inputoutput device position determining output 26 is inactive and the 8-bit memory module position determining output 24 is active. The word transfer control block 16 and the configuration determining block 23 operate by the described manner. The blocking scheme 32 activates its 8-bit memory determining output 40 and does not activate its input-output device determining output 37. The memory position determining scheme 33 does not activate its memory cell position determining output 36. The direction of the intermediate bidirectional data buffer 8 is defined in vice versa manner to that described. The 16-bit data bus of the 16-bit microprocessor system 1 is converted, and the data are transferred from the lower bidirectional data bus 2 to the upper bidirectional data bus 9 and vice versa.
At DMA transfer between the 8-bit input-output device 6 and the 8-bit memory 5, the DMA mode inputoutput device position determining output 26 and the 8bit memory module position determining output 24 of the configuration determining block 23 are inactive. The 16-bit data bus of the 16-bit microprocessor system 1 is not converted, and the data are transferred on the lower bidirectional data bus 2.
At DMA transfer between the 8-bit input-output device 11 and the 8-bit memory 10, the DMA mode inputoutput device position determining output 26 and the 8bit memory module position determining output 24 of the configuration determining block 23 are active. The 16bit data bus of the 16-bit microprocessor system 1 is not converted, and the data are transferred on the upper bidirectional data bus 9.
At DMA transfer between the 8-bit input-output device 11 and the 16-bit memory 3, the DMA mode inputoutput device position determining output 26 and memory type output 25 are active. At even address of the memory cell selected by the 8-bit DMA controller 7, the word transfer control block 16 does not activate its 16-bit memory byte position determining output 30. The blocking scheme 32 activates its 16-bit memory determining output 41 and input-output device determining output 37. The memory position determining scheme 33 does not activate its memory cell position determining output 36. The configuration determining block 23 converts the 16-bit data bus of the 16-bit microprocessor system 1, and the data are transferred through the intermediate bidirectional data buffer 8 from the upper bidirectional data bus 9 to the lower bidirectional data bus 2 and vice versa, in dependence upon the state of the direction determining output 21 of the configuration determining block 23. At odd address'of the selected memory cell, the word transfer control block 16 activates its 16-bit memory byte position determining output 30, and the memory position determining scheme 33 activates its memory cell position determining output 36. The configuration determining block 23 does not convert the 16-bit data bus of the 16-bit microprocessor system 1, and the data are transferred on the upper bidirectional data bus 9.
At DMA transfer between the 8-bit input-output device 6 and the 16-bit memory 3, the DMA mode inputoutput device position determining output 26 is inactive and memory type output 25 is active. At even address of the memory cell selected by the 8-bit DMA controller 7, the word transfer control block 16 does not activate its 16-bit memory byte position determining output 30. The blocking scheme 32 activates its 16-bit memory determining output 41 and does not activate its input-output device determining output 37. The memory position determining scheme 33 does not activate its memory cell position determining output 36. The configuration determining block 23 does not convert the 16-bit data bus of the 16-bit microprocessor system 1, and the data are transferred on the lower bidirectional data bus 2. At odd address of the selected memory cell, the word transfer control block 16 activates its 16-bit memory byte position determining output 30, and the memory position determining scheme 33 activates its memory cell position determining output 36. The configuration determining block 23 converts the 16-bit data bus of the 16-bit microprocessor system 1, and the data are transferred through the intermediate bidirectional data buffer 8 from the lower bidirectional data bus 2 to the upper bidirectional data bus 9 and vice versa, in dependence upon the state of the direction determining output 21 of the configuration determining block 23.
The upper data bus enable input 31 of the 16-bit memory 3 is opposite to the least significant bit 13 of the address outputs 12 of the 8-bit DMA controller 7.
When the source of the DMA request 19 is the 16-bit input-output device 4 and the memory cell selected by the 8-bit DMA controller 7 belongs to the 8-bit memory 5 ot 10, the memory type output 25 is inactive and the word transfer control block 16 activates its byte transfer enable output 29. The 16bit input-output device 4 monitors the state of the least significant address bit 13 of the 8-bit DMA controller 7 address outputs 12 and the upper bus enable output 31 of the word transfer control block 16, and at a difference it recognises byte transfer. At byte transfer the 16-bit input-output device 4 is converted into an 8-bit one and in dependence upon the transferred byte position, it controls its DMA mode input-output device position determining output 26.
The remaining blocks and schemes of the device operate according to one of the hereinbefore described methods.
When the source of the DMA request 19 is the 16-bit input-output device 4 and the memory cell selected by the 8-bit DMA controller 7 belongs to the 16-bit memory 3, the memory type output 25 and the DMA mode input-output device type output 27 are active. At even address of the selected memory cell the 8-bit DMA controller 7 activates its word transfer determining output 15, the transfer number of digits determining block 42 recognises the beginning of the word transfer operation and does not activate its byte transfer enable output 29. The configuration determining block 23 does not operate. The data bus control scheme 43 activates its upper bus enable output 31. When the 8bit DMA controller activates its transfer type determining outputs 28, the transfer number of digits determining block 42 activates its word transfer determining output 15. At the end of the transfer operation, the 8-bit DMA controller 7 adjusts its counters by two and transfers the data word by the 16bit data bus. At odd address of the selected memory cell the 8-bit DMA controller 7 does not activate its word transfer determining output 15. the transfer number of digits determining block 4 ! 2 activates its byte transfer enable output 29 and the device operates according to one of the hereinbefore described methods.
The device for dynamic DMA transfer sizing can be designed as an integrated circuit and allows more than one 16-bit memory module and 16-bit input-output device to be connected to the microprocessor system.
According to the foregoing description, there is provided a device for dynamic DMA transfer sizing, which finds application in 16-bit computers and microprocessor systems. A problem has been to design a device for dynamic DMA transfer sizing, which would enable the performance of DMA byte and word transfer operations. This would enable the type of the DMA operation to be automatically determined during the DMA transfer in dependence upon the 8-bit DMA controller (7) word transfer determining output (15) and the number of digits of memory modules (5), (10) and (3) and input-output devices (6), (11) and (4) at an arbitrary number of the transferred bytes and start memory address. The problem is solved by a device for dynamic
DMA transfer sizing wherein the 16-bit data bus of the 16-bit microprocessor system (1) is converted into an 8-bit data bus at byte transfer operation, whereupon the 8-bit DMA controller (7) adjusts its counter by one. At word transfer operation the 16-bit data bus of the microprocessor system (1) is not converted into an 8-bit bus and the 8-bit DMA controller adjusts its counters by two. Advantages of the invention are that the transfer number of digits is automatically determined at the beginning of the transfer operation and is not restricted by the parity of the byte count and start address.
Claims (4)
- CLAIMS : 1. A device for dynamic DMA transfer sizing, which contains a 16-bit microprocessor system (1), the lower bidirectional data bus (2) of which is connected to the lower bidirectional data bus of a 16-bit memory (3) and of 16-bit input-output devices (4), to the bidirectional data buses of an 8-bit memory (5), of 8bit input-output devices (6) and of an 8-bit DMA controller (7), and to the data inputs-outputs"A"of an intermediate data buffer (8), the upper bidirectional data bus (9) of the 16-bit microprocessor system (1) being connected to the upper data bus of the 16-bit memory (3) and 16-bit input-output devices (4), to the bidirectional data buses of an 8-bit memory (10) and 8-bit input-output devices (11) and to the data inputs-outputs"B"of the bidirectional intermediate data buffer (8), the address outputs (12) of the 16-bit microprocessor system (1) being connected to the address outputs of the 8-bit DMA controller (7) and to the address inputs of the 16-bit memory (3), the first and second 8-bit memories (5, 10), 8-bit input-output devices (6, 11) and 16-bit input-output devices (4), the microprocessor bus request output (17) and the microprocessor bus acknowledge input (18) of the 8-bit DMA controller (7) being connected to the corresponding input and output of the 16-bit microprocessor system (1), wherein the least significant address bit (13), the DMA address enable output (14) and the word transfer determining input-output (15) of the 8-bit DMA controller (7) are connected to corresponding inputs and input-output of the word transfer control block (16), the DMA request inputs and the request acknowledge outputs (20) of the 8-bit DMA controller (7) are connected to the corresponding inputs and outputs of the 8-bit input-output devices (6) and (11), and the 16-bit input-output device (4), the direction determining output (21) and the system converting output (22) of the configuration determining block (23) are connected to the corresponding inputs of the intermediate bidirectional data buffer (8), the 8-bit memory position determining output (24) is connected to the corresponding output of the 8-bit memories (5) and (10), the memory type output (25) of the 8-bit memories (5) and (10) and the 16-bit memory is connected to the corresponding inputs of the configuration determining block (23) and word transfer control block (16), the DMA mode input-output device position determining output (26) of the 8-bit input-output devices (6) and (11) and of the 16-bit input-output device (4) are connected to the corresponding input of the configuration determining block (23), the DMA mode input-output device type output (27) of the 8-bit input-output devices (6) and (11) and of the 16-bit input-output device (4) are connected to the corresponding input of the word transfer control block (16), the transfer type determining outputs (28) of the- 8-bit DMA controller (7) are connected to the corresponding inputs of the configuration determining block (23) and the word transfer control block (16), the byte transfer enable output (29) and the 16-bit memory byte position determining output (30) of the word transfer control block (16) are connected to the corresponding inputs of the configuration determining block (23), and the upper bus enable output (31) is connected to the corresponding input of the 16-bit memory (3) and the 16-bit input-output device (4).
- 2. A device for dynamic DMA transfer sizing according to claim 1, wherein the configuration determining block (23) contains a blocking scheme (32), memory position determining scheme (33), system converting scheme (34) and a direction determining scheme (35), the memory type input (25), 8-bit memory position determining input (24) and the DMA mode inputoutput device position determining output (26) of the configuration determining block (23) being inputs of the blocking scheme (32), the memory cell position determining output (36) of the memory position determining scheme (33) being connected to the corresponding input of the system converting scheme (34) and the direction determining scheme (35), the byte transfer enable input (29) of the configuration determining block (23) being an input of the blocking scheme (32), memory position determining scheme (33), system converting scheme (34) and direction determining scheme (35), the transfer type determining outputs (28) of the configuration determining block (23) being direction inputs of the direction determining scheme (35), the 16-bit memory byte position determining output (30) of the configuration determining block (23) being an input of the memory position determining scheme (33), the input-output device determining output (37) of the blocking scheme (32) being connected to the corresponding inputs of the system converting scheme (34) and direction determining scheme (35), the converting condition determining output (38) of the system converting scheme (34) being connected to the corresponding input of the direction determining scheme (35), whose output for selected direction (39) is an input of the system converting scheme (34), the 8-bit memory determining output (40) and the 16-bit memory determining output (41) of the blocking scheme being inputs of the memory positi6n determining scheme (33), and the direction determining output (21) and the system converting output (22) of the configuration determining block (23) being outputs of the schemes (34) and (35).
- 3. A device for dynamic DMA transfer sizing according to claim 1 or 2, characterised in that the word transfer control block (16) contains a transfer number of digits determining block (42) and a data bus control scheme (43), the memory type input (25), the DMA mode input-output device type output (27), the transfer type determining outputs (28), the DMA address enable output (14) and the byte transfer enable output (29) of the word transfer control block (16) being inputs and an output of the transfer number of digits determining block (42), the least significant address bit (13), the 16-bit memory byte position determining output (30) and the upper bus enable output (31) of the word transfer control block (16) being an input and outputs of the data bus control scheme (43), the word transfer determining input-output (15) of the word transfer control block (16) being an input-output of the data bus control scheme (43) and the byte transfer enable input (29) of the transfer number of digits determining block (42) being an input of the data bus control scheme (43).
- 4. A device for dynamic DMA transfer sizing substantially as hereinbefore described with reference to Figures 1 to 3 of the accompanying drawings.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| BG8313088A BG47775A1 (en) | 1988-02-25 | 1988-02-25 | Device for dynamic controlling of volume size in direct access |
| IT8805167A IT8805167A0 (en) | 1988-05-25 | 1988-05-25 | LUMINOUS BRACELET WITH A WATCH, OR A PHOTO, OR AN AMULET, OR AN EMBLEM, WHICH CAN BE LIGHTED THROUGH LEDS, BATTERIES AND CIRCUITS CONTAINED IN THE SAME. |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8903790D0 GB8903790D0 (en) | 1989-04-05 |
| GB2216304A true GB2216304A (en) | 1989-10-04 |
Family
ID=25663353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8903790A Withdrawn GB2216304A (en) | 1988-02-25 | 1989-02-20 | Dynamic DMA transfer sizing |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2216304A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2246223B (en) * | 1990-07-20 | 1994-08-03 | Mitsubishi Electric Corp | DMA control device |
-
1989
- 1989-02-20 GB GB8903790A patent/GB2216304A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2246223B (en) * | 1990-07-20 | 1994-08-03 | Mitsubishi Electric Corp | DMA control device |
| US5499383A (en) * | 1990-07-20 | 1996-03-12 | Mitsubishi Denki Kabushiki Kaisha | DMA control device controlling sequential storage of data |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8903790D0 (en) | 1989-04-05 |
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| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |