JPH0424857A - Bus arbitration method for multi-cpu system - Google Patents

Abstract

PURPOSE:To simplify the system constitution, to attain the reduction of cost and to improve the reliability by applying the bus arbitration method in a multi-CPU system. CONSTITUTION:The mutual wired OR connection is secured via the ID cords 4 between the signals showing the priority of each CPU 1 shown in the n-bit digital signals and all CPU 1. Then the connection is secured to a pull-up resistance at the termination. Each CPU 1 checks the idle state of a bus when acquiring the bus and then performs the check for acquisition of the bus with the proper waiting time set by its own priority when the bus is busy. In this case, the waiting time of each CPU 1 is shortened less as its own priority is set higher. Thus the system constitution is simplified with application of such bus arbitration method. Then the cost is reduced and the reliability is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Fields] The present invention is directed to a multi-CPU system that can be applied to various multi-CPU systems, such as a multi-CPU system for a controller that requires high-performance processing functions. Concerning bus arbitration methods.

[Prior Art] In a multi-CPU system, each CPU is responsible for highly urgent processing, and slave devices (memory, dual port memory,
Ilo, etc.), the access requests of each CPU are satisfied, and information is quickly exchanged between the CPUs, thereby realizing high-performance processing functions as a whole. Therefore, the following functions are required for bus arbitration.

(1) When a certain CPU issues an access request to the system bus when the bus is in an empty state, that CPU is granted access rights.

(2) While a CPU granted access rights is accessing a slave device on the system bus, exclusiveness is provided to prevent other CPUs from accessing it without permission.

(3) When the CPUs of Ii issue requests for access to the system bus at the same time, the CPUs are arbitrated in a certain order and the access right is given to the CPU with the highest priority.

(4) A CPU that lost in the previous arbitration can return to arbitration at the next arbitration.

An example of a connection circuit using a conventional bus arbitration method based on such a bus arbitration function is shown in the fourth section.
and FIG.

FIG. 4 shows a method called a serial method or daisy chain. In this method, the priority of each CPU is fixed by the connections on the system bus.

The permission power 411 of the CPU 41 with the highest priority is connected to the permission level, and its permission output 412 is sent to the next priority CP.
Each CPU U41.41. ...is connected in series.

When the higher-ranking CPU 41 obtains the right to access the bus, it outputs a disallowed level to the permission output 412 and prohibits bus access to the CPU 41 lower than itself.

FIG. 5 shows a method called a parallel method. This method uses a priority encoder 5 provided on the system bus.
14, the bus request output 513 of each CPU 51, 51 .

In both of the above methods, the arbitration function is realized by devising the wiring on the system bus, which results in complicated wiring, which poses problems in terms of cost reduction, ease of maintenance, etc.

[Problems to be Solved by the Invention] As described above, in the conventional arbitration method, the wiring is complicated and a priority encoder is required on the system bus, resulting in a complicated system configuration. Therefore, there are problems in that the cost of the entire system increases, and malfunctions and failure rates increase due to poor wiring and the like.

The present invention has been made in view of the above circumstances, and provides a bus arbitration method for a multi-CPU system that can solve the above-mentioned conventional problems, has a simple configuration, reduces costs, and improves reliability. The purpose is to

[Means for Solving the Problems] In the bus arbitration method of the present invention, a plurality of CPUs and a plurality of slave devices are connected to a common system bus, and a certain CPU can access a specific slave device. In the system, every CPU has its own priority, and this priority is expressed as an n-bit digital signal that is wired or connected to all CPUs. Each CPU constantly monitors these signals and can detect the idle state of the bus. Each CPU checks the availability of the bus when it needs to access the bus.

At this time, if you recognize the availability, you can change your priority
It is superimposed on the D code, and if the bus is not in an empty state, it waits for a waiting time Tv until the bus becomes empty. A check is made after a certain period of time has elapsed since the priorities have been superimposed, and if they match the priority, the bus access right is obtained, but if they do not match, the user waits for an additional waiting time Tv after the bus becomes empty. At this time, the higher the priority of each CPU, the shorter the waiting time Tν of each CPU.

[Operation] As described above, the present invention transmits the signal representing the priority of each CPU expressed as an n-bi soto digital signal to all CPUs.
When connected to the PU by wire and each CPU acquires the bus,
Traditionally, connections are made on the system bus by checking the bus free status and checking whether the bus is available with a specific waiting time Tw that is set according to the own priority when the bus is not free. The complicated wiring and priority encoders that were previously used can be eliminated, and the system bus can be configured with a flat cable, except for the problem of power supply. By employing the arbitration method (7) of the present invention described above, it is possible to simplify the system configuration, reduce costs, and improve reliability.

[Embodiment] FIGS. 1 to 3 are diagrams for explaining one embodiment of the present invention.

FIG. 1 is a connection circuit diagram that realizes bus arbitration according to an embodiment of the present invention. Each CPUI is wired-OR connected to each other using a 4-bit ID code 4, and is connected to a pull-up resistor 3 at the end. ID code 4 is expandable to n bits. Further, the ID code 4 is driven by a tri-state or an oven collector, and is pulled up to "H" (Hlgh) when the bus is in an empty state. ID code 4 is an active low illogical expression, and therefore corresponds to ID code 0 (zero) when the system bus is in an empty state. All CPUI, l
, . . . constantly monitors ID code 4, and can determine whether the system bus is idle or not.

FIG. 2 is a correspondence table between the priority order of each CPU and the waiting time Tw in one embodiment of the present invention. The higher the priority, the shorter the waiting time TV. In this example, the smaller the number, the more
The priority is high, but the opposite is also possible.

FIG. 3 is a state transition diagram of bus arbitration according to an embodiment of the present invention.

Next, the functions of one embodiment of the present invention will be explained with reference to FIG.

All CPUs have the functions shown in FIG. 3, and can output and monitor the ID code 4. Immediately after a reset or due to completion/cancellation of system bus access, the CPUI transitions to idling state 5 and is on standby.

Of course, each CPUI, l, . . . may have its own local bus in addition to the system bus. When a CPU attempts to access the system bus, it transitions from idle state 5 to busy check state 6,
Check if the system bus is empty. As a result of the check, if the system bus is in an empty state (bus free), the state transits to the request state 7, and if not, the state transits to the request hold state 9. When the request state 7 is reached, the state is changed to the code check state 8 while outputting its own priority to the ID code 4. The waiting time tv for transitioning from request state 7 to code check state 8 is short enough to be unaffected by the time delay of the driver that superimposes its own priority on ID code 4 and the receiver that monitors ID code 4. choose. This waiting time tν is
UI, 1. ....

Must be a unified value. The priority is the only number allowed on the system bus, and there must be no other CPU with the same priority. Code check status 8
Now, check whether the monitoring result of ID code 4 matches your priority order. If they match, the state transitions to access state IO; otherwise, the state transitions to request hold state 9. Only after transitioning to access state 10 does the CPUI gain access to the system bus. Once the system bus access is complete or reset,
Original idling condition! B. Return to 5. When the request hold state 9 is entered, the device continues to wait until the system bus becomes empty, waits for a waiting time tν corresponding to its own priority, and checks the empty state of the system bus again. If the system bus is in an empty state, a transition is made to request state 7, and the above-described bus arbitration is restarted.

[Effects of the Invention] By adopting the bus arbitration method for a multi-CPU system according to the present invention as explained above,
Wiring for bus arbitration becomes extremely simple, and batch wiring using a flat cable or the like becomes possible.

As a result, the overall system configuration can be simplified, wiring work can be simplified, and costs can be reduced and reliability can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a connection circuit configuration of a bus arbitration mechanism according to an embodiment of the present invention, FIG. 2 is a diagram showing the correspondence between priority order and waiting time Tw in an embodiment of the present invention, and FIG. The figure is a state transition diagram of bus arbitration processing according to an embodiment of the present invention, and FIGS. 4 and 5 are block diagrams showing connection circuit configurations of conventional bus arbitration mechanisms, respectively. ■... CPU, 2... Slave device, 3... Bullab resistance, 4... Bow D code, 5... Idling state, 6... Busy check state, 7... Request state, 8... ...Code check state, 9...Request hold state, 10...Access state.

Claims (1)

[Claims] In a multi-CPU system in which multiple CPUs and multiple slave devices are connected to a common system bus, and the CPU can access a specific slave device, each of the CPUs
The PU recognizes the idle state of the system bus from the signal state on the n-bit signal line for system bus control connected to all CPUs by wire OR, and has means for outputting code information unique to itself when acquiring the bus. , each having a unique priority, and the higher the priority, the shorter the waiting time at the time of bus contention is set.