KR100194985B1 - Message exchange device between processor modules - Google Patents

Abstract

The present invention relates to an apparatus for exchanging messages between processor modules, and more particularly to an apparatus for exchanging messages between processor modules on a VME bus.

In the message exchanger between the conventional processor modules, the master processor module can always use the VME bus, but the slave processor module cannot access the master processor module due to the inability to use the VME bus. There is a problem in that economic efficiency is lowered due to the use of a high-priced dual port memory separately for message transmission.

In the present invention, since both the master processor module and the slave processor module can use the VME bus, the use efficiency of the VME bus can be improved, and the economical efficiency can be improved because the message can be transmitted without using a high-cost dual port memory.

Description

Message exchange device between processor modules

The present invention relates to a message exchange device between processor modules, and more particularly, to a message exchange device between processor modules for efficiently exchanging messages between processor modules on a VME bus.

In general, a system such as an electronic switch and the like is provided with a plurality of processor modules, which perform the functions given while exchanging messages through a common connected bus.

In the related art, when a message is exchanged between processor modules through a VME bus, the method is illustrated in FIG. 1. That is, the master processor module 10 and the slave processor module 20 exchange messages through a VME bus connected in common. The master processor module 10 includes a CPU 11 and the slave processor module 20. The dual port memory 21 and the CPU 22 are provided, and the local bus LB is connected between the dual port memory 21 and the CPU 22.

The slave processor module 20 is in a position to request service from the master processor module 10, and when there is no service request, the CPU 22 records a message in the dual port memory 21. Meanwhile, the master processor module 10 periodically checks the dual port memory 21 and if there is a message, provides a service corresponding to the message and records the result in the dual port memory 21 of the slave processor module 20. do. The dual port memory 21 transfers input / output messages. The dual port memory 21 is composed of two circular queues as shown in FIG. 2, and is composed of a transmitting circular queue and a receiving circular queue. The transmitting circular queue is used when the CPU 22 of the slave processor module 20 wants to transmit a message to the master processor module 10 side, and the receiving circular queue is the CPU 22 of the slave processor module 20. Is used to receive a message supplied from the master processor module 10. Such a circular queue is managed as a pointer of a head and a tail. In a state where a message is not recorded, the head and the tail point to the same recording location, and when the message is recorded, the head increases and the next message is recorded. The location is pointed out, and when the recorded message is read and printed, the tail is increased to point to the location of the next message to be read, and when the message is full, the message is no longer recorded. That is, the dual port memory 21 is connected to the VME bus and the local bus LB, and performs a function of transferring a message between the master processor module 10 and the slave processor module 20.

In the above-described message exchanger between processor modules, the master processor module 10 may always use the VME bus, but the slave processor module 20 may access the master processor module 10 due to the inability to use the VME bus. There is a problem in that the efficiency of using the VME bus is lowered and the economical efficiency is lowered due to the use of the high-priced dual port memory 21 separately for message transmission.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and both the master processor module and the slave processor module use the VME bus, thereby improving the use efficiency of the VME bus and even if a high-cost dual port memory is not used separately. It is an object of the present invention to provide a message exchange device between processor modules to improve the economics by passing the.

In order to achieve the above object, a feature of the present invention is a message exchange device between processor modules for exchanging messages through a commonly connected VME bus, which receives a bus use request signal and outputs a bus use permission signal. An arbitration unit 30; A slave processor module 50 for outputting a bus use request signal to the bus arbitration unit 30 and outputting a message through a VME bus when a bus use permission signal is applied; The bus arbitration unit 30 outputs a bus use request signal, and when a bus use permission signal is applied from the bus arbitration unit 30, the slave processor module 50 is accessed through the VME bus and the slave processor is simultaneously accessed. By not outputting the bus usage permission signal to the module 50 side, the slave processor module 50 does not access itself through the VME bus, and does not output the bus usage request signal to the bus arbitration unit 30 side. If the bus use permission signal is applied from the bus arbitration unit 30 in the non-state state, the slave processor module 50 may access itself through the VME bus by outputting a bus use permission signal to the slave processor module 50. The master processor module 40 is provided.

By such a configuration, the present invention improves the efficiency of using the VME bus since both the master processor module and the slave processor module can use the VME bus, and can deliver messages without using a high-cost dual port memory. Will be improved.

1 is a block diagram showing a conventional message exchange device between processor modules.

FIG. 2 is a diagram showing a circular queue constituted by the dual port memory shown in FIG.

3 is a block diagram showing an apparatus for exchanging messages between processor modules according to the present invention;

4 is a configuration diagram of the master processor module shown in FIG.

5 is a configuration diagram of the slave processor module shown in FIG.

* Description of the symbols for the main parts of the drawings *

30: bus arbitration unit 40: master processor module

41: CPU 42: register

43: local memory 44: bus controller

50: slave processor module 51: CPU

52: Register 53: Local memory

54: bus controller

The message exchange device between the processor modules according to the present invention comprises a bus arbitration unit 30, a master processor module 40 and a slave processor module 50 as shown in FIG. The bus arbitration unit 30 performs a function of arbitrating use of the VME bus. The bus arbitration unit 30 receives a bus use request signal applied to the input terminal BR from the master processor module 40 and the slave processor module 50 and outputs the signal to the output terminal RG. ) Outputs a bus permission signal to the master processor module 40 side. The master processor module 40 outputs a bus use request signal to the bus arbitration unit 30 through the output terminal BR. When the bus use permission signal is applied to the input terminal BGIn from the bus arbitration unit 30, the VME bus is output. The slave processor module 50 cannot access the VME bus by accessing the slave processor module 50 and not outputting the bus permission signal to the slave processor module 50 through the output terminal (BGOut). When the bus use permission signal is applied from the bus arbitration unit 30 to the input terminal BGIn without outputting the bus use request signal to the bus arbitration unit 30 through the output terminal BR, the output terminal BGOut is applied. The slave processor module 50 uses the VME bus by outputting a bus use permission signal to the slave processor module 50. In addition, the slave processor module 50 outputs a bus use request signal to the bus arbitration unit 30 through the output terminal BR, and when the bus use permission signal is applied to the input terminal BGIn from the master processor module 40, the VME is applied. The master processor module 40 is accessed through the bus, and the bus use request signal is output to the bus arbitration unit 30 through the output terminal BR to allow the bus use permission signal from the master processor module 40 to the input terminal BGIn. If is not authorized, do not use the VME bus.

On the other hand, the master processor module 40 is composed of a CPU 41, a register 42, a local memory 43 and a bus controller 44 as shown in FIG. The local memory 43 is connected to the CPU 41 and the bus controller 44 via the local bus LB1 to transfer messages input and output between the CPU 41 and the VME bus. The bus controller 44 is connected to the slave processor module 50 via the VME bus, drives the VME bus under the control of the CPU 41, and detects that the slave processor module 50 drives the VME bus. The local bus use request signal BRL1 is output to the CPU 41 so that the slave processor module 50 can access the local bus LB1 by receiving the local bus use permission signal BGL1 from the CPU 41. . The register 42 receives the bus use request signal WB1 from the CPU 41, outputs a bus use request signal to the bus arbitration section 30 through the output terminal BR, and outputs the bus use request signal from the bus arbitration section 30. Receives the bus use permission signal from the input terminal BGIn and outputs the bus use permission signal GB1 to the CPU 41 side, and outputs the bus use request signal to the bus arbitration unit 30 through the output terminal BR. If the bus usage permission signal from the bus arbitration unit 30 is received through the input terminal BGIn without the output, the bus usage permission signal is output to the slave processor module 50 through the output terminal BGOut.

In addition, the slave processor module 50 includes a CPU 51, a register 52, a local memory 53, and a bus controller 54, as shown in FIG. The local memory 53 is connected to the CPU 51 and the bus controller 54 via the local bus LB2 and transfers messages input and output between the CPU 51 and the VME bus. The bus controller 54 is connected to the master processor module 40 via the VME bus, drives the VME bus under the control of the CPU 51, and detects that the master processor module 40 drives the VME bus. The local bus use request signal BRL2 is output to the CPU 51 so that the master processor module 40 can access the local bus LB2 by receiving the local bus use permission signal BGL2 from the CPU 51. . The register 52 receives the bus use request signal WB2 from the CPU 51 and outputs the bus use request signal to the bus arbitration unit 30 through the output terminal BR, and outputs the master processor module 40 from the master processor module 40. A bus use permission signal is applied to the input terminal BGIn, and the bus use permission signal GB2 is output to the CPU 51 side.

That is, the bus arbitration unit 30 receives a bus use request signal from the master processor module 40 and the slave processor module 50 to mediate the use of the VME bus. When the bus use request signal is applied, the bus use permission signal is output to the master processor module 40 through the output terminal BG. At this time, when the master processor module 40 receives the bus use permission signal from the bus arbitration unit 30, the master processor module 40 outputs the bus use request signal to the bus arbitration unit 30. By not outputting the bus permission signal to the slave processor module 50, the slave processor module 50 stops using the VME bus and accesses the local bus LB2 of the slave processor module 50 through the VME bus, and the bus arbitration unit ( When receiving the bus use permission signal from 30), if it has not output the bus use request signal to the bus arbitration unit 30 side, the slave processor module outputs a bus use permission signal to the slave processor module 50 side. Let 50 access its local bus LB1 via the VME bus. Therefore, when both the master processor module 40 and the slave processor module 50 output the bus use request signal to the bus arbitration unit 30 side, the master processor module 40 preferentially uses the VME bus. When only the slave processor module 50 outputs a bus use request signal to the bus arbitration unit 30 side, the slave processor module 50 uses the VME bus.

An apparatus for exchanging messages between processor modules of the present invention configured as described above operates as follows.

For example, the CPU 41 of the master processor module 40 outputs the bus use request signal WB1 to the register 42 side, so that the register 42 is connected to the bus arbitration unit 30 via the output terminal BR. When the bus use request signal is output to the bus arbitration unit 30, the bus arbitration unit 30 outputs a bus use permission signal to the master processor module 40 through the output terminal BG. At this time, when the register 42 receives the bus use permission signal from the bus arbitration unit 30 through the input terminal BGIn, the register 42 outputs the bus use permission signal GB1 to the CPU 41 and simultaneously outputs the output BGOut. ) Does not output the bus permission signal to the slave processor module 50. Accordingly, the CPU 41 controls the bus controller 44 to drive the VME bus to access the local bus LB2 of the slave processor module 50. The bus controller 54 of the slave processor module 50 When the master processor module 40 detects that the VME bus is driven, it outputs the local bus use request signal BRL2 to the CPU 51 and receives the local bus permission signal BGL2 from the CPU 51 to receive the master processor. Allow module 40 to access local bus LB2. At this time, the local memory 43 and the local memory 53 transmit messages input and output through the VME bus.

Further, for example, the CPU 51 of the slave processor module 50 outputs the bus use request signal WB2 to the register 52 side so that the register 52 receives the bus arbitration unit 30 through the output terminal BR. When outputting a bus use request signal to the side, the bus arbitration unit 30 outputs a bus use permission signal to the master processor module 40 side through the output terminal BG to input the input terminal BGIn from the master processor module 40. When the bus use permission signal is applied to the register 52, the register 52 outputs a bus use permission signal GB2 to the CPU 51 side. Accordingly, the CPU 51 controls the bus controller 54 to drive the VME bus, thereby accessing the local bus LB1 of the master processor module 40. The bus controller 44 of the master processor module 40 When the slave processor module 50 detects that the VME bus is driven, it outputs the local bus use request signal BRL1 to the CPU 41 and receives the local bus use permission signal BGL1 from the CPU 41 to receive the slave processor. Allow module 50 to access local bus LB1. At this time, the local memory 43 and the local memory 53 transmit messages input and output through the VME bus.

As described above, the present invention improves the efficiency of using the VME bus because both the master processor module and the slave processor module can use the VME bus, and can deliver messages without using a high-cost dual port memory. Let's go.

Claims (3)

In the message exchange device between processor modules for exchanging messages through a commonly connected VME bus, A bus arbitration unit 30 for receiving an applied bus use request signal and outputting a bus use permission signal; A slave processor module 50 for outputting a bus use request signal to the bus arbitration unit 30 and outputting a message through a VME bus when a bus use permission signal is applied; The bus arbitration unit 30 outputs a bus use request signal, and when a bus use permission signal is applied from the bus arbitration unit 30, the slave processor module 50 is accessed through the VME bus and the slave processor is simultaneously accessed. By not outputting the bus usage permission signal to the module 50 side, the slave processor module 50 does not access itself through the VME bus, and does not output the bus usage request signal to the bus arbitration unit 30 side. If the bus use permission signal is applied from the bus arbitration unit 30 in the non-state state, the slave processor module 50 may access itself through the VME bus by outputting a bus use permission signal to the slave processor module 50. Message exchange device between the processor module, characterized in that it comprises a master processor module (40). The method of claim 1, The master processor module 40 includes: a local memory 43 connected to the CPU 41 via a local bus LB1 and transferring a message input / output between the CPU 41 and the VME bus; When connected to the slave processor module 50 via a VME bus, the VME bus is driven under the control of the CPU 41, and when the slave processor module 50 detects that the VME bus is driven, the CPU ( A local bus use request signal BRL1 is output to the 41 side to receive the local bus use permission signal BGL1 from the CPU 41 so that the slave processor module 50 can access the local bus LB1. A bus controller 44; Receives a bus use request signal WB1 from the CPU 41, outputs a bus use request signal to the bus arbitration unit 30, and receives a bus use permission signal from the bus arbitration unit 30. The bus use permission signal GB1 is output to the CPU 41 side, and the bus use permission from the bus arbitration section 30 is not output to the bus arbitration section 30. And a register (42) for outputting a bus use permission signal to the slave processor module (50) when receiving a signal. The method of claim 1, The slave processor module 50 includes: a local memory 53 connected to a CPU 51 via a local bus LB2 and transferring a message input / output between the CPU 51 and the VME bus; Connected to the master processor module 40 via a VME bus to drive the VME bus under the control of the CPU 51, and when the master processor module 40 detects that the VME bus is driven, the CPU ( A local bus use request signal BRL2 is output to the 51 side to receive the local bus use permission signal BGL2 from the CPU 51 so that the master processor module 40 can access the local bus LB2. A bus controller 54; Receives a bus use request signal WB2 from the CPU 51, outputs a bus use request signal to the bus arbitration unit 30, and receives a bus use permission signal from the master processor module 40. And a register (52) for outputting a bus use permission signal (GB2) on the CPU (51) side.