GB2215516A - A method of producing a compound semiconductor device - Google Patents
A method of producing a compound semiconductor device Download PDFInfo
- Publication number
- GB2215516A GB2215516A GB8818768A GB8818768A GB2215516A GB 2215516 A GB2215516 A GB 2215516A GB 8818768 A GB8818768 A GB 8818768A GB 8818768 A GB8818768 A GB 8818768A GB 2215516 A GB2215516 A GB 2215516A
- Authority
- GB
- United Kingdom
- Prior art keywords
- conductive layer
- gaas substrate
- semi
- elements
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 150000001875 compounds Chemical class 0.000 title claims description 14
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000000137 annealing Methods 0.000 claims abstract description 19
- 239000002019 doping agent Substances 0.000 claims abstract description 12
- 229910052731 fluorine Inorganic materials 0.000 claims abstract 2
- 239000011737 fluorine Substances 0.000 claims abstract 2
- 125000001153 fluoro group Chemical group F* 0.000 claims 1
- 238000009826 distribution Methods 0.000 abstract description 12
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 abstract 5
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 29
- 235000012431 wafers Nutrition 0.000 description 12
- 239000013078 crystal Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004943 liquid phase epitaxy Methods 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- -1 silicon ions Chemical class 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
- H01L21/2656—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds characterised by the implantation of both electrically active and inactive species in the same semiconductor region to be doped
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- General Physics & Mathematics (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Recrystallisation Techniques (AREA)
Abstract
The method includes a first process of ion implanting elements 3 such as fluorine into an epitaxial layer 8 such as gallium arsenide, which elements are electrically inactive with the layer and a second process of annealing the layer. Another method includes a first process of ion implanting elements into a semi-insulative GaAs substrate, which elements are electrically inactive with the semi-insulative GaAs substrate, a second process of ion implanting n type or p type dopants into the semi-insulative GaAs substrate, and a third process of annealing the GaAs substrate so as to activate the dopants to produce a conductive layer. The layer 8 has a more uniform electrical conductivity distribution over its area than prior art devices. <IMAGE>
Description
A Method of Producing A Compound Semiconductor Device
FIELD OF THE INVENTION
The present invention relates to a method of producing a compound semiconductor device, and more particularly to that for producing a conductive layer having an uniform dopant concentration and superior in the reproducibility between wafers.
BACKGROUND OF THE INVENTION
Figures 3(a) and (b) are cross-sectional views showing a prior art method of producing a compound semiconductor device. In figure 3, reference numeral 1 designates a semiinsulative GaAs substrate and reference numeral 2 designates a resist. Reference numeral 5 designates Si ions and reference numeral 6 designates a region into which Si ions 5 are implanted. Reference numeral 7 designates an n type conductive layer obtained by annealing the Si ion implanted layer 6.
The production method will be described.
At first, a pattern comprising the resist 2 is produced on the semi-insulative GaAs substrate 1, and Si ions in the region 6 are selectively implanted thereinto (figure 3(a)).
Next, an annealing is conducted at about 800 C after removing the resist 2, thereby to activate the silicon ions and to produce an n type conductive layer 7 (figure 3(b)).
By conducting such selective ion implantation and annealing, it is easily possible to produce an n type conductive layer 7 at a desired position in the semi-insulative GaAs substrate 1.
In figure 5 showing a plan view of a wafer, the diagonal line sections represent portions in the wafer where dislocation density of the GaAs substrate 1 is likely to be high, and figure 4(b) shows conductivity distribution of the n type conductive layer 7 in the wafer surface in the direction of A - A' in figure 5. As is apparent from figures 4(b) and 5, the conductivity of the n type conductive layer 7 increases at a portion where GaAs substrate dislocation is likely to be high in the wafer surface, and the conductivity distribution represents a W shaped one in the direction of A - A' in figure 5. Herein, this is presumed to be due to point defects and impurities generally existing in the crystal independently on the type of crystal growth at dislocation portions, whereby the carrier concentration of the conductive layer is varied.
The reasons therefore are thought to be as follows.
Firstly, when it is supposed that there are a larger number of point defects of interstitial As than those of interstitial Ga, and there are larger number of point defects of Ga vacancy than those of As vacancy, when Si is implanted as dopants, Si is likely to replace in place of Ga at the dislocation portion. This replacement means the conductivity type changes toward n type. Secondly, trap centers or acceptor impurities are gettered at the dislocation portion, thereby increasing the number of electrons.
In this prior art production method of a compound semiconductor device, the n type conductive layer is affected a strong influence by such as dislocations of semiinsulative GaAs substrate in the process of activating Si ions by annealing, and therefore, the carrier concentration distribution becomes non-uniform and the electric conductivity distribution shows a W shaped one in the radial direction in the wafer surface.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of producing a compound semiconductor device capable of obtaining a uniform carrier concentration distribution and a superior reproducibility between wafers without being affected by such as dislocations of the semi-insulative GaAs substrate in the annealing process.
Other objects and advantages of the present invention will become apparent from the detailed description given hereinafter; it should be understood, however, that the detailed description and specific embodiment are given by way of illustration only, since various changes and modifications within the spirit and the scope of the invention will become apparent to those skilled in the art from this detailed description.
According to an aspect of the present invention, an annealing is conducted after implanting elements into the conductive layer, which elements are electrically inactive against the conductive layer. Accordingly, the carrier concentration of the conductive layer becomes uniform.
According to another aspect of the present invention, in producing an n type or p type conductive layer by conducting annealing after ion implanting n type or p type dopants into GaAs substrate, elements electrically inactive against GaAs are implanted into the semi-insulative GaAs substrate before implanting dopants. Accordingly, influences due to dislocations in the semi-insulative GaAs substrate are reduced, the variation in carrier concentration of the conductive layer is smoothed, the electric conductivity of the conductive layer is made uniform, and the carrier concentration profile is produced steep.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a cross-sectional view for explaining a method of producing a compound semiconductor device according to a first embodiment of the present invention:
Figures 2(a) to (c) are cross-sectional views for explaining a method of producing a compound semiconductor device as a second embodiment of the present invention;
Figures 3(a) and (b) are cross-sectional views for explaining a second prior art method of producing a compound semiconductor device;
Figure 4 (a) is a diagram showing conductivity distribution of the n type conductive layer in the radial direction according to the second embodiment of the present invention;
Figure 4 (b) is a diagram showing conductivity distribution of the n type conductive layer in the radial direction of the second prior art semiconductor device;;
Figure 5 is a plan view showing regions of the wafer surface where dislocation density is likely to be high in the wafer surface of a second prior art device; and
Figure 6 is a diagram showing carrier concentration profile of the n type conductive layer in the depth direction of the GaAs substrate of the second embodiment of the present invention (curve a) and carrier concentration profile of the n type conductive layer in the depth direction of the GaAs substrate of the second prior art device (curve b).
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
An embodiment of the present invention will be described in detail with reference to the drawings.
Figure 1 is a cross-sectional view showing a method of producing a compound semiconductor device according to the first embodiment of the present invention In figure 1, reference numeral 1 designates a semi-insulative GaAs substrate, reference numeral 3 designates F ions, and reference numeral 8 designates an n type Si epitaxial growth layer.
In the production method of this embodiment, an n type epitaxial growth layer 8 is produced on a semi-insulative
GaAs substrate 1 by VPE (Vapor Phase Epitaxy), MBE (Molecular Beam Epitaxy), MOCVD (Metal Organic Chemical
Vapor Deposition), or LPE (Liquid Phase Epitaxy), and F ions 3 which are electrically inactive against GaAs crystal are implanted into the n type Si epitaxial growth layer 8 as a conductive substrate, and thereafter, an annealing is conducted. By conducting ion implantation of F ions into the conductive layer and conducting annealing, it is possible to get rid of variation in carrier concentration of the epitaxial growth layer 8 over the wafer surface due to influences by dislocations or point defects, thereby enhancing the uniformity of the electric conductivity.
Herein, the conductive substrate may not be restricted to an epitaxial growth layer 8, but may be other material such as n type GaAs substrate with the same effects as described above.
Figures 2(a) to (c) are diagrams for explaining a method of producing a compound semiconductor device as a second embodiment of the present invention. In figure 2, reference numeral 1 designates a semi-insulative GaAs substrate and reference numeral 2 designates a resist.
Reference numeral 3 designates F ions and reference numeral 4 designates a region into which F ions 3 are implanted.
Reference numeral 5 designates Si ions and reference numeral 6 designates a region into which Si ions 5 are implanted.
Reference numeral 7 designates an n type conductive layer obtained by annealing the Si ion implanted layer 6.
The production method will be described with reference to figure 2.
A pattern of resist 2 is produced on the semiinsulative GaAs substrate 1, and F ions 3 which are electrically inactive against GaAs are selectively ion implanted into the GaAs substrate 1( figure 2(a)). Next, Si ions 5 which are n type dopants are implanted into the portions where F ions are implanted (figure 2 (b)), and after the resist 2 is removed, an annealing at about 800 C is conducted to activate Si ions 5, thereby to produce an n type conductive layer 7.
Figure 4(a) shows conductivity distribution of the n type conductive layer 7 in the radial direction of the wafer surface of the second embodiment. Contrary to that the conductivity distribution of the n type conductive layer of the prior art device shows a W-shaped one, that of the present invention shows a flat one. That is, when elements electrically inactive against GaAs are implanted into GaAs before implanting dopants, influences of dislocations of the
GaAs substrate which have been conventionally resulting a problem are relaxed and the carrier concentration distribution of the n type conductive layer can be made uniform.
Figure 6 comparatively shows carrier concentration profile (curve a) in the depth direction of the GaAs substrate 1 of the n type conductive layer 7 produced in the above-described embodiment and that (curve b) in the prior art device. In the prior art, Si ions can be diffused freely between the crystal lattices of GaAs at the implantation of Si ions 5 and are likely to be diffused in the depth direction in the substrate, and therefore, it is difficult to make the tail of the carrier concentration profile steep. When F ions 3 are ion implanted as in the present invention, however, the crystal lattices of the GaAs substrate are destroyed and diffusion of Si ions are obstructed by that and Si ions are made difficult to be diffused freely in the depth direction.Accordingly, the peak of the carrier concentration profile at the neighborhood of the surface increases, and on the other hand, the tail becomes steep.
In the above illustrated embodiment, a semi-insulative
GaAs substrate 1 is used as a substrate, but other compound semiconductor substrate may be used.
Furthermore, instead of Si ions, other n type ions s.uch as Se or S, or p type ions such as Mg, Be, or Zn may be used.
Furthermore, as elements electrically inactive against
GaAs which constitutes a conductive layer, elements of I,Th, , or 0 group other than F can be used with the same effects as described above. However, it is desirable that element lighter than As should be used because element heavier than
As is difficult to be restored its crystallinity in the process of annealing.
As is evident from the foregoing description, according to the present invention, an annealing is conducted after implanting elements electrically inactive against the conductive layer to the conductive layer. Accordingly, the carrier concentration distribution of the conductive layer can be made uniform and a conductive layer superior in the reproducibility between wafers can be produced.
Furthermore, in a case where an n type conductive layer is produced by conducting annealing after ion implanting n type or p type dopants into semi-insulative GaAs substrate, elements electrically inactive against GaAs are implanted into the semi-insulative GaAs substrate before implanting dopants, whereby influences of transitions of the semiinsulative GaAs substrate in the annealing process are reduced, the variation in carrier concentration of the conductive layer is smoothed, the electric conductivity of the conductive layer is made uniform and the carrier concentration profile can be made steep.
Claims (5)
1. A method of producing a compound semiconductor device comprising:
a first process of ion implanting elements (3)into a conductive layer (8), which elements (3) are electrically inactive against said conductive layer (8); and
a second process of executing annealing to said conductive layer (8).
2. A method of producing a compound semiconductor device comprising:
a first process of ion implanting elements (3) into a semi-insulative GaAs substrate (1) which elements (3) are electrically inactive against said semi-insulative GaAs substrate (1);
a second process of ion implanting n type or p type dopants (5) into said semi-insulative GaAs substrate (1); and
a third process of executing annealing to said GaAs substrate (1) so as to activate said dopants (5).
3. A method according to claim 1 or 2, wherein the element which is implanted into the conductive layer and is electrically inactive is fluorine.
4. A method of producing a semiconductor device substantially as hereinbefore described with reference to and as illustrated in Figure 1 or Figures 2(a) to 2(c) of the accompanying drawings.
5. A method of treating an epitaxial growth layer to reduce variations in carrier concentration which comprises treating the layer with an element which is electrically inactive against the conductive layer.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63047335A JPH01220822A (en) | 1988-02-29 | 1988-02-29 | Manufacture of compound semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8818768D0 GB8818768D0 (en) | 1988-09-07 |
| GB2215516A true GB2215516A (en) | 1989-09-20 |
| GB2215516B GB2215516B (en) | 1990-11-28 |
Family
ID=12772339
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8818768A Expired - Fee Related GB2215516B (en) | 1988-02-29 | 1988-08-08 | A method of producing a compound semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH01220822A (en) |
| FR (1) | FR2627901B1 (en) |
| GB (1) | GB2215516B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2244284A (en) * | 1990-05-02 | 1991-11-27 | Nippon Sheet Glass Co Ltd | A method of manufacturing a polycrystalline semiconductor film by ion implantation |
| US5141879A (en) * | 1989-08-28 | 1992-08-25 | Herbert Goronkin | Method of fabricating a FET having a high trap concentration interface layer |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8629013B2 (en) * | 2011-10-14 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Junction leakage reduction through implantation |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1238729A (en) * | 1967-09-11 | 1971-07-07 | ||
| GB1239044A (en) * | 1967-12-26 | 1971-07-14 | ||
| GB1269359A (en) * | 1968-08-22 | 1972-04-06 | Atomic Energy Authority Uk | Improvements in or relating to semiconductors and methods of doping semiconductors |
| GB1280199A (en) * | 1968-12-27 | 1972-07-05 | Hitachi Ltd | Method for producing semiconductor device utilizing ion implantation |
| US3914784A (en) * | 1973-12-10 | 1975-10-21 | Hughes Aircraft Co | Ion Implanted gallium arsenide semiconductor devices fabricated in semi-insulating gallium arsenide substrates |
| GB1456437A (en) * | 1973-01-31 | 1976-11-24 | Nippon Electric Co | Compound semiconductor layers |
| GB1484399A (en) * | 1976-05-04 | 1977-09-01 | Standard Telephones Cables Ltd | Method of annealing a body of iron-implanted semiconducto |
| GB1504017A (en) * | 1974-12-06 | 1978-03-15 | Hughes Aircraft Co | Field effect device |
| GB1536618A (en) * | 1976-12-06 | 1978-12-20 | Ibm | Semiconductor devices |
| US4383869A (en) * | 1981-06-15 | 1983-05-17 | Rca Corporation | Method for enhancing electron mobility in GaAs |
| EP0111085A2 (en) * | 1982-11-10 | 1984-06-20 | International Business Machines Corporation | Ion implantation process for compound semiconductor |
| US4545824A (en) * | 1981-11-26 | 1985-10-08 | Michel Salvi | Process for producing a GaAs or InP semiconductor by pre-implantation followed by transition metal diffusion |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2525028A1 (en) * | 1982-04-09 | 1983-10-14 | Chauffage Nouvelles Tech | PROCESS FOR PRODUCING FIELD EFFECT TRANSISTORS IN GAAS BY IONIC IMPLANTATIONS AND TRANSISTORS THUS OBTAINED |
| JPS6047428A (en) * | 1983-08-26 | 1985-03-14 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1988
- 1988-02-29 JP JP63047335A patent/JPH01220822A/en active Pending
- 1988-08-08 GB GB8818768A patent/GB2215516B/en not_active Expired - Fee Related
- 1988-12-20 FR FR8816835A patent/FR2627901B1/en not_active Expired - Fee Related
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1238729A (en) * | 1967-09-11 | 1971-07-07 | ||
| GB1239044A (en) * | 1967-12-26 | 1971-07-14 | ||
| GB1269359A (en) * | 1968-08-22 | 1972-04-06 | Atomic Energy Authority Uk | Improvements in or relating to semiconductors and methods of doping semiconductors |
| GB1280199A (en) * | 1968-12-27 | 1972-07-05 | Hitachi Ltd | Method for producing semiconductor device utilizing ion implantation |
| GB1456437A (en) * | 1973-01-31 | 1976-11-24 | Nippon Electric Co | Compound semiconductor layers |
| US3914784A (en) * | 1973-12-10 | 1975-10-21 | Hughes Aircraft Co | Ion Implanted gallium arsenide semiconductor devices fabricated in semi-insulating gallium arsenide substrates |
| GB1504017A (en) * | 1974-12-06 | 1978-03-15 | Hughes Aircraft Co | Field effect device |
| GB1484399A (en) * | 1976-05-04 | 1977-09-01 | Standard Telephones Cables Ltd | Method of annealing a body of iron-implanted semiconducto |
| GB1536618A (en) * | 1976-12-06 | 1978-12-20 | Ibm | Semiconductor devices |
| US4137103A (en) * | 1976-12-06 | 1979-01-30 | International Business Machines Corporation | Silicon integrated circuit region containing implanted arsenic and germanium |
| US4383869A (en) * | 1981-06-15 | 1983-05-17 | Rca Corporation | Method for enhancing electron mobility in GaAs |
| US4545824A (en) * | 1981-11-26 | 1985-10-08 | Michel Salvi | Process for producing a GaAs or InP semiconductor by pre-implantation followed by transition metal diffusion |
| EP0111085A2 (en) * | 1982-11-10 | 1984-06-20 | International Business Machines Corporation | Ion implantation process for compound semiconductor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5141879A (en) * | 1989-08-28 | 1992-08-25 | Herbert Goronkin | Method of fabricating a FET having a high trap concentration interface layer |
| GB2244284A (en) * | 1990-05-02 | 1991-11-27 | Nippon Sheet Glass Co Ltd | A method of manufacturing a polycrystalline semiconductor film by ion implantation |
| GB2244284B (en) * | 1990-05-02 | 1993-11-03 | Nippon Sheet Glass Co Ltd | A method of manufacturing a polycrystalline semiconductor film |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8818768D0 (en) | 1988-09-07 |
| JPH01220822A (en) | 1989-09-04 |
| FR2627901A1 (en) | 1989-09-01 |
| FR2627901B1 (en) | 1994-04-29 |
| GB2215516B (en) | 1990-11-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 746 | Register noted 'licences of right' (sect. 46/1977) |
Effective date: 19950809 |
|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19990808 |