GB2202094A - Multilayer printed circuit board - Google Patents
Multilayer printed circuit board Download PDFInfo
- Publication number
- GB2202094A GB2202094A GB08801471A GB8801471A GB2202094A GB 2202094 A GB2202094 A GB 2202094A GB 08801471 A GB08801471 A GB 08801471A GB 8801471 A GB8801471 A GB 8801471A GB 2202094 A GB2202094 A GB 2202094A
- Authority
- GB
- United Kingdom
- Prior art keywords
- circuit board
- holes
- printed circuit
- laminate
- multilayer printed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09436—Pads or lands on permanent coating which covers the other conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/061—Lamination of previously made multilayered subassemblies
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
A multilayer printed circuit board for the soldered attachment of surface mounted components 10 is disclosed. Connection lands 8 for the surface mounted components are connected directly by resin filled via holes to conductive tracks 5a within the board thereby eliminating surface track connections to the lands. This form of construction removes the need to use solder resist to prevent unwanted flow of solder along the surface tracks during soldering and thereby eliminates risk of contamination of the lands by the solder resist. <IMAGE>
Description
MULTILAYER PRINTED CIRCUIT BOARD
The present invention relates to a method of manufacturing a multilayer printed circuit board and in particular to the successful formation of solder joints for attaching surface mounted components to the circuit board.
It is necessary in a multilayer circuit board designed to accept surface mounted components to be able to provide connections between conductive surface lands, to which the terminals of surface mounted components are soldered, and conductive tracks or voltage planes at different layers within the circuit board. In order to accomplish this, conductive tracks are provided on the surface of the board connecting the conductive lands to plated via holes which in turn connect with the internal conductive tracks. It is also necessary to provide conductive surface tracks interconnecting some of the surface lands.
A problem which arises when the soldered joints are made is that solder cream, used when forming the joints, flows along the surface tracks and through the via holes to protrude from the other side of the board.
In order to prevent this, it has previously been proposed to form a barrier to the solder cream by applying a layer of solder #esist material across the surface tracks.
Due, however, to the smaller dimensions of the surface tracks and conductive lands and to the small intertrack spacing, it has been found difficult to prevent the solder resist material from coming into contact with the lands. Any such contact of the solder resist material results in the material contaminating the land by leaching into its tin/lead surface. This contamination is detrimental to the formation of good soldered joints. Although various forms of solder r-esist for example, liquid and dry film resists, have been tried the contamination problem is always present either from the resist material itself or from adhesive promoters contained in the resist material.
It will be realised that the solder joint reliability in surface mount applications is of utmost importance as the joint serves both as an electrical connection and as the means by which the component is mechanically attached to the circuit board.
Elimination of the solder resist material from the process would ensure that contamination could not occur. The object of the present invention is, therefore, to provide a multilayer printed circuit board and a method of making the same which is arranged to enable surface mounted components to be attached without the use of solder resist material.
According to the invention, a method of manufacturing a multilayer printed circuit board includes the steps of: (a) providing a laminate comprising an insulating layer sandwiched between conductive layers on first and second opposite faces (b) forming holes through the laminate at predetermined positions and plating through the holes so as to form electrical connections between the conductive layers; (c) forming a pattern of conductors on said first face by selectively removing portions of the conductive layer on said first face; (d) forming an assembly comprising further conductive layers of the circuit board; (e) bonding the first face of the laminate to the assembly under pressure; and (f) selectively removing portions of the conductive layer from the second surface to form conductive surface lands connected by the plated through holes to the conductors on the first face.
Preferably the steps (a) to (f) are carried out in the order set out in the above paragraph. However, it will be realised that this order need not be adhered to in carrying out the method.
A method of manufacturing a multilayer printed circuit board in accordance with the invention will now be described, by way of example, with reference to the accompanying drawing in which:
Figures 1-3 show three stages in the manufacture of outer layers of the printed circuit board, and
Figures 4-7 show the outer layers bonded to other layers and the subsequent steps in the manufacture.
Referring to the drawings, Figure 1 shows part of a double sided laminate 1 from which the outer layers are formed. The laminate comprises an insulating layer 2, 127 microns in thickness, sandwiched between a pair of copper layers 3 and 3a.
Figure 2 shows the laminate 1 with a hole 4, 152 microns in diameter, formed therethrough by for example, drilling. Although only one hole 4 is shown it will be understood that a number of such holes are formed, one for each of the required surface mount connections lands. Each of the holes 4 is positioned so as to correspond with the centre of one of the required connection lands.
The next stage of the process, as illustrated by Figure 3, is to apply a further layer 5, 5a of copper extending over the copper layers 3, 3a and through the hole 4. This layer is preferably applied in two stages, a first layer which is deposited electrolessly followed by a second layer which is electroplated on to the first layer. This operation results in a copper layer 20 microns thick on the walls of the holes 4 thereby forming via holes.
Conductive tracks (not shown) are now formed in the copper layer 5a by conventional etch techniques.
Some of these tracks connect with the plated via holes 4 and others interconnect the holes 4.
Figure 4 shows the processed laminate 1 bonded to an assembly 6 which comprises the remainder or inner layers of the printed circuit board. The bonding process is carried out in an autoclave device using a conventional pre-preg material. In this device the laminate 1 and the assembly 6 are placed on a base plate and within a bag formed by a flexible membrane attached to the base plate. The base plate, together with the circuit board and bag, is enclosed in a chamber in which the pressure can be raised to 9/12 barr by the introduction of an inert gas. In operation the bag is evacuated to remove all air and both the temperature and the pressure is raised within the chamber to accomplish the bonding. Bonding by this method ensures an even pressure on all sides of the circuit board which is effective to prevent excess resin from being forced out at the edges.
The pressure causes the resin from the pre-preg material 7 to be forced into the plated holes 4, filling the holes and bleeding through to the copper layer 5.
Any resin which has bled through to the surface of layer 5 is removed by, for example, brush abrading and sulphuric dipping. When this has been accomplished the plated holes 4 remain filled with columns of resin which end flush with the surface of the copper layer 5 of the laminate 1 as illustrated in Figure 5.
Further holes (not shown) of diameter 250 microns which are required to establish connections from the tracks formed in the layer 5a to inner tracks are now drilled and plated. The outer layer of copper 5 is plated using conventional copper and tin/lead techniques and etched to form the surface lands 8 and any other conductive tracks which may be required on the surface.
Each of the surface lands 8 is positioned over a plated-through hole 4 so that the holes 4 are in the centre of the lands 8. Due to the small diameter of the holes 4, the deposited copper layer on the lands 8 has sufficient adhesion and mechanical strength to stand up to the final solder reflow process in which terminals 9 of the surface mounted components 10 are soldered to the lands 8.
It will be realised that all tracks connecting the surface lands to via holes and those interconnecting surface lands have been removed from the surface of the circuit in the described structure. Thus, the necessity to use any form of solder resist material has been removed together with the resulting contamination of the surface lands.
Although the described bonding operation employs an autoclave device it will be realised that other methods of bonding which apply both pressure and heat may be employed.
Claims (7)
1. A method of manufacturing a multilayer printed circuit board including the steps of: (a) providing a laminate comprising an insulating layer sandwiched between conductive layers on first and second opposite faces; (b) forming holes through the laminate at predetermined positions and plating through the holes so as to form electrical connections between the conductive layers; (c) forming a pattern of conductors on said first face by selectively removing portions of the conductive layer on said first facet (d) forming an assembly comprising further conductive layers of the circuit board; (e) bonding the first face of the laminate to the assembly under pressure; and (f) selectively removing portions of the conductive layer from the second surface to form conductive surface lands connected by the plated through holes to the conductors on the first face.
2. A method as claimed in claim 1, in which, during the bonding step (e), some of the bonding material is forced through the plated holes and including the further step of removing any surplus bonding material from said second face.
3. A method as claimed in claim 1 or 2, including the step of forming holes extending through all layers of the circuit board and plating through the holes so as to provide selective interconnections between the pattern of conductors on said first face and said further conductive layers.
4. A method as claimed in any of claims 1 to 3, including the step of forming a tin/lead layer over the conductive layer of the second surface prior to the final step (f).
5. A method as claimed in any preceding claim, in which the bonding step (e) is carried out in a vacuum and the pressure is applied by enclosing the laminate and the assembly in a pressurised chamber.
6. A method of manufacturing a multilayer printed circuit board as herein described with reference to the accompanying drawing.
7. A multilayer printed circuit board manufactured by a method according to any preceding claim.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB878705543A GB8705543D0 (en) | 1987-03-10 | 1987-03-10 | Printed circuit board |
Publications (3)
Publication Number | Publication Date |
---|---|
GB8801471D0 GB8801471D0 (en) | 1988-02-24 |
GB2202094A true GB2202094A (en) | 1988-09-14 |
GB2202094B GB2202094B (en) | 1990-09-26 |
Family
ID=10613617
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB878705543A Pending GB8705543D0 (en) | 1987-03-10 | 1987-03-10 | Printed circuit board |
GB8801471A Expired - Fee Related GB2202094B (en) | 1987-03-10 | 1988-01-22 | Multilayer printed circuit board |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB878705543A Pending GB8705543D0 (en) | 1987-03-10 | 1987-03-10 | Printed circuit board |
Country Status (1)
Country | Link |
---|---|
GB (2) | GB8705543D0 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0379686A2 (en) * | 1989-01-27 | 1990-08-01 | Nippon Cmk Corporation Limited | Printed circuit board |
EP0424262A1 (en) * | 1989-10-20 | 1991-04-24 | STMicroelectronics S.A. | Portable electronics with connectable components |
US5523920A (en) * | 1994-01-03 | 1996-06-04 | Motorola, Inc. | Printed circuit board comprising elevated bond pads |
GB2307351A (en) * | 1995-11-16 | 1997-05-21 | Marconi Gec Ltd | Printed circuit boards and their manufacture |
EP1209957A2 (en) * | 2000-11-27 | 2002-05-29 | Fujitsu Ten Limited | Substrate structure |
EP2079292A3 (en) * | 2000-12-14 | 2009-10-28 | Denso Corporation | Manufacturing method of multilayer substrate and multilayer substrate produced by the manufacturing method |
WO2018073128A1 (en) * | 2016-10-18 | 2018-04-26 | HELLA GmbH & Co. KGaA | Circuit board |
-
1987
- 1987-03-10 GB GB878705543A patent/GB8705543D0/en active Pending
-
1988
- 1988-01-22 GB GB8801471A patent/GB2202094B/en not_active Expired - Fee Related
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0379686A2 (en) * | 1989-01-27 | 1990-08-01 | Nippon Cmk Corporation Limited | Printed circuit board |
EP0379686A3 (en) * | 1989-01-27 | 1990-09-12 | Nippon Cmk Kk | Printed circuit board |
EP0424262A1 (en) * | 1989-10-20 | 1991-04-24 | STMicroelectronics S.A. | Portable electronics with connectable components |
FR2653601A1 (en) * | 1989-10-20 | 1991-04-26 | Sgs Thomson Microelectronics | PORTABLE ELECTRONICS CONNECTABLE TO CHIPS. |
US5311396A (en) * | 1989-10-20 | 1994-05-10 | Sgs-Thomson Microelectronics, S.A. | Smart card chip-based electronic circuit |
US5523920A (en) * | 1994-01-03 | 1996-06-04 | Motorola, Inc. | Printed circuit board comprising elevated bond pads |
GB2307351A (en) * | 1995-11-16 | 1997-05-21 | Marconi Gec Ltd | Printed circuit boards and their manufacture |
EP1209957A2 (en) * | 2000-11-27 | 2002-05-29 | Fujitsu Ten Limited | Substrate structure |
EP1209957A3 (en) * | 2000-11-27 | 2003-07-23 | Fujitsu Ten Limited | Substrate structure |
US6750537B2 (en) | 2000-11-27 | 2004-06-15 | Fujitsu Ten Limited | Substrate structure |
EP2079292A3 (en) * | 2000-12-14 | 2009-10-28 | Denso Corporation | Manufacturing method of multilayer substrate and multilayer substrate produced by the manufacturing method |
WO2018073128A1 (en) * | 2016-10-18 | 2018-04-26 | HELLA GmbH & Co. KGaA | Circuit board |
CN109792847A (en) * | 2016-10-18 | 2019-05-21 | 黑拉有限责任两合公司 | Circuit board |
CN109792847B (en) * | 2016-10-18 | 2022-09-20 | 黑拉有限责任两合公司 | Circuit board |
US11452214B2 (en) | 2016-10-18 | 2022-09-20 | HELLA GmbH & Co. KGaA | Printed circuit board |
Also Published As
Publication number | Publication date |
---|---|
GB2202094B (en) | 1990-09-26 |
GB8705543D0 (en) | 1987-04-15 |
GB8801471D0 (en) | 1988-02-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20040122 |