GB2196518A - Protocol adaptor - Google Patents

Abstract

Telegraph adaptor apparatus enables synchronous data processing equipment, such as data encryption equipment, to be used with equipment producing asynchronous telegraph formation characters. The apparatus comprises a first unit 16 which converts the telegraph formatted characters into synchronous format and vice versa, and a second unit (18 Fig. 2) for converting the output from the data processing equipment into telegraph format for transmission down a line, and vice versa. The first unit 16 includes a UART 26 and the second unit (18) includes a microprocessor (20) and a USART (44). A fibre optic link 22 interconnects the first and second units (16, 18), enabling the microprocessor (20) to control the UART 26 as well as the USART (44). <IMAGE>

Description

SPECIFICATION Protocol adaptor Field of the invention This invention relates to protocol adaptor apparatus, for example telegraph adaptor apparatus to enable synchronous data processing equipment to be used with equipment producing asynchronous telegraph formatted characters.

Background to the invention Known telegraph adaptor apparatus converts asynchronous telegraph formatted characters into a synchronous or clocked form for supply to synchronous data processing equipment, such as data encryption equipment. The synchronous data forming the output of the synchronous data processing equipment is then typically transmitted over a line, to a similar equipment at the distant end. The invention aims to provide protocol adaptor apparatus which produces an output suitable for passing via communication networks which require the traffic to be in an asynchronous form.

Summary of the invention According to one aspect of the invention telegraph adaptor apparatus to enable synchronous data processing equipment to be used with equipment producing asynchronous telegraph formatted characters, comprises a first unit for converting the telegraph formatted characters into synchronous format for processing by the data processing equipment, and vice versa, a second unit for converting the output from the data processing equipment into telegraph format for transmission down a line, and vice versa, and linking means interconnecting the first and second units to effect control of both units. The second unit therefore provides an output which is asynchronous in nature, enabling the traffic to be passed via communications networks which will only accept asynchronous formats.

The linking means preferably comprise a fibre optic link, and ip the preferred embodiment the second unit includes a microprocessor which, through the fibre optic link, controls the first unit.

The data processing equipment is preferably data encryption equipment, the output of which is an encrypted or cipher version of the plain text input.

The first unit may include a universal asynchronous receiver/transmitter (UART) which is controlled by the microprocessor of the second unit and which transforms the asynchronous telegraph formatted signals to parallel format for supply to a parallel to serial shift register. The second unit may include a universal synchronous/ asynchronous receiver/transmitter (USART) for converting the synchronous output of the data processing equipment into asynchronous form for transmission down the line, and vice versa, the USART being controlled by the microprocessor.

Protocol adaptor apparatus according to the invention may be used for more general conversion from one format to another and is not limited to asynchronous/synchronous conversion.

Hence according to another aspect of the invention protocol adaptor apparatus to enable data processing equipment handling signals of a first format to be used with equipment handling signals of a second format, comprises a first unit for converting the signals of the second format into signals of the first format for processing by the data processing equipment, and vice versa, a second unit for converting the signals of the first format into signals of the second format for transmission down a line, and vice versa, and linking means interconnecting the first and second units to effect control of both units.

Telegraph adaptor apparatus according to the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a perspective view of the apparatus, and Figure 2, consisting of Figures 2a and 2b, is a block circuit diagram of the telegraph adaptor apparatus in conjunction with encryption equipment.

Detailed description of the drawings Referring to Figure 1, the telegraph adaptor comprises two die-cast boxes 10, 12 designed to fit side by side in a 19" rack using a special mounting shelf. One box 10 is connected to data encryption equipment (the crypto, 14 Figure 2) and the line terminating equipment and is called the terminal unit 16.

The other box 12 is connected to the line and the crypto 14 and is known as the line unit 18.

The terminal unit 16 contains retiming logic for the conversion of asynchronous signals from the terminal 24 into synchronous signals acceptable to the crypto 14 and vice versa.

The terminal unit 16 is controlled from the line unit 18 which contains a microprocessor 20 (Figure 2b) for this purpose. Communication of control signals between the two units 16, 18 is via a fibre optic link 22.

The units 16, 18 are individually powered from mains and security protection (TEMPEST) to current UK standards is provided on both uriits, even though only the terminal unit 16 handles the plain text (RED signals). This enables the line unit 18 to be used in RED areas with a minimum of installation problems.

The line unit 18 as well as performing the conversion of asynchronous signals from the line to synchronous format for the crypto 14, also generates clock signals for the crypto 14, and controls the transmission and receipt of cryptographic synchronisation sequences for a variety of operating modes and formats at speeds up to 9600 bits/sec. It is also capable of literalisation and deliteralisation for the preparation and decryption of off-line messages.

Both units 16, 18 are designed to interoperate using pulse release signals and the line unit will accept a release puise or level from equipment on the line side, whilst the terminal unit will provide an enabling signal to the terminal to control its output of characters. A buffer store which can be configured to hold between a minimum 2 and maximum 2000 characters is also provided internal to the line unit to accommodate momentary delays in traffic.

With reference to Figure 2a, the terminal unit 16 incorporates only one printed wiring board involving active logic. The major function of this unit 16 is to receive telegraph formatted signals from the terminal 24 and to convert them to parallel format in a UART 26 and then feed them to a parallel in-serial out shift register 28 ready for the resulting synchronous signals to be shifted through the crypto 14, under the control of the microprocessor 20 in the line unit 18.

In the opposite direction, the line unit 18 shifts data through the crypto 14 into a serial in-parallel out shift register 30 from where it is serialised in the UART 26 into a standard telegraph character format, and transmitted to the terminal 24. The UART 26 is a standard 6402 UART pack operating in conjunction with CMOS shift registers 28, 30. Logic is provided to select the length of these shift registers appropriate to the particular format chosen by the user.

The UART 26 is provided with clocks (16 times the required baud rate) from a standard 4702 baud rate generator chip 32 operating from a 2.4576 MHz crystal oscillator. The associated logic is to provide 100 baud operation as this speed is not generated by the chip. Speed selection is by means of direct inline switches 34, a bank of four of these allowing selection of any of the 14 speeds provided by the unit.

A number of other switches 36 are provided so that the user can choose an appropriate character length and format, as well as whether a parity bit is to be used, and whether it is to be odd or even.

In TFS (traffic flow security) operation, allspace characters are detected by means of gating (indicated at 38) operating on the paral lel signal going into the UART 26. If TFS working is selected, the character is prevented from being transmitted to the terminal 24.

All the control signals relating to the UART 26 are sent or received via the fibre optic link 22. This link consists of a duplex 8 channel link using a programmable logic device to perform the mux/demux and coding function. The signals sent over the link consist of the following.

1) Terminal to line a) Data received (DR). Informs the line unit 18 that the terminal unit 16 has received a character from the terminal 24.

b) Test signal (DDR). This is simply one of the signals from the line unit routed back via another channel. It is used by the line unit to verify the presence of the terminal unit during power up and initialisation phases.

c) 5 by-pass channels for miscellaneous control.

2) Line to terminal a) Data received reset (DDR). Used to load data from the UART into the shift register and to reset the UART ready for another character.

b) Transmit buffer register load (TBRL).

Loads a character into the UART from the shift register to be placed out to the terminal.

c) Pulse release signal. If the data from the terminal has to be controlled, this signal can be used to stop and start the flow.

d) 5 by-pass channels for miscellaneous control.

The line unit 18 consists of two active boards, the micro board 18a and the line board 18b. The micro board 1 8a contains the microprocessor 20, and its associated memory comprising 8K PROM 40 and 2K RAM 42, as well as USART 44 and programmable peripheral interface (PPI) 46.

The USART 44 on the micro board is used to communicate with the line terminating equipment 48, whilst the PPI 46 is used to communicate with the terminal unit 16 via the fibre optic link 22 and also to interface with the signals to and from the crypto 14.

The microprocessor bus lines extend into the line board 1 8b and connect into a second PPI chip 50. This is used to communicate with the front panel controls (shown in Figure 1) and also to interface with dil switches 52 by which the user can choose an appropriate format for transmission to line.

The PPI 50 also interfaces with a section of logic 54 concerned with the generation of transmit and receive timebase signals. This logic is clocked by 2.4576 MHz from a baud rate generator 56 and produces two signals, the transmit timebase, and the receive timebase.

The transmit timebase is used to time the transmission of characters to line, and occurs at intervals of one character period. This enables the machine to transmit in accurately defined timeslots.

The receive timebase also occurs at intervals of one character period, and is used to advance the decryption process during intervals of no traffic. In this way, two machines can be held in synchronism in the absence of traffic.

The receive timebase differs from the transmit timebase, however, in that it is adjusted to line up with received traffic if and when it occurs. Thus, in the case of intermittent bursts of traffic, the receive timebase will be constantly corrected so that it is optimally aligned in the event of a break.

The baud rate generator 56 is virtually identical to the generator 32 in the terminal unit 16.

The fibre optic link 22 consists of two identical systems operating in opposite directions, each providing eight information channels.

The multiplexing and demultiplexing is performed in a programmable logic device, which also Manchester encodes the resulting stream to remove any DC component which may be present. This makes the design of the optical system, particularly the receive amplifier, much easier.

The fibre optic system from the terminal unit 16 to the line unit 18 comprises a Manchester encoder/multiplexer 58 which receives control signals from the UART 26 and which supplies an optical transmitter 60 feeding a fibre optic cable. At the other end of the fibre optic link 22, the optical signals are received by an optical receiver 62 and then fed to a demultiplexer/Manchester decoder 64 which feeds the reconstituted control signals to the PPI 46.

In the reverse direction, control signals pass from the PPI 46 to a Manchester encoder/multiplexer 66, an optical transmitter 68, through the fibre optic link 22, to an optical receiver 70, a demultiplexer Manchester decoder 72 and thence to the UART 26.

The transmitter 60, 68 is an infra red light emitting diode, and the fibre cable is low grade multimode polymer fibre, having an attenuation of 200dB per kilometre at the wavelength used. The receiver 62, 70 is a pin diode and is followed by a FET input wideband amplifier and a comparator from which comes the received Manchester encoded stream.

The mux/demux chip operates directly from 2.4576MHz as provided from the baud rate chip. This is internally divided, and results in a composite bit rate of 307,200 bits/sec over the link. Framing bits- are included in this, so the final sample rate for each of the eight channels is slightly over 19.2k sample/second.

As previously mentioned, protocol adaptor apparatus according to the invention may be used for more general conversion from one signal format to another, four examples being: (i) Format conversion The terminal unit might be capable only of operating in 5-bit code, whereas the line unit might require ASCII to be used. The protocol adaptor could be used to perform this conversion using an internal software controlled buffer to accommodate timing differences. The described hardware would do this with no change. Appropriate software would be required.

(ii) Speed conversion In the same way, the baud rates of the terminal unit and the line unit could be different. Once again, the same hardware could be used to perform a conversion, but different software would be required.

(iii) Packet switching Where the data in has a header portion (identifying destination of the message and possibly origin also) and a text portion, it is necessary to separate the header to ensure that this is not encrypted with the text. If a suitable terminal unit were provided, the line unit could be used to provide packet assembly and disassembly (PAD) facilities. The terminal unit would need to transmit address information to the line unit via the optical cables.

Appropriate software would be required and the terminal unit would be different also. The line unit would not require changes to the hardware.

(iv) Error protection In the case of a high error rate link such as VHF radio, it would be possible for the line unit to ensure reliable cryptographic synchronisation by the use of error detection and protection applied to the synchronisation preamble.

This is important, as a high error rate link can be useable by non-encrypted traffic, but cannot be used for secure communication because it is impossible to achieve cryptographic synchronisation.

Claims (8)

1. Telegraph adaptor apparatus to enable synchronous data processing equipment to be used with equipment producing asynchronous telegraph formatted characters, the apparatus comprising a first unit for converting the telegraph formatted characters into synchronous format for processing by the data processing equipment, and vice versa, a second unit for converting the output from the data processing equipment into telegraph format for transmission down a line, and vice versa and linking means interconnecting the first and second units to effect control of both units.

2. Telegraph adaptor apparatus according to claim 1, wherein the linking means comprise a fibre optic link.

3. Telegraph adaptor apparatus according to claim 2, wherein the second unit includes a microprocessor which, through the fibre optic link, controls the first unit.

4. Telegraph adaptor apparatus according to any of the preceding claims, wherein the data processing equipment is data encryption equipment, the output of which is an encrypted or cipher version of the plain text in put.

5. Telegraph adaptor apparatus according to claim 2, wherein the first unit includes a universal asynchronous receiver/transmitter (UART) which is controlled by the microprocessor of the second unit and which transforms the asynchronous telegraph formatted signals to parallel format for supply to a parallel to serial shift register.

6. Telegraph adaptor apparatus according to claim 5, wherein the second unit includes a universal synchronous/ asynchronous receiver/transmitter (USART) for converting the synchronous output of the data processing equipment into asynchronous form for transmission down the line, and vice versa, the USART being controlled by the microprocessor.

7. Protocol adaptor apparatus to enable data processing equipment handling signals of a first format to be used with equipment handling signals of a second format, comprising a first unit for converting the signals of the second format into signals of the first format for processing by the data processing equipment, and vice versa, a second unit for converting the signals of the first format into signals of the second format for transmission down a line, and vice versa, and linking means interconnecting the first and second units to effect control of both units.

8. Telegraph adaptor apparatus constructed and arranged substantially as herein particularly described with reference to the accomanying drawings.