JPS62286332A - Digital signal branching and inserting equipment - Google Patents

Abstract

PURPOSE:To ensure a taking by detecting fault information in a received PCM multiplex signal and using said information so as to allow the clock of an oscillator to operate a transmitting side timing pulse generating circuit, thereby sending a synchonizing pattern and channel information in a transmitting PCM multiplex signal even if an error takes place in the received PCM multiplex signal. CONSTITUTION:A reception branch panel 2 detects a clock and frame synchronizinging information from the received PCM multiplex signal to supply a received side timing pulse synthesized by a reception side timing pulse generating circuit 4 to an insertion transmitting panel 7. If intermittent or consecutive synchronizing step-out takes place due to an error generated in the received PCM multiplex signal and the stop or mistransmission of the reception side timing pulse takes place thereby, a switching circuit 9 of the insertion transmitting panel 7 is operated via a controller 26 by an error detection circuit 5 detecting the synchronizing step-out or the intermission of the received PCM multiplx signal, a transmitting side timing pulse generating circuit 10 is subjected to self-running by using the clock of an oscillator 8 to activate the synchronizing pattern and a channel information insertion circuit 11.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a call protection means for a digital signal drop/add device that adds/drops call path information to a digital transmission path.

〔overview〕

The present invention is a digital signal add/drop multiplexer inserted into a transmission path, and if there is an abnormality in the timing pulse of the incoming PCM multiplex signal, the timing pulse of the PCM multiplex signal to be sent is generated using the clock signal from the built-in free-running oscillator. By doing so, even if a failure occurs in the received PCM multiplex signal, insertion call information can be sent normally.

[Conventional technology]

The configuration of a conventional digital add/drop multiplexer is shown in FIG. This device includes a receiving branching board 13 for branching information on the communication base 12 from a received PCM multiplex signal, and an inserting and transmitting board 1 for inserting information on the communication base 12 into a transmitting PCM multiplex signal.
7, and is arranged at both ends or in the middle of the digital transmission line. In this device, the transmitting side timing pulse generating circuit 20 receives the clock and receiving side timing signal from the receiving branch board 13 and operates in synchronization with the receiving side timing pulse generating circuit 15. As a result, when the digital add/drop multiplexer is placed in the middle of the digital transmission path, it is possible to insert and output information about the communication path board 12 that is synchronized with the received PCM multiplex signal.

Furthermore, when used at both ends of a digital transmission path, a PCM signal can be sent out using the clock from the oscillator 18.

[Problem that the invention seeks to solve]

When such a conventional digital add/drop multiplexer is used in the middle of a transmission line, intermittent or
When a received signal failure that causes continuous synchronization occurs, the synchronization extraction circuit 14 irregularly sends synchronization timing pulses to the reception side timing pulse generation circuit 15, so that the reception side supplied to the transmission side timing pulse generation circuit 20 Timing pulses are also sent out irregularly. As a result, the transmitting side timing pulse generating circuit 20 operates irregularly, making it impossible to normally output synchronization patterns and channel information.

That is, as shown in FIG. 3, in a digital transmission line in which a plurality of digital drop/drop/add devices are arranged, a failure occurring in the (N-1)th transmission line causes a failure in the Nth transmission line.
There is a drawback that communication on the Nth transmission path is not guaranteed.

The present invention eliminates such drawbacks, and the receiving PCM
It is an object of the present invention to provide a digital signal add/drop multiplexer capable of sending out insertion communication information despite a failure of multiplex signals.

[Means for solving problems]

The present invention is a method for inserting incoming PCM into a digital transmission path.
a first timing pulse generating means (4) that extracts a timing pulse of a multiplexed signal and generates a first clock signal in synchronization with the timing pulse; and a timing pulse of a PCM multiplexed signal that is sent out based on the given clock signal. Second timing pulse generation means (10
) and a free-running oscillator (8) that generates a second clock signal corresponding to the timing pulse of the PCM multiplex signal to be sent out.
and switching means (9) for supplying either the first clock signal or the second clock signal to the second timing pulse generating means, the digital signal add/drop device fault detection means (5) for detecting that the timing pulse of the multiplexed signal is abnormal; and based on the output of the fault detection means, the output of the oscillator is switched to the second timing pulse generation means using the switching means. The present invention is characterized in that it is provided with a control means (26) for giving.

[Effect]

When a failure in the received PCM multiplex signal is detected, the receiving side timing pulse and clock that are normally supplied to the transmitting side timing pulse generation circuit are switched to the self-running oscillator Kukotoku, and the insertion call information is transmitted normally. Send by timing pulse.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be explained based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Now, the reception branch board 2 detects clock and frame synchronization information from the received PCM multiplexed signal, and supplies the reception side timing pulse synthesized by the reception side timing pulse generation circuit 4 to the insertion and transmission board 7. During normal operation, the insert/output board 7 inserts and multiplexes received multiplexed signal information, synchronized synchronization patterns, and channel information.

Here, the features of the present invention are enclosed by broken lines in FIG.

By the way, if intermittent or continuous loss of synchronization occurs due to a failure in the received PCM multiplex signal, and this causes the receiving side timing pulse to stop or be sent incorrectly,
The fault detection circuit 5 that detects synchronization loss or disconnection of the received PCM multiplex signal operates the switching circuit 9 of the insertion/transmission board 7 via the controller 26, and the timing pulse generation circuit 10 on the transmission side runs by the clock of the oscillator 8. , the synchronization pattern and channel information insertion circuit 11 is operated.

However, if the phase of the free-running oscillator 8 is slightly shifted, the high-speed PC
Although it may not be possible to receive all M signals, signals such as low-speed monitoring signals and maintenance channels can be extracted.

〔Effect of the invention〕

As explained above, the present invention detects fault information in the received PCM multiplex signal and uses this information to operate the transmitting timing pulse generation circuit using the oscillator clock, so even if a fault occurs in the received PCM multiplex signal, This has the advantage that the synchronization pattern and communication path information can be sent to the transmitted PCM multiplex signal to ensure communication.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing the configuration of an apparatus according to an embodiment of the present invention. 2 is a block configuration diagram showing the configuration of a conventional device. FIG. 3 is an explanatory diagram showing the operation of a conventional device arranged on a digital transmission path. 1.12...Telephone road board, 2.13...Reception branch board,
3.14... Synchronization extraction circuit, 4.15... Receiving side timing pulse generation circuit, 5... Failure detection circuit, 6.
16... Clock extraction circuit, 7.17... Insertion transmitter board, 8.18... Oscillator, 9.19... Switching circuit,
10.20... Transmission side timing pulse generation circuit, 1
1.21...Synchronization pattern and channel information insertion circuit, 22.23.24.25...Digital add/drop device, 26...Controller.

Claims (1)

[Claims] (1) Extract the timing pulse of the incoming PCM multiplex signal that is inserted into the digital transmission path,
A first timing pulse generating means (4) that generates a first clock signal in synchronization with this timing pulse, and a second timing pulse that generates a timing pulse of a PCM multiplex signal to be sent out based on the given clock signal. generating means (10); a free-running oscillator (8) for generating a second clock signal corresponding to the timing pulse of the PCM multiplexed signal to be sent; and either the first clock signal or the second clock signal. In the digital signal drop/drop/add device, the switching means (9) provides one of the timing pulses to the second timing pulse generation means, and the fault detection means (5) detects that the timing pulse of the incoming PCM multiplexed signal is abnormal. ), and control means (26) for applying the output of the oscillator to the second timing pulse generation means using the switching means based on the output of the fault detection means. Insertion device.