GB2186105B - Multifunction arithmetic logic unit circuits - Google Patents

Multifunction arithmetic logic unit circuits

Info

Publication number
GB2186105B
GB2186105B GB8701631A GB8701631A GB2186105B GB 2186105 B GB2186105 B GB 2186105B GB 8701631 A GB8701631 A GB 8701631A GB 8701631 A GB8701631 A GB 8701631A GB 2186105 B GB2186105 B GB 2186105B
Authority
GB
United Kingdom
Prior art keywords
logic unit
arithmetic logic
unit circuits
multifunction
multifunction arithmetic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB8701631A
Other languages
English (en)
Other versions
GB2186105A (en
GB8701631D0 (en
Inventor
Walter Robert Steiner
Paul Andrew Simoncic
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of GB8701631D0 publication Critical patent/GB8701631D0/en
Publication of GB2186105A publication Critical patent/GB2186105A/en
Application granted granted Critical
Publication of GB2186105B publication Critical patent/GB2186105B/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/003D [Three Dimensional] image rendering
    • G06T15/10Geometric effects
    • G06T15/40Hidden part removal
    • G06T15/405Hidden part removal using Z-buffer
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/14Conversion to or from non-weighted codes
    • H03M7/24Conversion to or from floating-point codes
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804Details
    • G06F2207/3808Details concerning the type of numbers or the way they are handled
    • G06F2207/3812Devices capable of handling different types of numbers
    • G06F2207/382Reconfigurable for different fixed word lengths
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804Details
    • G06F2207/386Special constructional features
    • G06F2207/3884Pipelining
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905Exception handling
    • G06F7/4991Overflow or underflow

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Computer Graphics (AREA)
  • Nonlinear Science (AREA)
  • Complex Calculations (AREA)
  • Image Generation (AREA)
GB8701631A 1986-01-30 1987-01-26 Multifunction arithmetic logic unit circuits Expired GB2186105B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/824,053 US4815021A (en) 1986-01-30 1986-01-30 Multifunction arithmetic logic unit circuit

Publications (3)

Publication Number Publication Date
GB8701631D0 GB8701631D0 (en) 1987-03-04
GB2186105A GB2186105A (en) 1987-08-05
GB2186105B true GB2186105B (en) 1989-10-25

Family

ID=25240489

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8701631A Expired GB2186105B (en) 1986-01-30 1987-01-26 Multifunction arithmetic logic unit circuits

Country Status (5)

Country Link
US (1) US4815021A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS62197823A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3701599A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
FR (1) FR2593620A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB2186105B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0776911B2 (ja) * 1988-03-23 1995-08-16 松下電器産業株式会社 浮動小数点演算装置
US5038309A (en) * 1989-09-15 1991-08-06 Sun Microsystems, Inc. Number conversion apparatus
DE3936334A1 (de) * 1989-10-30 1991-05-02 Siemens Ag Datentransfer-verfahren
JPH04290122A (ja) * 1991-03-19 1992-10-14 Fujitsu Ltd 数値表現変換装置
US5420815A (en) * 1991-10-29 1995-05-30 Advanced Micro Devices, Inc. Digital multiplication and accumulation system
EP0627682B1 (en) * 1993-06-04 1999-05-26 Sun Microsystems, Inc. Floating-point processor for a high performance three dimensional graphics accelerator
DE59408784D1 (de) * 1993-08-09 1999-11-04 Siemens Ag Signalverarbeitungseinrichtung
JP4072738B2 (ja) * 1997-08-21 2008-04-09 Smc株式会社 5ポート電磁弁ボディを利用した3ポート電磁弁
US7043511B1 (en) * 2002-08-30 2006-05-09 Lattice Semiconductor Corporation Performing conditional operations in a programmable logic device
US8667045B1 (en) * 2011-05-11 2014-03-04 Altera Corporation Generalized parallel counter structures in logic devices
US9043290B2 (en) 2013-01-14 2015-05-26 International Business Machines Corporation Rewriting relational expressions for different type systems
US9916130B2 (en) 2014-11-03 2018-03-13 Arm Limited Apparatus and method for vector processing
GB2560766B (en) 2017-03-24 2019-04-03 Imagination Tech Ltd Floating point to fixed point conversion
US10673438B1 (en) * 2019-04-02 2020-06-02 Xilinx, Inc. Digital signal processing block
US20230061618A1 (en) * 2021-08-31 2023-03-02 Intel Corporation Bfloat16 square root and/or reciprocal square root instructions
US12379927B2 (en) 2021-08-31 2025-08-05 Intel Corporation BFLOAT16 scale and/or reduce instructions
US12229554B2 (en) 2021-08-31 2025-02-18 Intel Corporation BFLOAT16 fused multiply instructions

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4417314A (en) * 1981-07-14 1983-11-22 Rockwell International Corporation Parallel operating mode arithmetic logic unit apparatus

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3551665A (en) * 1966-09-13 1970-12-29 Ibm Floating point binary adder utilizing completely sequential hardware
US4037094A (en) * 1971-08-31 1977-07-19 Texas Instruments Incorporated Multi-functional arithmetic and logical unit
JPS5833572B2 (ja) * 1977-10-21 1983-07-20 株式会社東芝 情報処理方式
JPS5776634A (en) * 1980-10-31 1982-05-13 Hitachi Ltd Digital signal processor
JPS57196355A (en) * 1981-05-27 1982-12-02 Toshiba Corp Data processor
US4475237A (en) * 1981-11-27 1984-10-02 Tektronix, Inc. Programmable range recognizer for a logic analyzer
US4454589A (en) * 1982-03-12 1984-06-12 The Unite States of America as represented by the Secretary of the Air Force Programmable arithmetic logic unit
JPS59149539A (ja) * 1983-01-28 1984-08-27 Toshiba Corp 固定小数点−浮動小数点変換装置
US4524345A (en) * 1983-02-14 1985-06-18 Prime Computer, Inc. Serial comparison flag detector

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4417314A (en) * 1981-07-14 1983-11-22 Rockwell International Corporation Parallel operating mode arithmetic logic unit apparatus

Also Published As

Publication number Publication date
DE3701599A1 (de) 1987-08-06
JPS62197823A (ja) 1987-09-01
GB2186105A (en) 1987-08-05
GB8701631D0 (en) 1987-03-04
JPH0544686B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-07-07
FR2593620A1 (fr) 1987-07-31
DE3701599C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-01-16
US4815021A (en) 1989-03-21

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19930126