GB2173374A

GB2173374A - Scanning and preprocessing circuit for centrally controlled apparatuses, particularly for telephone exchanges

Info

Publication number: GB2173374A
Application number: GB08606337A
Authority: GB
Inventors: Maria Seefranz
Original assignee: BHG Hiradastechnikai Vallalat
Current assignee: BHG Hiradastechnikai Vallalat
Priority date: 1985-03-29
Filing date: 1986-03-14
Publication date: 1986-10-08
Also published as: GB8606337D0; SE8601425L; DE3609060A1; HUT39920A; HU193325B; SE8601425D0

Abstract

The scanning apparatus is suitable for the scanning and preprocessing of data in single-bit and multi-bit form and includes an address generator 7, multi-bit address summator 3, data selector 8, sampling circuit 6, state and/or change in state storage unit 9, comparison and evaluating circuit 10 and interface circuit 12. <IMAGE>

Description

SPECIFICATION Scanning and preprocessing circuit for centrally controlled apparatuses, particularly for telephone exchanges The invention relates to scanning and preprocessing circuit for centrally controlled apparatuses, particularly for telephone exchanges.

In the apparatuses where the number of peripheries to be controlled is relatively high, scanning circuits are used, i.e. instead of the constant monitoring of the states of peripheries, the cyclic short time challenge method is used.

Two main groups of the scanning circuits are known: serial and parallel circuits. The serial scanning circuit challenges one state at a time during fixed interval, then another one during the next interval. The so-obtained informations transmitted to a common line form a single signal flow.

In case of parallel scanning several, generally 8 or 16 states are challenged at the same time, which are transmitted through 8 or 16 lines to the evaluating circuit. When realizing the two methods the difference in the number of lines and formation of the appropriate preprocessing circuit is significant in favour of the serial scanning. The serial scanning is preferred for single-bit informations and parallel scanning for multi-bit coded informations in spite of the mentioned disadvantages.

Single-bit and multi-bit informations occur in most of the apparatuses. For example in the subexchanges the informations arriving from the subscriber set are single-bit in case of dial, and multi-bit in case of key set. The former one would require the use of serial scanning, and the latter one parallel scanning.

The objective of the invention was to develop such scanning circuit which is suitable for scanning of multi-bit informations too, while the favourable properties of the serial scanning are retained. The invention was based on the recognition that during the production of multi-bit informations a major part of the circuits produces single-bit, so-called "valid code came about" information, thus for the circuit evaluating the change in state it is sufficient to examine this single-bit instead of the code. However the control needs the code, hence after establishing the change in state, the multi-bit information will be transmitted.

The invention relates to scanning and preprocessing circuit for centrally controlled apparatuses, particularly for telephone exchanges, provided with controlled scanning address generator, address decoder for the individual addressing of the monitored points, address summator compiling the individual address of multi-bit informations, information selector for selection between the incoming single and multi-bit informations, serial/parallel converter, data selector for selecting the information to be transmitted to the control unit, sampling circuit, storage unit containing the states and/or changes in state of the previous scanning cycle n > 2, comparison and evaluating circuit, interface circuit for transmitting information to the central control unit, and logical circuit that controls the operation within the unit.

A possible realization of the invention is shown in Fig. 1. The address generator 7 produces cyclically at fixed intervals the address of the monitored points of number k, and with the aid of address decoder 11 it addresses the points to be scanned independently of being single-bit or multi-bit points. The outputs numbered mck out of those of the address decoder 11 numbered which serve the addressing of the multi-bit information-are connected to the input of the address summator 3. This way if the address decoder 11 addresses multi-bit information, it activates the output of the address summator at the same time.The address summator 3 permits the transmission of the multi-bit information-out of the single-bit and multi-bit informations arriving at the input of the information selector 4-to the input of the serial/parallel converter 5. Output of the serial/parallel converter 5 is connected to the data selector 8. State of the addressed points to be scanned passes as single-bit information to the input of the sampling circuit 6. After sampling the signal is partly stored in the data and change in state storage unit 9, and partly it is transmitted to the comparison and evaluating circuit 10. The fact of the change in state can be established on the basis of the information content of the scanning cycle n > 2. Thereupon the comparison and evaluating circuit 10 transmits the result to the logical circuit 13.The logical circuit 13 stops the address generator 7 and transmits its instantaneous state through the data selector 8 and interface 12 to the control unit 2. As soon as the central control unit 2 receives the information, the logical circuit 13 permits again the operation of the scanning address generator 7 and transmits the information on the output of the serial/parallel converter 5 through the data selector 8 to the input of the interface circuit 12. This information is transmitted by the interface circuit 12 to the central control unit 2.

1. Scanning and preprocessing circuit for centrally controlled apparatuses, particularly for telephone exchanges, characterized in that it is suitable for receiving two independent, single bit and multi-bit serial informations, the scanning address generator (7) is connected to the data selector (8), address decoder (11) and to logical circuit (13); the address summator (3) to information selector (4); the information selector (4) is connected through the serial/parallel converter (5) to the data selector (8); in

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **.

SPECIFICATION Scanning and preprocessing circuit for centrally controlled apparatuses, particularly for telephone exchanges The invention relates to scanning and preprocessing circuit for centrally controlled apparatuses, particularly for telephone exchanges.

In the apparatuses where the number of peripheries to be controlled is relatively high, scanning circuits are used, i.e. instead of the constant monitoring of the states of peripheries, the cyclic short time challenge method is used.

Two main groups of the scanning circuits are known: serial and parallel circuits. The serial scanning circuit challenges one state at a time during fixed interval, then another one during the next interval. The so-obtained informations transmitted to a common line form a single signal flow.

In case of parallel scanning several, generally 8 or 16 states are challenged at the same time, which are transmitted through 8 or 16 lines to the evaluating circuit. When realizing the two methods the difference in the number of lines and formation of the appropriate preprocessing circuit is significant in favour of the serial scanning. The serial scanning is preferred for single-bit informations and parallel scanning for multi-bit coded informations in spite of the mentioned disadvantages.

Single-bit and multi-bit informations occur in most of the apparatuses. For example in the subexchanges the informations arriving from the subscriber set are single-bit in case of dial, and multi-bit in case of key set. The former one would require the use of serial scanning, and the latter one parallel scanning.

The objective of the invention was to develop such scanning circuit which is suitable for scanning of multi-bit informations too, while the favourable properties of the serial scanning are retained. The invention was based on the recognition that during the production of multi-bit informations a major part of the circuits produces single-bit, so-called "valid code came about" information, thus for the circuit evaluating the change in state it is sufficient to examine this single-bit instead of the code. However the control needs the code, hence after establishing the change in state, the multi-bit information will be transmitted.

The invention relates to scanning and preprocessing circuit for centrally controlled apparatuses, particularly for telephone exchanges, provided with controlled scanning address generator, address decoder for the individual addressing of the monitored points, address summator compiling the individual address of multi-bit informations, information selector for selection between the incoming single and multi-bit informations, serial/parallel converter, data selector for selecting the information to be transmitted to the control unit, sampling circuit, storage unit containing the states and/or changes in state of the previous scanning cycle n > 2, comparison and evaluating circuit, interface circuit for transmitting information to the central control unit, and logical circuit that controls the operation within the unit.

A possible realization of the invention is shown in Fig. 1. The address generator 7 produces cyclically at fixed intervals the address of the monitored points of number k, and with the aid of address decoder 11 it addresses the points to be scanned independently of being single-bit or multi-bit points. The outputs numbered mck out of those of the address decoder 11 numbered which serve the addressing of the multi-bit information-are connected to the input of the address summator 3. This way if the address decoder 11 addresses multi-bit information, it activates the output of the address summator at the same time.The address summator 3 permits the transmission of the multi-bit information-out of the single-bit and multi-bit informations arriving at the input of the information selector 4-to the input of the serial/parallel converter 5. Output of the serial/parallel converter 5 is connected to the data selector 8. State of the addressed points to be scanned passes as single-bit information to the input of the sampling circuit 6. After sampling the signal is partly stored in the data and change in state storage unit 9, and partly it is transmitted to the comparison and evaluating circuit 10. The fact of the change in state can be established on the basis of the information content of the scanning cycle n > 2. Thereupon the comparison and evaluating circuit 10 transmits the result to the logical circuit 13.The logical circuit 13 stops the address generator 7 and transmits its instantaneous state through the data selector 8 and interface 12 to the control unit 2. As soon as the central control unit 2 receives the information, the logical circuit 13 permits again the operation of the scanning address generator 7 and transmits the information on the output of the serial/parallel converter 5 through the data selector 8 to the input of the interface circuit 12. This information is transmitted by the interface circuit 12 to the central control unit 2.

1. Scanning and preprocessing circuit for centrally controlled apparatuses, particularly for telephone exchanges, characterized in that it is suitable for receiving two independent, single bit and multi-bit serial informations, the scanning address generator (7) is connected to the data selector (8), address decoder (11) and to logical circuit (13); the address summator (3) to information selector (4); the information selector (4) is connected through the serial/parallel converter (5) to the data selector (8); in put of the sampling circuit (6) is interconnected with the information selector (4); output of the sampling circuit (6) is connected to the state and change in state storage unit (9) and to the comparison and evaluating circuit (10); [the state and change in state storage unit (9) is connected to the comparison and evaluating circuit (10)] output of the comparison and evaluating circuit (10) is connected to the logical circuit (13); the logical circuit (13) to the data selector (8) and to the interface (12) as well as to the scanning address generator (7) on a separate line; the interface (12) is connected to the data selector (8) and to the output of the unit.