SU1397953A1 - Device for address control of message switching - Google Patents

Abstract

The invention relates to multichannel electrical signal transmission systems and is intended to programmatically control the transmission rate of message flows on each of the channels. The aim of the invention is to increase the informational flexibility of the device. The device contains the sources of messages, the switch. the first and second decoders, the unit for determining the input effects, the block for selecting the transmission direction, the memory elements, the transmission rate control blocks, the OR elements, the transmission channels. A device for address control of message switching allows the device to expand its functionality, since A portion of the messages may be transmitted to the consumer without intermediate storage in memory cells. And the ability to control by command from an external device the setting of the transmission speed of information on each output channel increases the efficiency of channel use, and also uses this device as hardware to adapt the information communication network both in the design process and in the design process. functioning. 2 з.п, ф-л, 3 Il. (I

Description

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The invention relates to multichannel electrical signal transmission systems and is intended to programmatically control the transmission rate of message flows over each channel in information transmission networks.

The purpose of the invention is to increase information flexibility.

Figure 1 shows a block diagram of a device for address control of message switching; Figure 2 is a block diagram of an information rate control block; FIG. 3 is a block diagram of a block for selecting the direction and rate of transmission of the incoming message.

The block diagram of the device contains the sources, messages, switch 2 from n input channels either to m output channels or to memory elements, the second decoder 3 (states of message receivers), determining the presence of free message receivers at each current time point , block 4 for determining input effects, block 5 for selecting the direction of transmission of the incoming message to the memory elements or directly to the output channels and selecting its transmission rate, the first decoder 6 determining the state ( i.e., the filling of the memory elements, the rate control blocks, the elements OR 9i-9fn, the output transmission channels of messages.

The information rate control unit 8 (figure 2) contains a master oscillator 1I, a readout unit 12 for organizing the reading of information from the memory elements 7, a buffer register 13, and an amplifier-formagel 14 output signals.

Unit 5 (FIG. 3) contains an address driver 15, which determines the address of the receiver or memory element 7 and controls the unit 2. multiplexer 6, main memory unit 17, which stores operational information, and synchronization unit 18.

The device works as follows

Input information about the sources 1,, 1 J, ... , 1 enters the switch 2 and the input impacts definition block 4 and contains both the information part directly transmitted to the network subscriber and the address part, which indicates the origin and destination points of the messages, signs of the beginning and end of the transmission, instructions on the assignment or change of the message transmission speeds via communication channels, etc.

Block 4 of the address part of the incoming messages contains information indicating the addresses of the message receivers (the address part that does not contain the addresses of the receiver is translated for analysis into block 5). Based on information about the specified addresses of receivers and data on the presence of unfilled elements 7 ,, 7,. . . , 7 memory (information of the state decoder of the memory elements 7 and the synchronization unit 18) unit 4 either transmits to the shaper 15 the addresses of the number of the preferred transmission channels of the message or generates a failure signal to the source of the message

until the release of memory elements 7.

The address generator 15, based on the analysis of the information of the decoder 3, about the presence of free output channels 10, information of block 4 about preferred channels for transmitting messages and data for memory block 17 about current values of message transmission speeds on input and output channels, chooses a message or free channel as a receiver 10 with the transmission rate of messages that coincides with the transmission rate of the input channel, or in the absence of free receivers or a mismatch of transmission rates, memory element 7 ;.

The address chosen by the shaper 15 as a control action enters the switch 2, which sends the message either through the corresponding OR 9 element. Through channel 10, or to the memory element 7. The completion of the transmission of the message and its length are determined by the synchronization unit 18 on the basis of the end of the transmission in the address part of the message.

The imaging unit 15 transmits to the memory unit 17 the numbers of the elements 7 that store the received messages, and, at the command of the unit 18, the transfer of the message translates the unit 2 to the high-impedance state.

As channels 10 are ready (decoder information 3), synchronization block 18 according to memory block I7

determines the presence and length of messages stored in the corresponding element 7, and, initializing block 12, organizes the transmission of the message from element 7 through block 8 and element 9 to channel 10. The data on occupied and released elements 7 is transmitted by block 18 to block f.

The assignment or change of the transmission rates of messages on the output channels 10 is carried out as follows. From the part of messages arriving at block 5, multiplexer 16 selects those that contain instructions for assigning message transfer rates for each of sources 1 and channels 10. The received information is recorded in memory block 17 and is used further by block 15. Assigned rate transmitting the output channel 10 in the form of a control code enters generator 11 of block 8. Generator II sets the clock frequency of reading information from memory element 7 by block 12 and the clock frequency of transmitting information through the register 13 of reading.

Information from register I3 can

FDI, whose outputs are connected to the inputs of the corresponding transmission channels, whose information outputs are connected to the inputs of the second decoder, the output of which is connected to the first input of the direction and speed selection block, the first and second outputs of which are connected respectively to the second control input of the input actions and with the control input of the switch, the second group of outputs of which is connected to the corresponding inputs

5 memory elements, the first outputs of which are connected to the inputs of the first decoder, the second outputs are connected to the first inputs of the same rate control blocks, the second and third inputs of which are connected respectively to the third and fourth outputs of the direction selector and rate, the speed control blocks the transmissions are connected to the second inputs of the elements of the same name OR,

2. The device in accordance with claim 1, 1 and 2, and that is because the unit is selected

transmitted either in sequential, direction or transmission rate

or in parallel code. With the aid of amplifier 14, signals from register 13 are generated in amplitude and amplified in power.

Invention Formula

I, A device for address control of message switching, containing the sources of messages, the outputs of which are Q input of the direction selector and

connected to the same information inputs of the switch, the input effects determination unit, the memory element, the first decoder, the output of which is connected to the first control input of the input effects determination unit, and transmitting channels, in order to increase the information flexibility of the device, into it baud rate control blocks, OR elements, second decoder, direction and baud rate selector blocks, message source outputs are connected to the information inputs of the same name and determining the input block impacts, a first group of switch outputs coupled to the lane

the inputs of the elements of the same name

five

: Includes an address driver, a multiplexer, a memory unit, a synchronization unit, the first inputs of the address generator and a multiplexer are combined and are the first input of the direction and speed selection block, the first input of the synchronization unit and the second input of the address generator are combined and are the second

the transmission speeds, the first outputs of the address maker, the multiplexer and the synchronization unit are connected to the corresponding inputs of the main memory unit, the first input of which is connected to the second input of the synchronization unit, the second output of which is connected to the third input of the address maker, the second output of the main memory unit is connected with the second multiplexer input, the third clock of the synchronization unit is the first output of the direction selector and the transmission rate, the second output of the address generator is the second output m of the block for selecting the direction and speed of transmission; the second input of the multiplexer is the third output of the block for selecting the direction and speed

transmission, the fourth output of the synchronization unit is the fourth output of the direction selection and transmission rate unit.

3. The device according to claim 1, characterized in that the transmission rate control unit comprises a generator, a readout unit, a buffer register, a signal conditioner amplifier, the first read input is the first input of the transmission rate control unit, an input generator is the second input of the speed control unit ne

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the second input of the readout unit is the third input of the transmission rate control unit; the first output of the master oscillator is connected to the third input of the readout unit, the output of which is connected to the first input of the buffer register, the second input of which is connected to the second output of the master oscillator; with the same inputs of the signal amplifier amplifier whose input is the output of the transmission rate control unit.

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Claims (4)

Claim 1. A device for addressable control of message switching, containing message sources, the outputs of which are connected to the same information inputs of the switch, an input impact detection unit, a memory element, a first decoder, the output of which is connected to the first control input of the input impact detection unit, and transmitting channels, characterized the fact that, in order to increase the information flexibility of the device, transmission speed control blocks, OR elements, a second decoder, a selection block are sent to it ia and transmission speeds, the outputs of the message sources are connected to the same information inputs of the input impact determination unit, the first group of outputs of the switch is connected to the first inputs of the same elements OR, the outputs of which are connected to the inputs of the corresponding transmitting channels, the information outputs of which are connected to the inputs of the second decoder, the output of which is connected to the first input of the block for selecting the direction and transmission speed, the first and second outputs of which are connected respectively to the second control input of the input impact detection unit and with the control input of the switch, the second group of outputs of which is connected to the corresponding inputs of memory elements, the first outputs of which are connected to the inputs of the first decoder ora, second inputs connected to first inputs of similar transmission rate control blocks, second and third inputs being connected respectively to third and fourth outputs select the direction and rate block, a control block outputs are connected to the transmission rate of the second inputs of like elements in OR. 2. The device according to claim 1, characterized in that the direction and transmission rate selection unit comprises an address generator, a multiplexer, a random access memory block, a synchronization unit, the first inputs of the address generator and the multiplexer are combined and are the first input of the direction and transmission rate selection unit, the first the input of the synchronization unit and the second input of the address generator are combined and are the second input of the block for selecting the direction and transmission speed, the first outputs of the address generator, multiplexer and synchronization block are connected are connected with the corresponding inputs of the RAM block, the first output of which is connected to the second input of the synchronization block, the second output of which is connected to the third input of the address generator, the second output of the RAM block is connected to the second input of the multiplexer, the third output of the synchronization block is the first output of the direction selection block and transmission speed, the second output of the address driver is the second output of the unit for selecting the direction and transmission speed, the second output of the multiplexer is the third output and eye direction when the transmission rate, the fourth sync block is output to fourth output selecting unit and the direction of the transmission rate. 3. The device according to π.1, characterized in that the transmission rate control unit comprises a master oscillator, a read unit, a buffer register, a signal conditioning amplifier, the first read input is the first input of the transmission speed control unit, the input of the master oscillator is the second the input of the transmission speed control unit 1, the second, the input of the reading unit is the third input of the transmission speed control unit, the first output of the master oscillator is connected to the third input of the reading unit, the output of which is connected nen with the first input of the buffer register, the second input of which is connected to the second output of the master oscillator, the outputs of the buffer register are connected to the same inputs of the amplifier-driver, the output of which is the output of the transmission speed control unit. FIG. 2 FIG. 3 Compiled by V. Krajushkin Editor E. Papp Tehred L. Serdyukova Corrector 0. Kravtsova Order 2602/49 Circulation 558 Subscription VNIIIPI of the USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushskaya nab., D. 4/5 Production and printing company, Uzhhorod, st. Project, 4