GB2171251A

GB2171251A - Thin films

Info

Publication number: GB2171251A
Application number: GB8602637A
Authority: GB
Inventors: Masahiro Kameda; Yojiro Kamei; Kenichi Kurihara
Original assignee: Ricoh Co Ltd
Current assignee: Ricoh Co Ltd
Priority date: 1984-08-25
Filing date: 1986-02-14
Publication date: 1986-08-20
Also published as: FR2569494A1; FR2569494B1; GB8520956D0; GB2171251B; GB2165692A; DE3530419A1; GB8602637D0; GB2165692B

Abstract

A method for forming an interconnection pattern of A1 on a structure, such as a semiconductor device, includes applying energy to the film, and wet or dry etching said energy-applied film to profile the film into a desired pattern, and heat treating the patterned film.

Description

1 GB 2 171 251 A 1

SPECIFICATION

Thin-films This invention relates to a method for forming a thin-film in a desired pattern, and particularly to a method for forming a multilayer interconnection pattern in a process for manufacturing LSIs, in particular MOSFETs.

In forming interconnections and leads in LSIs in accordance with the prior art, a thin-film of an electrically conductive material, such as A[ and AI-Si, is first formed by evaporation, sputtering, etc. and then after patterning, it is subjected to heat treat ment at the temperature ranging from 400'C to 500'C. However, it is known that ridges called whiskers or hillocks are formed at the surface during this heat treatment thereby destroying smoothness in the surface. Such whiskers and hillocks could cause disconnections in interconnection lines due to 85 electrom ig ration, and, in particular, they could cause an electrical short between a first lead layer and a second lead layer in a multilayer interconnection structure, thereby forming obstructions against realization of a multilayer interconnection structure. 90 Japanese Patent Laid-open Publication, No. 57 183053, etc. discloses a method for preventing the formation of whiskers in a main surface of Al by implanting impurities, such as P, As and Ar. In the publication, it is also described that production of 95 whiskers is a phenomenon peculiar to pure A] and no such phenomenon takes place for alloy materials, such as AI-Si. On the other hand, with respect to hillocks, a paper presented by T. J. Faith, in J. Appl.

Phys., Vol. 52, No.7, July 1981, includes a description 100 which indicates that ridges in the form of hillocks may be formed in the surface of pure Al. As described in the LSI DATA HANDBOOK, Science Forum Co., pp. 316 - 323, one approach to prevent the formation of such hillocks is to use an electrically 105 conductive material added with an impurity, such as Si, Cu and Mg; however, for A]- Si, for example, the effects are not sufficient, and, for AI-Si-Cu, there are problems including difficulty in etching, Cu residues and contamination inside of the sputtering device by 110 Cu. Another approach is to introduce 0, but this cannot be easily put into practice because of an increase in resistance and difficulty in controlling the introduction of 0.

Moreover, in forming interconnection patterns in LSIs, chemical wet etching has also been used to etch an Al pattern into a desired pattern. Although wet etching of A[ is simple, it can no longer be applied when a desired line width of Al becomes 3 microns or less. One of the reasons for this is the formation of hillocks. Thus, in forming a fine metal pattern, wet etching cannot be applied though it is easy to carry out.

It is therefore a primary object of the present invention to provide an improved method for forming a fine interconnection pattern.

Another object of the present invention is to provide a method for forming a multilayer interconnection pattern without producing a short between layers.

A further object of the present invention is to provide a method forforming a thin-film having a desired pattern on a structure, such as a semiconductor device.

A still further object of the present invention is to provide a method for forming an interconnection pattern high in accuracy and sharpness.

A still further object of the present invention is to prevent hillocks from being formed on leads or interconnection patterns.

Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

Brief description of the drawings

Figure 1 is an electron microscopic photograph showing the surface of an AI interconnection film formed without a step of ion implantation, including appreciable hillocks; Figure 2 is an electron microscopic photograph showing the surface of an AI interconnection film formed with a step of ion implantation by B, including no appreciable hillocks; Figure 3 is an electron microscopic photograph showing the surface of an AI interconnection film formed with a step of ion implantation by As, including no appreciable hillocks; Figure 4 is an electron microscopic photograph showing an A] interconnection pattern with the line width of 2.25 microns, which has been formed by wet etching without a step of ion implantation; Figure 5 is an electron microscopic photograph showing an A] interconnection pattern with the line width of 3.5 microns, which has been formed by wet etching without a step of ion implantation; Figure 6 is an electron microscopic photograph showing an A[ interconnection pattern with the line width of 2.25 microns, which has been formed by wet etching with a step of ion implantation by P; Figure 7 is an electron microscopic photograph showing an AI interconnection pattern with the line width of 3.5 microns, which has been formed by wet etching with a step of ion implantation by P; Figure 8 is an electron microscopic photograph showing a double-layer interconnection pattern of AI formed without a step of ion implantation; Figure 9 is an electron microscopic photograph showing a double-layer interconnection pattern of AI formed with a step of ion implantation by B; Figure 10 is an electron microscopic photograph showing a multilayer interconnection structure including an interlayer insulating film formed on a first metal layer by the low pressure CVD method; Figure 11 is an electron microscopic photograph showing the condition in which the interlayer insulating film shown in Figure 10 is coated with OCD; Figure 12 is a schematic illustration showing the structure of a typical semiconductor device having a multilayer interconnection pattern; Figure 13 is a graph showing the relation between the dose and the hillock density, which is obtained by plotting the experimental results for the im- planted ions of As', P and B; 2 GB 2 171 251 A Figure 14 is a graph showing the relation between the implantation energy and the hillock density, which is obtained by plotting the experimental results; Figure 15 is a graph showing the relation between the dose and the sheet resistance, which is obtained by plotting the experimental results; Figure 16 is a graph showing the relation between the cumulative failure rate and the time of failure, which is obtained by plotting the results of experiments of electromig ration; Figure 17 is a graph showing the relation between the dose and the hillock density, which is obtained by plotting the experimental results for the im- planted ions of H, B, P, As, Ar and 13F2; Figure 18 is a graph showing the distribution of implanted As ions in the direction of depth; Figure 19 is a graph showing the distribution of implanted BIF2' and Ar ions in the direction of depth; and Figure 20 is a graph showing the relation between the dose and the hillock density for the hillocks of 1 microns or higher and 0.2 microns or higher with the ion implantation of As' ions at 50 KeV.

Now, the present invention will be described more in detail by way of its specific embodiments, especially in the case where an interconnection pattern is to be formed on the surface of an LSI which is at the stage of near completion.

First, using an electrically conductive material, such as AI, AI-Si, Mo, Ti and W, which is commonly used as an excellent interconnection material in the manufacture of an LSI, a film of electrically conductive material is formed to a desired thickness according to any of the well known thin-film forming 100 techniques. For example, it is preferable to form this film to the thickness ranging from 8,000 angstroms to 1 micron according to the high speed magnetron sputtering method orthe self-rotating type E-gun evaporation method. In the present embodiment, it is assumed that a film of AI is formed to the thickness of 1 micron. Then, ions of an element, such as Ar, As and B, are implanted into this AI film by the well known ion implantation method. In the present embodiment, use is made of As ions. It is preferable 110 to carry out the ion implantation under the conditions of energy level at 60 KeV and the dose per unit area at 1 X 1016 ionSICM2. Moreover, it is preferable to set the ion concentration at 5 x 1017ions/cm3 or more in the vicinity of the surface (in particular, within 2,000 angstroms from the surface), and it is most preferable to set at 5 x 1020 ions!cm3 or more. Then, using a well known photolithography technique, the AI film is etched to define a desired interconnection pattern. Thereafter, as a heat treatment step, the resulting structure is subjected to heat treatment in a nitrogen atmosphere at 450 'C for 30 minutes.

The mechanism of production of hillocks is said to stem from anisotropic growth which takes place due to therami stresses caused by heattreatment around the crystalline nuclei locally present in the vicinity of the surface. With this as a premise, in accordance with the present invention, a step of ion implantation is added prior to the step of heat treatment with an 2 intention that crystalline nuclei are purposely pro duced to an extent that they are uniformly distributed over the entire surface, thereby causing production of nuclei and thus anisotropic growth uniformly over the entire surface to prevent the production of hillocks locally. Described more in detail, an AI film formed, for example, by evaporation is considered to be non-uniform in its internal structure. And, if there is any non-uniform structural portion locally in the vicinity of the surface, there is a possibility that the local thermal stress produced by such a non-uniform structural portion at a later heat treatment step could cause the formation of hillocks.

In accordance with the present invention, howev- er, since the structural quality of an AI film is made uniform by having ions of a predetermined element implanted into the AI film prior to the step of heat treatment, whereby the film composition in the vicinity of the AI film surface, in particular, is positively made uniform by the introduction of implanted ions, the occurrence of thermal stress concentration is prevented at the time of heat treatment. It is to be noted that, in the embodiment described above, as a means for causing a uniform growth of nuclei overthe entire surface by forming crystalline nuclei uniformly throughout the thin-film with the application of energy to the film, use has been made of the ion implantation method which is well known in the field of semiconductor technology.

It should however be noted that the present invention is not limited only to such a method and a generally used method of introducing ions, such as reverse sputtering and plasma treatment, may also be used.

In orderto confirm the principle of the present invention, the surfaces of electrically conductive layers formed by the prior art method without a step of ion implantation and the method of the present invention with a step of ion implantation have been examined using a scanning electron microscope (SEM) and electron microscopic photographs taken are shown in Figures 1 through 3. Figure 1 shows the surface of an AI interconnection layer formed by the prior art method without a step of ion implantation before the step of heat treatment. It is seen that hillocks are formed appreciably in the surface. On the other hand, Figure 2 shows the surface of an AI interconnection layer formed in accordance with the present invention with a step of ion implantation of B carried out prior to the step of heat treatment. No appreciable hillocks are seen in the surface. Figure 3 shows an AI layer formed similarly by the present invention using As ions instead of B ions, and there is no difficulty in appreciating thatthere is no appreciable hillocks formed in the surface.

Now, another aspect of the present invention in which an AI film is wetetched to define a desired pattern will be described.

First, using AI, which is commonly used as an excellent interconnection material in the manufacture of an LSI, a film of electrically conductive material is formed to a desired thickness according to any of the well known thin-film forming techniques. For example, it is preferable to form this film to the thickness ranging from 8,000 angstroms to 1 3 GB 2 171 251 A 3 micron according to the high speed magnetron sputtering method or the self-rotating type E-gun evaporation method. Here, it is assumed that a film of AI is formed to the thickness of 1 micron. Then, ions of an element, such as Ar, As and B are implanted into this AI film by the well known ion implantation method. In the present embodiment, use is made of As ions. It is preferable to carry out the ion implantation under the conditions of energy level at 60 KeV and the dose per unit area at 1, 1016 ion SICM2. It is preferable to set the ion concentration at 5 x 1017 ion S/CM3 or more in the vicinity of the surface (in particular, within 2,000 angstroms from the surface), and it is most preferable to set at 5 x 1020 ionS/CM3 or more. Then, after applying resist overthe entire surface, this resist is formed into a desired pattern.

The AI film thus patterned is then subjected to wet etching using an etching solution containing phos- phoric acid, sulfuric acid and acetic acid at the ratio of 3: 0.17: 0.6, thereby forming a desired interconnection pattern. Thereafter, as a heat treatment step, the resulting structure is heat-treated first in a nitrogen atmosphere at 430 'C for 20 minutes and then in a hydrogen atmosphere for 20 minutes.

N interconnection patterns at two line widths of 2.25 microns and 3.5 microns were wet-etched first without a step of ion implantation prior thereto and then with a step of ion implantation and the resulting structures were comparatively examined. Figure 4 shows the A[ pattern wetetched at line width of 2.25 microns without a step of ion implantation. It is easily seen that lines are not clearly cut. Figure 5 shows the case in which the A[ layer was wet-etched at line width of 3.5 microns without a step of ion implantation. A few projections extending into the cut lines are seen, and they could cause bridging between the adjacent layers. Figure 6 is the case in which the A[ layer was wet-etched at line width of 2.25 microns with a step of ion implantation by P prior to the step of heat treatment, and Figure 7 is the case for line width of 3.5 microns with a step of ion implantation by P. As shown, the etched lines are sharper and no appreciable hillocks or projections are seen.

It will now be described as to the case of forming a double-layer X interconnection pattern according to another embodiment of the present invention. Using the A] interconnection layer thus formed in a desired pattern as described in the last preceding embodiment as a first electrically conductive layer, a layer of phosphosilicate glass (PSG.) containing 2% by mole of phosphorous is formed on the first electrically conductive layer to the thickness of 8,000 angstroms as an interlayer insulating film. Then, photolithography and etching as well known in the art art carried out to define through-holes in the interlayer insulating film at desired positions. Then, N is deposited over the entire surface. Then, the thus deposited N layer is formed into a desired pattern thereby defining a second electrically conductive layer, which is isolated from the first electrically conductive layer by the interlayer insulating film except those portions connected through the through- holes. Thereafter, the resulting structure is subjected 130 to heat treatment first in a nitrogen atmosphere and then in a hydrogen atmosphere at the temperature of 430 'C.

The dou ble-layer Al interconnection structure thus formed was examined by a SEM and its electron microscopic photograph is shown in Figure 9. As may be easily appreciated from this photograph, there is no appreciable hillocks formed in the surface of the structure. Besides, the pattern is sharp and accurate and an excellent coverage is attained. In contrast, Figure 8 is an electron microscopic photograph showing a double-layer N interconnection structure formed in accordance with a prior art method without a step of ion implantation. It is seen that appreciable hillocks are formed in the surface.

As may be understood from the last two embodiments, in accordance with this aspect of the present invention, hillocks may be prevented from being formed and a fine interconnection pattern may be defined clearly by applying wet etching. Moreover, in the formation of a two-layer interconnection structure with a first electrically conductive layer having a fine pattern, an excellent coverage by an interlayer insulating film during the process of forming the two-layer interconnection structure may be attained. As described above in accordance with the present invention, since the formation of hillocks is prevented by the addition of a step of ion implantation, fine interconnection patterns may be defined using wet etching. Furthermore, it is true that dry etching may be used for the formation of a fine pattern in a multilayer interconnection structure, but there was a problem of poor coverage by the interlayer insulating film, which could result in disconnections. On the other hand, in accordance with the present invention, since wet etching may be used positively, the problem of poor coverage is obviated, and a method for forming a fine interconnection pattern excellent in coverage and having no hillocks and disconnections is provided. Particularly, when PSG or the like is used to form the interlayer insulating film in a multilayer interconnection structure, an extremely excellent coverage may be attained by the present invention. Besides, the present invention is particularly useful for the formation of a fine pattern since no irregularities, such as dents and projections, are formed along the etched edges.

A further embodiment of the present invention for forming a multilayer interconnection structure will now be described below. Using the magnetron type sputtering method, a film of AI-Si 1% is formed on a Si substrate to the thickness of approximately 6,000 angstroms over the entire surface by evaporation.

Then, boron ions are implanted into this AI-Si 1 % film by ion implantation under the conditions, including energy level at 50 KeV and dose per unit area at 1 _, 10 16 ion S/ CM2. In the vicinity of the surface, particularly within 2,000 angstroms from the surface, the ion concentration is preferably set at 5 x 10" ions,'cm3 or more, and most preferably at 5 0 1020 ion S/CM3 or more. The distribution of ion concentration within the film has a maximum approximately at 1,000 angstroms from the surface. Then, the A]-Si 1% film implanted with ions is etched by an 4 GB 2 171 251 A 4 etching solution containing phosphoric acid, nitric acid and acetic acid at the ratio of 3: 0.17: 0.6 for approximately 2.5 minutes at the temperature of 42 'C to define a desired interconnection pattern.

Thereafter, the resulting structure is heat-treated in a 70 nitrogen atmosphere at the temperature of 450 'C for minutes.

Then, an interlayer insulating film of silicon oxide is formed over the entire surface covering the AI-Si 1% film having a desired pattern to the thickness of approximately 8,000 angstroms by the CVD (chemical vapor deposition) method. When use is made of the low pressure CVD, the pressure is preferably reduced to 0.1 Torr. Then, a film of OCID (tradename) is formed on the interlayer insulating film to the thickness of approximately 1,200 angstroms. Thereafter, the resulting structure is heat-treated in a nitrogen atmosphere at the temperature of 400'C. Then, selective etching is carried outto define through-holes. Then, pure Al is deposited on the OCD layer overthe entire surface by evaporation, which is then etched into a desired pattern thereby forming a second electrically conductive layer of approximately 8, 000 angstroms thick.

Figure 10 is an electron microscopic photograph showing the two-metal layer interconnection structure having the interlayer insulating film formed by the low pressure CVD. And, Figure 11 is an electron microscopic photograph showing the condition in which the OCID is coated on the interlayer insulating film. It is to be noted that as an interconnection material, use may be made of a high melting point metal, such as Al-alloys and Mo, and a sflicide thereof.

As described above, in accordance with the present invention, it is possible to prevent hillocks from being formed on a metal interconnection layer of semiconductor device by having impurity ions implanted before the step of annealing. According to the systematic study for prevention of hillock production on the interconnection pattern of semiconductor device, it has been found that the production of hillocks can be suppressed almost completely from a practical viewpoint by having impurity ions implanted into a metal interconnection pattern at the 110 dose of approximately 1015 ions;'cml or more. This aspect of the present invention will now be described more in detail below.

Figure 12 is a schematic illustration showing the structure of a typical semiconductor device having a multilayer interconnection pattern, to which the present invention is most advantageously applied to form the interconnection pattern. As shown, as the underlying support structure, there is provided a substrate 1 which is preferably comprised of a semiconductor material, such as silicon, of one conductivity type and which includes a pair of diffusion regions 1 a and 1 b formed by doping selected impurities of opposite conductivity type. It is to be noted that the substrate I may include any other well-known elements, such as buried layers and channel stops. On the substrate 1 is formed a field oxide film 2, typically, from Si02 to the thickness of approximately 9,000 angstroms. And, a phosphosilicate glass (PSG) film 3 is formed on the field oxide film 2to the thickness of approximately 8,000 angstroms.

Furthermore, on the PSG film 3 is formed a first metal layer 4, which defines the first layer of to-be-formed multilayer interconnection pattern, to the thickness of approximately 6,000 angstroms, and second metal layers 6 and 10, which define the second layer of the multilayer interconnection pattern, are formed to the thickness of approximately 9,000 angstroms with a PSG layer 5 as an interlayer insulating layer having the thickness of approximately 8,000 angstroms sandwiched between the first and second metal layers 4 and 6 (10). The topmost layer 7 is a passivation layer having the thickness of approximately 7,000 angstroms. Also provided in the structure shown in Figure 12 are a gate oxide film 8 of approximately 500 angstroms and a polysilicon gate 9 of approximately 3,500 angstroms. It is to be noted that the particular sizes given above are only for the illustrative purpose and the present invention is no way limited only to these. In the preferred embodiment, use is made of pure Al or an alloy of Al and Si for forming either of the metal layers 4, 6 and 10.

In the structure shown in Figure 12, it is assumed for the purpose of illustration that the left-hand first metal layer 4 and the second metal layer 10 are interconnected by a via extending through a through-hole, but the right-hand first metal layer4 and the second metal layer 6 are electrically isolated from each other by the interlayer insulating layer 5. In this case, if the step of ion implantation of impurity ions at a predetermined dose level or more is not carried out after formation of the first metal layer 4, there will be produced hillocks as indicated by 5a on the top surface of the first metal layer 4 when the entire structure is subjected to heattreatmentr so that the first and second metal layer 4 and 6 may be shorted by such a hillock extending through the interlayer insulating layer 5. In accordance with this aspect of the present invention, there is provided a method of preventing the production of hillocks by carrying out the step of ion implantation with impurities at the dose level of approximately 1015 ions/cM2 from the exposed surface of thefirst metal layer subsequent to the formation thereof from a selected electrically conductive material. With the implantation of impurity ions at dose of approximately 1015 ionS/CM2, it is possible to prevent hillocks from being produced even if the first metal 4 is subjected to heat-treatment thereafter.

As described previously, it is considered that the production of hillocks takes place because particular directions of crystal growth are defined in a metal layerwhen it is formed, for example, by evaporation or sputtering, and the anisotropic crystal growth takes place depending on such particular directions when subjected to heat-treatment. However, according to this aspect of the present invention, it is considered that such particular crystal growth directions are completely destroyed by having impurity ions implanted at the dose level of approximately 1015 ionS/CM2 or more, preferably 1016 ion S/CM2 or more, after formation of a metal layer thereby forming an amorphous-like structure random in GB 2 171 251 A 5 orientation, which allowsto preventthe production of hillocks from occurring.

It is to be noted that the remaining portions of the structure shown in Figure 12 may be formed by technologies commonly used in the manufacture of semiconductor devices, such as photolithography and etching.

Figure 13 is a graph showing the experimental results as plotted with the abscissa taken for dose level and the ordinate taken for hillock density. In this experiment, after formation of a metal layer of A] on a supporting structure, such as semiconductor -device, ions of selected impurities, such as As, P and B, were implanted into the metal layer and the number of hillocks produced on the metal surface after heat-treatment were counted. And the experi ment was repeated by varying the dose of impurity ions. Described more particularly with respectto the present experiment, a PSG layer was formed on a silicon substrate to the thickness ranging from 7,000 to 9,000 angstroms, and, then, a metal layer of A]-Si was formed on the PSG layer to the thickness ranging from 7,000 to 9,000 angstroms by the DC magnetron sputtering process. Then, ion implanta tion was carried out with selected impurity ions at a dose level in a range between 1014 and 2 x 10" ion S/CM2, followed by the step os patterning and heat-treatment at430 'C. Thereafter, the number of hillocks produced on the metal layer and having sizes equal to or larger than a predetermined level were counted using observation techniques, such as SEM and XMA.

As shown in the graph of Figure 13, the present experiment was carried outfor impurity ions of As, P and B, and the ion implantation was carried out 100 always at the energy level of 50 KeV. It is easily seen from Figure 13 that the production of hillocks can be virtually eliminated from a practical viewpoint by including the step of ion implantation at the dose level of approximately 1015 ion S/CM2 or more. It is also seen from the graph of Figure 3 that the production of hillocks can be prevented almost completely irrespective of the kinds of impurities if the dose level is set at least at 5 x 10" to 1015 ion S/CM2, It is to be noted that in the present 110 experiment the reference size or height was set at 2,000 angstroms and the number of those hillocks having the height equal to or higher than the reference was counted, because those hillocks could be a problem in coverage.

Figure 14 graphically shows the experimentally obtained relation between the implantation energy taken for the abscissa and the hillock density taken for the ordinate. In this case, As ions were implanted at the dose of 101' ionS/CM.2, wherein the implantation energy was varied to see the dependency of the hillock density on implantation energy. As apparent from Figure 14, the hillock density very little depends on the implantation energy in the range of investiga- tion. As will be described more in detail later, it has been found from the surface analysis experiment that the implanted As ions (50 KeV) are mostly present at the depth of 100angstroms and its vicinity from the surface, and after heat-treatment they are shifted to the depth in a range between 1,000 and 2,000 angstroms.

Figure 15 is a graph showing the plots of experimental results indicating that the sheet resistance of AI-Si layer remains substantially unchanged overthe range of dose where the number of hillocks produced by heattreatment decreases dramatically. It is thus clearthat the resistance of metal layer forming part of interconnection pattern is not adversely affected by the step of ion implantation according to the present invention. Moreover, Figure 16 shows the results of comparative experiment between the A]-Si film implanted with As ions and AI-Si film without As implantation, and, as shown, it may be easily understood that durability against electromig ration is significantly improved by carrying out the step of ion implantation according to the present invention.

It has also been confirmed experimentally from the analysis of electron beam diffraction pattern for with and without ion implantation of As ions that the diffraction pattern without ion implantation includes continual interference fringes, but the diffraction pattern with ion implantation includes no such interference fringes. From this, it can be said that a crystalline structure of some sort is present in the metal layer after formation, and such a crystalline structure is completely destroyed by the ion implantation at a desired dose level equal to or greater than a predetermined level in accordance with the pre- sent invention, thereby converting the crystalline state into the amorphous state or the state of a collection of microcrystal line structures.

Now, a further aspect of the present invention will be described. As described previously, in accordance with the principle of the present invention, the production of hillocks on the surface of a metal layer forming an interconnection pattern is prevented from occurring by carrying out a step of implantation of impurity ions prior to the step of heat-treatment.

In accordance with this aspect of the present invention, the production of hillocks is prevented almost completely irrespective of the kind of impurity ions used by carrying out the step of ion implantation such that the depth of impurity ions implanted into the metal interconnection layer, or more specifically the peak of the distribution of impurity ions implanted, is set to be located within 800 angstroms from the surface. That is, in accordance with this aspect of the present invention, after formation of the first metal layer 4 from a selected material in the semiconductor structure shown in Figure 12, impurity ions are implanted into the first metal layer 4 from its exposed surface such that the implanted ions has a distribution whose peak is located within approximately 800 angstroms from the surface. With the presence of impurity ions so implanted, no hillocks are formed on the first metal layer 4 even if the entire structure is subjected to heat-treatment.

As described previously, it is considered that particular directions of crystal growth are defined in a metal layer when it is formed on a supporting structure and hillocks are produced when anisotropic growth of crystal takes place following these particular directions with the application of heat.

However, in accordance with this aspect of the 6 GB 2171251 A present invention, it is considered that a relatively shallow implantation of impurity ions into a metal layer to define a distribution of implantated ions therein whose peak is located within 800 angstroms, preferably within 500 angstroms, from the surface can cause these particular directions of crystal growth to be completely destroyed, thereby forming an amorphous-like random structure which allows to prevent the formation of hillocks from taking place.

Figure 17 shows in graphic form the results of the experiment in which a metal layer of Al was formed on a supporting structure, such as a semiconductor device, and impurity ions (As, P, B, Ar or BF2) were implanted into the metal layer by changing the dose level from one test to another prior to the step of heat-treatment, wherein the number of hillocks formed on the metal layer after heat- treatment were counted. In particular, in the present experiment, a PSG layer was formed on a silicon substrate to the thickness of 7,000 to 9,000 angstroms, and, then, a metal layer of A[-Si was formed on the PSG layer to the thickness of 7,000 to 9,000 angstroms by the DC magnetron sputtering process. After carrying out the step of ion implantation at a dose level ranging from 1014to 2 X 1016 ionS/CM2 to the Al-Si layer, pattern- ing and heat-treatment at 430 'C were carried out, followed by the step of observation by SEM or XMA for counting the number of meaningful hillocks.

In the graph of Figure 17, the abscissa is taken for the dose level in cm 2 and the ordinate is taken for the hillock density in number/cM2. In the present example, the ion implantation was carried Out always at the energy level of 50 KeV, and the number of those hillocks having sizes or heights larger than a predetermined reference size or height was counted 100 to determine the hillock density. According to the results plotted in the graph of Figure 17, it is seen thatthe production of hillocks can be suppressed to a minimum, which is insignificant from a practical viewpoint, if the dose level is-set approximately at 1015 ionS/CM2 or higher in the case of using As, P or B as impurity ions and if the dose level is setapproxi mately at 1014 ionS/CM2 or higher in the case of using Ar or BF2 as impurity ions. It is also seen in the graph of Figure 17that when the dose level is set at 5 x 1015 to 1016 ionS/CM2 or higher, itis possible to prevent hillocks from being produced almost comr pletely irrespective of impurity fons used. Similarly with the previous case, the reference height in counting the number of meaningful hillocks was set 115 at 2,000 angstroms also in the present case.

Figures 18 and 19 showthe distribution of impurity ions implanted into the above-described AI-Si layerwhen analyzed by SIMS. In the graph of each of these figures, the abscissa is taken forthe depth in angstroms as measured from the exposed surface where the ion implantation into the AI- Si layer is carried out and the ordinate is taken for the doping concentration in ions/cc of the impurity ions im- planted into the Al-Si layer. Figure 18 shows the distribution of As ions after the implantation thereof according to the present invention and the distribution of As ions after heat-treatment subsequeritto the step of ion implantation. In this case, the implantation of As ions was carried out at the dose 6 level of 1 / 1 Olt' ions/cm2 at the energy level of 50 KeV, and the step of heat-treatment was carried out atthe temperature of 450 "C for 30 minutes. As apparent from Figure 18, afterthe step of implanta- tion of As ions according to the present invention, the peak of the resulting distribution of As ions implanted into the Al-Si layer is located in the vicinity of the surface, approximately ranging between 100 and 300 angstroms. It is also seen that the peak still remains relatively closer to the surfaceand ranges approximately 500 to 700 angstroms from the surface.

Figure 19 shows the resulting distributions when Ar and BF2 ions were implanted into the Al-Si layer.

As shown, although the distribution of BF2 when implanted into the Al-Si layer under the condition same as that for As shown in Figure 18 is shifted slightly toward the surface, its peak is located at the position very close to the peak of As distribution shown in Figure 18. The distribution of BF2 ions after ion implantation is similarto that of As so thatit is expected thatthe distribution of BF2 after heattreatment is also similarto that of As. The graph of Figure 19 also includes two distributions of Ar ions, one after ion implantation and the other after annealing. Interestingly, a clear peak is not shown in the distribution of implanted Ar ions, but it is seen that a peak must be present very near the exposed surface. The peak of distribution of Ar ions appears to remain located within 100 angstroms from-the exposed surface either after ion implantation or after heat-treatment subsequent to the step of ion implantation. However, within the realm of experimental accuracy, it is relatively diff icuitto pin-point the location of the peak of As ion distribution. - From above, it can be easily understood that in the case of implanting impurity ions, such as As, P, B, Ar and BF2, into a film of electrically conductive material, if the ion implantation is so carried out to define a distribution of implanted ions whose peak is located within 800 angstroms (taking into consideration of various fluctuating factors) from the exposed surface, the production of hillocks can be prevented from occurring even -if the step of heat-treatment, such as annealing is carried outthereafter, Although the analysis as to why such a relatively shallow ion implantation is so effective in preventing the formation of hillocks from taking place has not yet been fully conducted, the presence of such eff ect has been also confirmed by other experimental techniques, such as electron microscopic observation and electron beam analysis pattern observation.

A still further aspect of the present invention will now be described. As indicated above, in accordance with the present invention, there is provided a method of manufacturing an interconnection pattern of semiconductor device orthe like which comprises the steps of forming a film of electrically conductive material on a supporting structure; implanting im- purity ions into the film from its exposed surface; patterning the ion- implanted film to a desired pattern; and subjecting the entire structure to heattreatment. Preferably, the step of ion implantation is carried out at a dose level of 1015 ion S.;CM2 or more.

According to this aspect of the present invention, it is 7 GB 2 171 251 A 7 preferable to carry out the step of patterning accord ing to dry etching using a positive resist. Furth ermore, the dry etching to be carried outforthe step of patterning uses a boron-chlorine family gas as an etchant gas.

Described more in detail with respect to this aspect of the present invention by way of embodi ments, when patterning the first metal layer 4 in the structure shown in Figure 12, a selected material is deposited onto the PSG film 3 and then ions of selected impurities are implanted into the thus deposed layer from the exposed surface thereof, which is followed by the step of patterning the first metal layer 4 into a desired pattern according to dry etching using a positive resist, whereby a boron chlorine family gas, such as BC13, is used as an etching gas. It has been found experimentally that when etching is carried out using SiC14 as an etching gas, the shape of metal layer deforms as a result of etching; in particular, it has been found that a step is formed at the edge of metal layer thereby making - the entire structure to be in the form of mountain.

This tendency has been found to become enhanced as the amount of ion implantation increases. On the contrary, in the case where dry etching is carried out using a boron-chlorine family gas, such as BC13, no such undesired tendency has been encountered and there has been obtained a clear and sharp edged pattern.

Thus, according to this aspect of the present 95 invention, when manufacturing an interconnection pattern for example, of a semiconductor device by depositing a metal of selected material onto a supporting structure to form a metal layer thereon, implanting selected impurity ions into the metal layer, applying dry etching to have the metal layer patterned, and subjecting the entire structure to heat-treatment, it is preferred to use a boron chlorine family gas, such as BC13, as an etchant during the step of dry etching because the metal pattern is not adversely affected by such etchant and a clear and sharp pattern can be formed without local narrowing or modification in profile.

Figure 20 graphically shows the results of experi ment conducted in connection with this aspect of the 110 present invention. That is, similarly with the pre viously described cases, a PSG film of 71000 to 9,000 angstroms thick was formed on a silicon substrate, and, then, a layer of AI-Si was formed thereon to the thickness of 7,000 to 9,000 angstroms by a DC magnetron sputtering process. Then, after implant ing As ions into the AI-Si layer atthe energy level of KeV with a variable dose level up to 2 x 1016 ions/cm', the AI-Si layer was patterned by dry etching using BC13 into a desired pattern and then the entire structure was subjected to heat-treatment at the temperature of 430'C. Thereafter, the surface of the Al-Si layer was examined by an observation technique, such as SEM and XMA, and the number of those hillocks having sizes larger than 1 micron and the number of those hillocks having sizes larger than 0.2 microns were counted. It can be seen that when the ion implantation is carried out at a dose level of 1015 ionS/CM2 or more, no appreciable hillocks are formed. It should also be noted that a sharply cut pattern may be obtained even if patterning is carried out by dry etching, While the above provides a full and complete disclosure of the preferred embodiments of the present invention, various modifications, alternate constructions and equivalents may be employed without departing from the true spirit and scope of the invention. Therefore, the above description and illustration should not be construed as limiting the scope of the invention, which is defined bythe appended claims.

Claims

1. A film pattern forming method comprising the steps of:

forming a film of a selected material on a structure; applying energy to said film; wet-etching said energy-applied film to profile said film into a desired pattern; and heat-treating said film thus patterned.

2. A method of Claim 1 wherein said step of applying energy is carried out to produce crystalline nuclei uniformly in said film.

3. A method of Claim 1 wherein said structure includes MOS transistors, and said pattern is an interconnection pattern for said MOS transistors.

4. A film pattern forming method comprising the steps of:

forming a film of a selected material on a structure; applying energy to said film; dry-etching said energy-applied film to profile said film into a desired pattern; and heat-treating said film thus patterned.

5. The method of Claim 4 wherein said step of applying energy is carried out to produce crystalline nuclei uniformly in said film.

6. The method of Claim 4 wherein said step of applying energy is carried out to produce an amorphous-like structure without preferred direction of crystal growth in said film.

7. The method of Claim 4 wherein said step of applying energy is carried out to produce a microcrystalline structure having no preferred direction of crystal growth in said film.

8. The method of Claim 4 wherein said step of applying energy is carried out by ion implantation.

9. The method of Claim 8 wherein said ion implantation is carried out at a predetermined dose level in a range of approximately 10 ion S1CM2 or more.

10. The method of Claim 4 wherein said step of dry-etching is carried out using a boron-chlorine family gas as an etching gas.

11. The method of Claim 10 wherein said boronchlorine family gas is BC13.

12. The method of Claim 4 wherein said support- ing structure is a semiconductor device and said film is an interconnection pattern of said semiconductor device.

13. The method of Claim 12 wherein said electrically conductive material includes a metal.

14. The method of Claim 13 wherein said metal is 8 GB 2 171251 A 8 -AL

15. The method of C[aim 14 wherein said electrically conductive material also includes Si.

Printed in the U K for HMSO, D8818935, 6;86,7102. Published by The Patent Office, 25 Southampton Buildings, London, WC2A lAY, from which copies maybe obtained.