GB2168527A

GB2168527A - Photo-detector

Info

Publication number: GB2168527A
Application number: GB08431710A
Authority: GB
Inventors: George Horace Brooke Thompson
Original assignee: STC PLC
Current assignee: STC PLC
Priority date: 1984-12-15
Filing date: 1984-12-15
Publication date: 1986-06-18
Also published as: GB2168527B; GB8431710D0

Abstract

A photo-detector in the form of an optical field effect transistor comprising a transparent semi- insulating InP substrate (1), a transparent p InP gate region (2), and n InGaAs channel region (3) and source and drain contacts (5,6). Light incident on the bottom face of the substrate is detected. The channel region is thicker and reduced in doping in comparison with a normal JFET in order to achieve efficient light absorption and low gate to source capacitance. The source and drain contacts are interdigitated to increase the area for optical absorption (Fig. 1). Alternatively, the channel region is a composite structure including a lowly doped layer for directing photogenerated carriers to a more highly doped layer (active channel layer) of reduced dimensions of reduced area and upon which strip-like source and drain contacts are disposed. The optical FET structures proposed facilitate integration with other circuit elements. <IMAGE>

Description

SPECIFICATION Photo-detector This invention relates to photo-detectors and in particular, although not exclusively, to optical field effect transistors comprising photo-detectors suitable for operation in optical fibre systems.

Typically photo-detections in such systems relies upon the use of avalanche photodiodes or upon the combination of a PIN diode and a FET transistor (PIN-FET combination) in which the output of the PIN diode is fed to the gate of an FET.

An optically sensitive FET can in principle combine the detector and amplifier functions of a PIN-FET and give superior sensitivity at a high modulation frequency as a result of elimination of the separate capacitance of the PIN diode. In practice the problem is to find a means of concentrating the light input on the small active area beneath the gate of the FET, and to ensure that it is all absorbed in the spacing of the channel.

According to one aspect of the present invention there is provided an optical field effect transistor comprising a semi-insulating optically transparent substrate, an optically transparent gate region of one conductivity type disposed on an area of one side of the substrate, a channel region of opposite conductivity type disposed on said gate region and source and drain contacts to said channel region, which transistor serves to detect light incident on the other side of the substrate in the vicinity of said area.

According to another aspect of the present invention there is provided a method of manufacturing an optical field effect transistor according to the preceding paragraph, the method including the steps of etching a recess in one side of a semi-insulating InP substrate, diffusing the one side of the substrate with Zn to form a p'lnP layer on the substrate, growing n InGaAs on the p'inP layer by liquid phase epitaxy whereby to fill the recess and produce a substantially planar structure, etching the n InGaAs until the InP substrate is revealed outside of the filled recess, forming source and drain contacts to the n InGaAs within the recess and isolating them from the ptlnP layer within the filled recess, and providing a gate contact to the pilnP layer within the filled recess.

Embodiments of the present invention will now be described with reference to the accompanying drawings, in which: Figure 1 illustrates a partially-sectioned view of one embodiment of optical FET; Figure 2 illustrates a partially-sectioned view of another embodiment of optical FET, and Figures 3a,b and c illustrate stages in the manufacture of the device of Fig. 1.

A conventional compound semiconductor JFET basically comprises a semi-insulating substrate upon which is a relatively high conductivity channel layer. Source, drain and gate contacts are made to the channel layer from the same surface thereof. In such an arrangement when used as an optical FET there is little area available for absorption into the channel of light incident on the surface. In an alternative FET structure the gate is disposed under the channel layer and thus the depletion region extends towards the said surface rather than away from it. This alternative structure in theory provides a greater area for light absorption into the channel from said surface and such a structure has been proposed as an optical FET in "New minority hole sinked photoconductive detector" by C.Y. Chen et al. Appl.Phys.Lett.43(12) 15 December 1983 p115.

The structure proposed therein has a spacing between the source and drain contacts of 4,um and is of high capacitance in view of the large gate area. The spacing between the source and drain contacts should ideally be reduced to around 1,um to reduce carrier transit time, to reduce the FET cut-off frequency and to reduce the FET noise contribution. However if the source drain contact spacing is so decreased in the known structure then once again there is little area for absorption into the channel of light incident on the surface.

One way of reducing the drain source spacing which we now propose is to use interdigitated source and drain electrodes to produce a nearly square active area and to illuminate the device from the substrate side. This is possible since InP used for the substrate, for example, is transparent. The total source to gate capacitance must not be allowed to increase or sensitivity will again be prejudiced. To counteract the increase in area the thickness of the channel must be increased, and its doping level reduced, so that the gate may be sufficiently biased largely to deplete the channel. This increase in channel thickness is also very necessary to ensure substantially complete absorption of normally incident light.

These modifications produce an optical FET with unorthodox geometry and some unusual secondary characteristics. The source to drain spacing remains the same but instead of the channel thickness being about five times smaller than, it is about three times larger. Also the source and drain width is increased by a factor of ten to fifteen and the current per unit width has decreased in inverse proportion. Because of the low source current per unit width, the source and drain contacts can have very small dimensions in the direction of current flow in the channel and of the same order or even smaller than the source to drain spacing.If the gates were located in the conventional position between source and drain on top of the channel the fringe fields from adjacent gates in an interdigititated layout would then overlap as they spread across the thick channel under the source and drain contacts. Thus it is advantageous to dispense with the normal gates placed on top of the channel and substitute them by a continuous gate embedded below the channel. An example of such a structure is indicated in Fig. 1.

The optical FET device of Fig. 1 comprises a semi-insulating InP substrate 1, a p+InP gate 2, an n-lnGaAs channel layer 3, an optional p+lnGaAs surface layer 4 and interdigitated source and drain contacts 5 and 6, respectively. The drain contacts are interconnected (not shown) in a manner similar to the interconnection of the source contacts. Fig. 1 only shows one half of the device. The gate is continuous under the whole channel area where light is absorbed and only extends from under the channel layer by an amount sufficient for electrical contact purposes, as at 2a. The embedded gate requires no self-alignment for its manufacture, as would multiple gates on top of the channel and it also reacts more strongly with the semiconductor underneath the source and drain contacts, adding a little more to the transconductance.Typically the doping levels and thicknesses of the layers 2 to 4 of Fig. 1 are as follows: Doping Level Thickness Layer 2-2X10'8 cm-3 0.5 ,ltm Layer 3-2X10'5 cm-3 2 ,ttm Layer 4-5X 10t7 cm-3 700 A With a negatively biased gate and the drain being positively biased with respect to the source the depletion region is as shaded.

The structure of Fig. 1 can be converted into an opto-HEMT (High Electron Mobility Transistor) by using an nt layer of higher bandgap than layer 3, eg InP, or InAIAs, and of appropriate thickness for layer 4. Layer 3 should be very low doped. The channel then consists of a two dimensional electron gas in the InGaAs layer 3 immediately below layer 4. This provides improved mobility. The source and drain contacts must then be sufficiently alloyed or suitably implanted to penetrate through layer 4 into layer 3.

Fig. 2 illustrates an alternative layout in which a wide embedded p+lnP gate 7 disposed on a semi-insulating InP substrate 8 is associated with a non-interdigitated FET, having strip-like source and drain contacts 9 and 10, respectively, in such a way that carriers which are generated in the channel 11 over the whole area of the gate are focussed by the potential distribution into a smaller area strip-like channel layer 12. Thus the channel is comprised of two parts, the thick and very pure (n )InGaAs layer 11 immediately on top of the gate, and the thin and more highly doped (n)lnGaAs layer 12 above it which is restricted in width to the combined dimensions of the source and drain and the spacing between them, the contacts being parallel to one another and the length of layer 12.Since the main space charge will be generated in layer 12 the field lines will follow the converging pattern between the gate and the channel layer 12 as illustrated and direct the photogenerated carriers towards the critical part (12) of the channel.

This structure will have a somewhat lower capacitance than that in Fig. 1 but will demand better contacts because of the higher current density through the channel.

The structure of Fig. 2 can be converted into an opto-HEMT (High Electron Mobility Transistor) by substituting a thin layer of n-lnP for the n InGaAs layer 12. The channel then consists of a two dimensional electron gas in the InGaAs layer 11 immediately below the InP. This provides improved mobility. Typically the doping levels and the thickness of the layers 7,11 and 12 of Fig. 2 are as follows: Doping Level Thickness Layer 7 2X10iscm 3 0.5 ijm Layer 11 5X 1014 cm 3 3 Xtm Layer 12 3X10'6 cm 3 0.2 ,um The fabrication of the devices may be based on the scheme illustrated in Fig. 3 to produce a planar geometry.Recesses 13 (Fig. 3a) are formed in a semi-insulating InP substrate 14, the surface of which is then zinc diffused to form a p'lnP layer 15 part of which is ultimately the gate. The p'InP is removed on three sides 20 of the recess by appropriate masking with a resist and etching. Over the entire layer 15 n InGaAs 16 is then grown by liquid phase epitaxy until a reasonably planar surface is obtained, and the recesses are filled. The wafer is then etched back with a non-selective etch until the semi-insulating substrate 14 is revealed outside of the recesses, that is to line 17, leaving localised regions of InGaAs lined on the underside with p*lnP. Interdigitated, in the case of Fig. 1, source and drain contacts 18,19 are registered on the InGaAs with metallic input connections carried over onto the semi-insulating InP (Fig. 3b).

Finally appropriate contact 21 is made to the p'lnP gate region 15 together with metallisation 22 (Fig. 3c) which is a section at right angles to Fig. 3b).

Both of the structures illustrated are appropriate for integrating monolithically with separate FET's formed on the insulating substrate and have low capacitance, thus rendering them appropriate for use in sensitive optical receivers. In the Fig. 2 structure the layers of n InGaAs used in the optical FET can also be used for the channel of separate JFET's and layers of n+InP and undoped GalnAs used in the optical HEMT can also be used for the channel of separate HEMT's. The optical FET of the present invention, which may be termed an optical embedded gate FET (OPEGFET), combines a number of features to produce a structure with low gate stray capacitance, these features being increase in the area for optical absorption, thickening of the channel layer with reduction in doping to more efficiently absorb the incident light whilst maintaining a low gate to source capacitance, and the embedding of a p-type gate layer beneath the channel layer, which gate layer is continuous over the whole area where light is absorbed, the device being illuminated at its substrate surface rather than its channel surface. In practice a load resistance in series with the gate is required, this may be readily manufactured by conventional techniques on the same substrate and electricaly connected to the gate, that is integrally formed with the optical FET.

Claims

1. An optical field effect transistor comprising a semi-insulating optically transparent substrate, an optically transparent gate region of one conductivity type disposed on an area of one side of the substrate, a channel region of opposite conductivity type disposed on said gate region and source and drain contacts to said channel region, which transistor serves to detect light incident on the other side of the substrate in the vicinity of said area.

2. An optical field effect transistor as claimed in claim 1 wherein in comparison with a conventional JFET the channel region is considerably increased in thickness and reduced in doping whereby to achieve efficient light absorption and low gate to source capacitance and wherein the gate region is continuous over the whole area where light is absorbed.

3. An optical field effect transistor as claimed in claim 1 or claim 2 wherein the source and drain contacts are of an interdigitated structure.

4. An optical field effect transistor as claimed in claim 3 wherein the substrate is of semiinsulating InP, the gate region is of p lnP and the channel region is of n InGaAs.

5. An optical field effect transistor as claimed in claim 4 further including a p InGaAs layer on the channel region and under the contacts.

6. An optical field effect transistor as claimed in claim 3, wherein the substrate is of semiinsulating InP, the gate region is of p'lnP, the channel region is of very lowly doped n InGaAs and including an nlnP or n InAlAs layer on the channel region and under the contacts.

7. An optical field effect transistor as claimed in claim 1 or claim 2, wherein the channel region is a composite structure including a relatively thick low doped layer disposed on said region and a more highly doped strip-shaped layer disposed on a portion of the low doped layer, the source and drain contacts comprising strip contacts disposed on the strip-shaped layer in parallel with one another and in parallel with the length of the strip-shaped layer, which low doped layer serves in use of the transistor to direct photogenerated carriers towards the stripshaped layer.

8. An optical field effect transistor as claimed in claim 7, wherein the substrate is of semiinsulating InP, the gate region is of p 'InP, the low doped layer is of n InGaAs and the more highly doped layer is of n InGaAs.

9. An optical field effect transistor as claimed in Claim 7, wherein the substrate is of semiinsulating InP, the gate region is of p' lnP, the low doped layer is of n InGaAs and the more highly doped layer is of n InP.

10. An optical field effect transistor as claimed in any one of the preceding claims wherein in use the gate is negatively biased with respect to the source, and the drain is positively biased with respect to the source.

11. A method of manufacturing an optical field effect transistor according to claim 1, the method including the steps of etching a recess in one side of a semi-insulating InP substrate, diffusing the one side of the substrate with Zn to form a p InP layer on the substrate, selectively removing some of the p' lnP layer around the periphery of the recess, growing n InGaAs on the p' lnP layer by liquid phase epitaxy whereby to fill the recess and produce a substantially planar structure, etching the n InGaAs until the InP substrate is revealed outside of the filled recess, forming source and drain contacts to the n InGaAs within the recess and providing a gate contact to the plnP layer within the filled recess.

12. An optical field effect transistor substantially as herein described with reference to and as illustrated in Fig. 1 or Fig. 2 of the accompanying drawings.

13. A method of manufacturing an optical field effect transistor substantially as herein described with reference to and as illustrated in Fig. 3 of the accompanying drawings.