JPS62250675A - Photodetector - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to optical detectors, especially optical fiber systems.
The present invention relates to a photofield effect transistor equipped with a photodetector suitable for operation.

[Prior art and its problems] Light detection in such optical fiber systems is usually performed by an avalanche photodiode or by a PI
PI where the output of the N diode is fed to the gate under EF
Combination of N diode and FET transistor (PIN
-EFT coupling).

As a general rule, PIN-FE is an optically sensitive FET.
By combining the detection and amplification functions of T and eliminating the isolation capacitance of the PIN diode, high-grade sensitivity can be obtained at high modulation frequencies. In practice, the problem is that the optical input must be concentrated in a small active area under the gate of the FET, and all of this optical input must be absorbed into the channel space.

SUMMARY OF THE INVENTION According to the invention, a semi-insulating optically transparent substrate and an optically transparent gate of one conductivity type located in an area on one side of the substrate are provided. a channel region of opposite conductivity type located on the gate region, and source and train contacts in contact with the channel region, detecting light incident on the opposite side near the area on the -side of the substrate. A concave portion is etched in the photovoltaic substrate, Zn is diffused on one side of the substrate, and a part of the p+ type TNPs around the p+ pear-shaped InP is selectively removed on the substrate.
By growing n'' type 1 nGaAs on the + type InP layer by liquid phase epitaxial method, the recess is filled and a substantially planar structure is formed, and the n- type is grown until an InP substrate appears outside the filled recess. Etch the concentration of n-type InGaAS and deposit n-type 1 nGaAs within the recess.
A method of manufacturing a photofield effect transistor is provided which includes forming source and drain contacts in 1li and providing a gate contact in p9 type InPI within a filled recess.

Example 1 A conventional composite semiconductor JFET (junction field effect transistor) essentially comprises a semi-insulating substrate, on which is a relatively highly conductive channel layer. The source, drain, and gate contacts are formed on the same surface of the channel layer. In such a configuration, when used as an optical FET, there is only a small area in the channel to absorb optical input impinging on the surface.

In another configuration of the FET, the gate is located below the channel layer so that the depletion region is formed to extend toward the substrate surface rather than away from the substrate surface. This second configuration theoretically provides a larger area for absorbing light from the substrate surface into the channel, and such a configuration is well known in the literature [e.g.
°゛New Minority, Hall, by Chen et al.
Think, Photo, Conductive, Detector (N
ewminority hole 5 inked
photoconductive detector)
”(”AI)l)In, Phys, Lett, 4
3(12), December 15, 1983, page 115.) The configuration presented here has a 4 micrometer spacing between the source and drain contacts and a large gate area. The spacing between source and drain contacts is reduced to around 1 micrometer to reduce carrier transmission time, reduce FET cutoff frequency, and even reduce FET noise contribution. Ideally, it would be possible to

However, in the prior art, such a reduction in the spacing between the source and the drain leaves less area for absorption of surface light incident on the channel.

Decreasing the distance between source and drain according to this invention 1
One method involves interdigitating source and drain electrodes to form a substantially rectangular active region and irradiating the device from the substrate side. This is possible if the InP used in the substrate is transparent, for example. The gate-source capacitance must not increase or the sensitivity will be impaired again. By increasing the thickness of the channel and lowering its doping concentration as opposed to increasing the area, the gate must be sufficiently biased to deplete the channel. Increasing the thickness of the channel is also necessary for virtually complete absorption of normally incoming light.

The various examples described above result in optical FETs with unusual configurations and some secondary properties. The spacing between source and drain is approximately three times as large, even though the channel thickness is approximately one-fifth as thick. Further, the width of the source and drain is 10 to 15 times larger, and the current per unit width decreases in inverse proportion. Because the source current per unit width is small, the dimensions of the source and drain contacts in the current direction within the channel are comparable to or smaller than the spacing between the source and drain.

If the gate is located between the source and drain at the top of the channel, as in a conventional transistor configuration, the interfering electric field from adjacent gates will be transmitted to the thick wall below the source and drain contacts in an interdigital fashion. They overlap because they extend through channels. Therefore, instead of the usual gate placed at the top of the channel, it is advantageous to place a continuous gate buried under the channel. An example of such a configuration is shown in FIG. The photofield effect transistor shown in the first factor includes a semi-insulating InPI plate 1, a p+ type InP gate 2, an n-type 1 n
GaA! 3 channel layer 3, p+ type 1 provided as necessary
An nGaAS surface layer 4 is provided with source and drain contacts 5 and 6 in an interdigitated configuration. The drain contacts are interconnected as are the source contacts (not shown). Only half of the device is shown in FIG. The gate extends below the entire channel region where light is absorbed and is designated 2a. As such, a sufficient amount of electrical contact extends below the channel layer. The fabrication of buried gates does not require self-alignment, such as multiple layers on top of the channel, and the gates react strongly with the semiconductor below the source and drain contacts.
Adds to mutual conductance, albeit to a small extent. Usually shown in Figure 1! l! The doping levels and thicknesses for 2-4 are as follows.

Doping level Thickness layer 2 2X101Bcm" 0.5m layer 3 2X
101'α-32ts layer 4 2X10! The Tcm' 700A gate is negatively biased, the drain is positively biased with respect to the source, and the shaded area is the depletion region.

InP or InA with a higher bandgap than layer 3
By using a layer 4 of suitable thickness with an n+ type layer such as IAS, the transistor of the configuration shown in FIG.
It becomes MT (high electron mobility transistor). The doping concentration of layer 3 must be fairly low. The channel therefore consists of a two-dimensional electron gas in the in(3aAS layer 3) just below lI4, which facilitates mobility.The source and drain contacts are then made through the layer Il!4. 3 must be sufficiently alloyed or properly implanted with ions so as to be in a state of penetration.

Another structure of the phototransistor of the invention is shown in FIG. 2, in which a large buried p+ type InP gate 7 disposed on a semi-insulating InP substrate 8 is connected to a non-interdigital FET. With strip-shaped source and drain contacts 9, 10, the carriers generated in the channel 11 over the area of the entire gate region are concentrated into a narrower strip-shaped channel layer 12 by the potential distribution. The channel is therefore a thick very pure n just above the gate head.
- type 1 nGaAs layer 11 and above this layer 11 a thinner, more highly doped n-type 1 whose width is limited to the sum of the source, drain and the spacing between them;
It consists of an nGaAs layer 12, the contacts being parallel to each other and extending along the length of the layer 12. Since most of the space charge is generated within l112, the electric field lines follow the converging pattern between gate 7 and channel layer 12 as shown in FIG. Orient to section 12. This transistor has a somewhat lower capacitance than that shown in FIG. 1, but requires better contact because the current density through the channel is higher.

The transistor shown in FIG. 2 consists of an n-type InGaAs layer 1
Optical HEMT can be achieved by changing 2 to a thin n“ type InP layer.
C high electron mobility transistor). In this case, the channel is l nQa just below InP)1
The AsGaAs layer consists of a planar electron gas. This improves mobility. Typical doping levels and thicknesses for 1517.11.12 are as follows.

Doping level Thickness layer 7 2X10"CIl"' 0.54 layer 11
5X101' as°33 Tan layer 12 3X101
"on'3 0.2 pt The coverage of the device of the present invention is based on the method of forming a planar structure shown in FIGS. 3a to 3c.

A recess 13 is formed in the semi-insulating InPI plate 14, and zinc is diffused into the surface thereof to form a p+ type InP layer 15, a portion of which will eventually become the gate. The p+ pear-shaped InP is removed on three sides 20 of the recess 13 by etching. Next, n-type InGaAsli 16 is formed by liquid layer epitaxial growth to fill the recesses 13 and to cover the entire layer 15 until a sufficient planar surface is obtained. The wafer is then etched down to the line 17 so that the semi-insulating substrate 14 appears outside the recess 13, and the p+ pear-shaped In
It is etched non-selectively to leave InGaAsfli[ located at P. In the interdigital state shown in FIG. 1, source and drain contacts 18 and 19 are formed on the InGaAs 1l (third
(see figure b). Finally, a suitable contact 21 with a metallization 22 is formed in the p'' (nP out-of-gauge region 15 (see FIG. 3C, perpendicular to FIG. 3B)). Both are suitable for monolithically integrating isolated FETs formed on an insulating substrate, and their low capacitance makes them suitable for use in high-sensitivity optical receivers. In the transistor configuration, n-type 1 used in optical FET
An nGaA3 layer can also be used for the channel of the isolated JFET, and n+ type InPI and undoped Ga I nAs1I used in optical HEMTs can also be used for the channel of the isolated HEMT. The optical FET of the present invention, referred to as an embedded gate optical FET (OPEGFET), combines a number of properties to form a low stray capacitance configuration. This means reducing the doping and making the channel layer thinner to more efficiently absorb the incident light, while keeping the source-gate capacitance low, and making the channel layer a continuous p-type gate layer throughout the concentration range where light is absorbed. The device is configured to irradiate the substrate surface rather than the channel surface. In practice, a load resistor is required in series with the gate, which is manufactured in the same substrate in a conventional manner and is electrically connected to the gate which is symbolically formed with the optical FET.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating an embodiment of an optical FET, a part of which is cross-sectional. FIG. 2 shows another embodiment of a partially cross-sectional optical FET. Figures 3a to 3c represent the manufacturing stages of the device shown in Figure 1.

Claims (11)

[Claims] (1) a semi-insulating optically transparent substrate, an optically transparent gate region of one conductivity type located in an area on one side of the substrate, and an opposite conductivity type located on the gate region; A photofield-effect transistor comprising a channel region, a source and a drain in contact with the channel region, and a contact for detecting light incident on an opposite side of a substrate near said area. (2) Compared to a normal junction field effect transistor,
The thickness of the channel region is considerably large and the doping concentration is small, so that the light is absorbed sufficiently and the source-gate capacitance is low, and the gate region extends over the entire region where the light is absorbed. Range 1
The photo-field effect transistor described in . (3) The photo-field effect transistor according to claim 1 or 2, wherein the source and drain are arranged so that they intersect with each other. (4) The substrate is semi-insulating InP, and the gate region is p^+
type InP, and the channel region is n^-type InGaAs.
A photo-field effect transistor according to claim 3. (5) P-type In under the contact on the channel region
5. The photo-field effect transistor according to claim 4, which has a GaAs layer. (6) The substrate is made of semi-insulating InP, the gate region is made of p^+ type InP, the channel region is made of lightly doped InGaAs, and the n^+ type is made above the channel region and below the contact. InP or n^+ type In
4. A photo-field effect transistor according to claim 3, comprising a layer of AlAs. (7) the channel region has a composite structure comprising a relatively thick lightly doped layer located on said region and a more highly doped strip-shaped layer located on a portion of the lightly doped layer; , with source and drain contacts located on this strip-shaped layer and parallel to each other and parallel to the length of the strip-shaped layer, a lightly doped layer directing photogenerated carriers into the strip-shaped layer. Claim 1 or 2
The photo-field effect transistor described in . (8) The substrate is semi-insulating InP, and the gate region is p^+
The type is InP, and the lightly doped layer is n^-^-type I.
nGaAs, and the more highly doped layer is n-type I.
The photo-field effect transistor according to claim 7, which is nGaAs. (9) The substrate is semi-insulating InP, and the gate region is p^+
The type is InP, and the lightly doped layer is n^-^-type I.
nGaAs, and the higher concentration doping layer is n^+
8. The photo-field effect transistor according to claim 7, which is of type InP. (10) The photoelectric field effect according to any one of claims 1 to 9, wherein the gate is negatively biased with respect to the source and the drain is positively biased with respect to the source during use. type transistor. (11) Etch a recess on one side of the semi-insulating InP substrate, diffuse Zn on one side of the substrate to form a p^+ type InP layer on the substrate, and remove the p^+ type InP layer around the recess. By selectively removing a part of the p^+ type InP layer and growing n^- type InGaAs on the p^+ type InP layer by liquid phase epitaxial method, the recesses are filled and a substantially planar structure is formed. Etch the n^-type InGaAs layer outside the filled recess until the InP substrate is exposed, form source and drain contacts to the n-type InGaAs layer within the recess, and etch the p^-type InGaAs layer within the filled recess. +type I
A method of manufacturing a photo-field effect transistor, including the step of providing a gate contact in an nP layer.