JPS6184061A - Semiconductor photoelectric converter - Google Patents

Abstract

PURPOSE:To raise the yield of carrier in the gate regions and to enable to improve the photoelectric conversion efficiency in a semiconductor photoelectric converter by a method wherein, when the semiconductor photoelectric converter is constituted in the structure; wherein the source region is provided in the semiconductor layer, the gate regions to encircle the source region are provided in the semiconductor layer, and moreover, the drain regions to encircle the gate regions are provided in the semiconductor layer; the drain regions are made to function as the sensitizing regions as well. CONSTITUTION:An N<-> type layer 32 is made to epitaxially grow on an N<-> type Si substrate 31, an N<-> type source region 33 is formed by diffusion in the central part of the layer 32 and P<+> type gate regions 34 are formed by diffusion while encircling the source region 33. Then, N<+> type regions 35, which are the drain regions as well as are made to function as the sensitizing regions while encircling the regions 34, are formed by diffusion up to reach the substrate 31 and a gate electrode 36 mounted on the region 33 is earthed. Moreover, a gate electrode 37 mounted on the region 34 is connected to a bias power source 40 through a resistor 39 and is given bias voltage VG and a drain electrode 38 mounted on the region 35 is connected to a bias power source 42 through a load resistor 41 and is given drain voltage VDS. The drop in voltage on the resistor 41, which is caused by photo current, is designed in such a way as to lead out from an output terminal 43 in such a way.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor photoelectric conversion device that uses a static induction transistor (SIT) as a photodetection and switching element.

(Prior art) A semiconductor photoelectric conversion device using SIT as a photodetection and switching element is disclosed in, for example, Japanese Patent Application Laid-Open No. 58-1) 3386.
No. 59-107569 and No. 59-107570. Figure 2 A is JP-A-59-107.
The figure shows the pixel structure of the one-dimensional sensor described in Japanese Patent No. 569, in which 1 is an n+ substrate made of Si, 2 is a high-resistance n-layer or an intrinsic semiconductor layer, and 3 is a first gate (1) consisting of a door region with a high impurity concentration. (referred to as a control gate), 4 is a high impurity concentration gate formed to surround the control gate 3. 5 is a source consisting of a region, and 5 is a second gate (5) consisting of a high impurity region for isolating adjacent pixels.
(called shielding gate), 6 is SiO2, Si3
a gate insulating film such as N, 7 a control gate electrode,
8 is a source electrode, 9 is a shielding gate electrode, 10
indicates the drain electrode. A readout pulse φGllφ(, 2+...) is applied to the control gate electrode 7 of successive pixels from a pixel selection circuit (not shown), and the shielding gate electrode 9 is commonly connected to all pixels, and a bias circuit (not shown) is applied to the control gate electrode 7 of successive pixels. A predetermined voltage vsG is applied from the drain electrode 10 to the bidet fourteenth source 12 via a load resistor 11.

FIG. 2B is an equivalent circuit diagram of FIG. 2A, in which 13 equivalently represents an SIT having a control gate for light reception, and 14 equivalently representing an SIT having a parasitic shielding gate.

In the one-dimensional sensor shown in FIG. 2A, by applying a constant bias voltage VSG to the shielding gate electrode 9 commonly connected to all pixels, the depletion layer is removed from each shielding gate 5. spread, thereby allowing each pixel to be separated from each other. Such a separation method has the advantage of simplifying the structure, but on the other hand, since separation is performed at the depletion layer, photocharges generated in the vicinity are collected through the shielding gate 5, resulting in a problem of reduced sensitivity. One possible way to solve this problem is to lower the bias voltage SG applied to the shielding gate IW electrode to suppress the expansion of the depletion layer. There is a problem in that so-called signal crosstalk occurs in which the photocharges accumulated in the gates flow into the adjacent control gates 3 via the shielding gates 5.

Furthermore, as another separation method, a method in which a diffusion layer of the same conductivity type as the substrate is provided between pixels has been proposed.

However, in conventional semiconductor YC electric conversion devices with this separation structure, photocharges generated by light irradiation are transferred to the SI
In order to effectively collect light in the gate region of the SIT and to increase the density of pixel packaging, a diffusion layer serving as a separate region is provided close to the gate region of the SIT. Therefore, the light-receiving area of each pixel (SIT) is small, and there are problems in that the S/N ratio of the signal is particularly poor in weak light, and the spectral sensitivity for short wavelength light is low.

(Object of the Invention) An object of the present invention is to solve the above-mentioned problems and to provide a semiconductor charging conversion device with a high degree of failure.

(Summary of the Invention) The present invention provides a channel region made of a -conductive turtle type high-resistance semiconductor, and a ? One main electrode region and the other main electrode region of one conductivity type are provided facing each other through the channel region, and a main electrode region of the opposite conductivity type is provided in contact with the channel region to control the current flowing between the two main electrode regions. A static "JL reader" comprising a gate region and a sensitizing region of one conductivity type, which is provided at least a diffusion length of carriers caused by co-photoexcitation from the gate region and promotes the movement of carriers to the gate region. It is characterized by having a plurality of transistors arranged.

Here, for example, the substrate is used as a door, and the depletion layer that spreads laterally from the P+ diffusion layer of the opposite conductivity type is used as the light-receiving region. Suppose that a narrow N+ layer with 1 fortune is formed. In this way, the N layer acts as a potential valley for electrons among the electron-hole pairs generated in the light-receiving region.
Conversely, it acts as a wall for holes. Therefore, electron-hole pairs are easily dissociated due to the presence of the N+ layer, electrons are absorbed by the N+ layer, and holes are reflected by the N''Wt potential wall and diffused into the P+ region. Since the holes will diffuse through regions with low electron concentration,
Its diffusion length becomes longer. When the diffusion length becomes longer in this way, holes generated in a more distant light-receiving region can also be collected in the P+ region, resulting in improved sensitivity.

The results of experimentally confirming this will be explained with reference to FIGS. 3A to 3C and FIG. 4. Figures 3A to 3C show samples used in the experiment, and Figure 3A shows an i
Jt722 is epitaxially grown, and a diffusion region 28 is formed in this one layer 22 to form a PIN7 photodiode, and the 31st JB is formed with a V-groove reaching the NQ'' plate 21C between adjacent PIN7 photodiodes to form a dielectric 24.
In addition, in FIG. 3C, a door diffusion layer 25 reaching the door substrate 21 is formed instead of embedding the VFT dielectric. In addition, in FIGS. 3B and 3C, the door diffusion area 23
distance rAX between dielectric 24 and N+ diffusion region 25
are each equal. The experiment was carried out by moving each sample and a small-diameter light beam spot using a light source such as a laser, and irradiating the light beam spot onto the surface of the P-N photodiode to determine the PIN at each position X.
The photocurrent Iph of the photodiode is measured and its sensitivity distribution is determined.

Figure 4 shows the experimental results, where the vertical axis is the photocurrent;
h, the horizontal axis represents the distance X from the P+ diffusion region 23,
Curved lines a, b, and C show the sensitivity distributions for the samples of FIG. 3, A, B, and C, respectively. As curve ia shows, the photocurrent ph decreases exponentially with distance X when there is nothing between adjacent PIN photodiodes. On the other hand, as shown by curves C and C, when there is a dielectric 24 and an N diffusion region 25 between adjacent PIN photodiodes, which acts as an isolation region, the photocurrent ph decreases rapidly within the isolation region. , the change in photoelectric current pH during this period is much smaller when the N+ diffusion layer 25 is provided than when the dielectric layer 24 is provided, and from this result, the diffusion M25 is considered to be a sensitizing region that significantly increases sensitivity. It has been proven that it works. In addition, in FIG. 3G, the distance between the door expansion area 28 and the diffusion layer 25 is such that the impurity concentration of the diffusion layer 25 is 1 × 1 (112 am-8 (7
) is 60μmqlXIQ Crn is 20
μm, I X 10110l4” (7) then 6
μm % I X 1/j when 10 am
Approximately m is suitable.

(Embodiment) FIGS. 1A and 1B show a first embodiment of the present invention.
FIG. 1A shows the cross-sectional structure of one pixel, and FIG. 1B shows its equivalent circuit. In this example, an N-epitaxial layer 32 is grown on an N substrate 31, and this epitaxial layer 32 is coated with N.
A + source region 33 and a P+ gate region 84 are formed to surround it, and an N+ diffusion layer that also serves as an isolation region is formed between adjacent pixels at a position separated by a co-hole diffusion length from the P+ gate region 34. Sensitized area 35 consisting of layers
is formed so as to reach the N+ substrate 31. In addition, 36.
37 and 38 indicate a source electrode, a gate electrode, and a drain voltage pole, respectively, and a source electrode 86 is on the γ ground;
Gate 'i1! A resistor 89 is connected to the pole 37 to apply a bias voltage VG from a bias power source 40, and a drain voltage vDs is applied from a bias power source 42 to the drain electrode a8 via a load resistor 41. The voltage drop caused by the photocurrent is taken out from the output terminal 43.

FIG. 5 shows another embodiment of the invention.

In this example, a narrow groove is formed in the epitaxial layer 82.
The trench is dug to a depth that reaches the substrate 31, a sensitizing region 35 consisting of an N+ diffusion region is formed along the sides of the V-groove, the V-groove is filled with an insulator 45, and a drain voltage is applied to the back surface of the N+ substrate 31. 1A and 1B in that the P+ gate region 34 and the sensitizing region 85 are similarly separated by a small co-hole diffusion length. In this example, since a V-groove is formed and the sensitizing region 35 is formed along the side surface thereof, it is formed by diffusing it from the surface of the epitaxial layer 82 as shown in FIGS. 1A and 1E. Compared to the case of
It has the advantage of being extremely small to μm, allowing for a wider light-receiving area.

FIGS. 6A and 6B show still another embodiment of the present invention. In this example, a linear array sensor is shown, and FIG. 6A shows the pixel structure. , FIG. 6B represents the entire equivalent circuit.

In this example, the pixel structure is different from that in FIG. The circuit configuration is shown in Figure 2A.

There is an advantage that the branching path without the SIT with a parasitic shielding gate as in B is simplified.

Note that the present invention is not limited to the above-mentioned example, and can be modified or changed in many ways.

For example, in FIG.
The gain region 35 consisting of + diffusion region may be provided separately, and in this case, instead of filling the V groove with an insulator, a P+
Depletion layer separation by region can also be applied. Also,
By applying an appropriate bias to the sensitized region 35,
It may be formed apart from the substrate 81.

(Effects of the Invention) As described above, according to the present invention, by providing a sensitizing region, it is possible to increase the collection rate of carriers in the gate region, thereby increasing the photoelectric conversion efficiency and thus improving the sensitivity. In addition, the light-receiving area can be increased, and the spectral sensitivity to short wavelength light can also be improved.

For example, when the SIT image sensor according to the present invention is constructed by making the sensitizing region also function as a separation region, when the SIT image sensor according to the present invention is constructed by applying depletion layer separation as shown in FIG. 2A, In comparison, sensitivity and photosensitivity can be improved by 20 to 30%.

[Brief explanation of drawings]

Figures 1A and B are diagrams for explaining the first embodiment of the present invention, Figures 2A and B are diagrams for explaining the conventional example, and Figures 8A-C and 4 are diagrams for explaining the present invention. FIG. 5 is a diagram for explaining the second embodiment of the present invention, and FIGS. 6A and B are diagrams for explaining the third embodiment of the present invention. 31... Substrate 32... Epitaxial layer a3... Source region Re... Gate region 35... Sensitizing region 36... Source 11 pole 37... Gate electrode'#8 38... Drain electrode 45... Insulator 47... Insulating film first
Figure 2 Figure 3 A ph Figure 4 Figure 5

Claims (3)

[Claims] 1. a channel region made of a high-resistance semiconductor of one conductivity type;
One main electrode region and the other main electrode region of one conductivity type are provided facing each other through the channel region, and a main electrode region is provided in contact with the channel region in order to control the current flowing between these two main electrode regions. A gate region of opposite conductivity type and a sensitizing region of one conductivity type that is provided at least a diffusion length of carriers generated by co-photoexcitation from the gate region and promotes the movement of carriers to the gate region. A semiconductor photoelectric conversion device characterized by having a plurality of electrostatic induction transistors arranged in an array. 2. 2. The semiconductor photoelectric conversion device according to claim 1, wherein the sensitizing region is configured to separate adjacent static induction transistors. 3. 2. The semiconductor photoelectric conversion device according to claim 1, wherein an insulating isolation region is provided between adjacent static induction transistors, and the sensitizing region is provided along a side surface of the insulating isolation region.