GB2165397A - Transceiver element - Google Patents

Description

1

SPECIFICATION

Transceiver element This invention relates to antenna systems and more 70 particularly to phased array antenna systems.

As is known in the art, an array antenna includes a plurality of individually radiating elements. In some systems the individual radiating elements are coupled to a transmitter through a transmitter elementfor controlling the phase and amplitude of thetransmit ted signal. Similarly,the individual radiating elements are coupled to a receiverthrough a receiver element, for controlling the phase and amplitude of the received signal. In other systemsthe individual 80 radiating elements are coupled to both thetransmitter and receiverthrough a single element here referred to as a tranceiverfor controlling the phase and amplitude of both transmitted and received signals. The relative phase and amplitude of the microwave frequency signal passing between the plurality of radiating element and a corresponding plurality of individual transceiving elements are controlled to obtain a desired radiation pattern, The pattern obtained is a result of the combined action of all the individual transceiver and radiating elements. Many devices such as ferrite phase shifters are used to control the phase of the microwave frequency signal. Many of such phase shifters are reciprocal, that is, the phase shift of a signal passing through one of such devices is independent of the direction which the signal passes through. In some applications it is desirable to provide an active phase shifterto provide gain to a signal passing there through. Such a phase shifter is generally inherently non reciprocal. Thus, the use of an 100 nonreciprocal phase shifter in a transceiver would require the use of two of such phase shifters. A developing trend in phased array antenna systems is toward production of the transceiver elements in monolithic integrated circuitform. This is desired in 105 orderto reduce cost and sizefactors generally associated with phased array antenna systems and to provide phased array antennas adapted for certain applications where size and cost are critical such as airborne orspace based radar systems.

In accordance with the present invention, a trans ceiverfor coupling a microwave signal between an antenna element and a radarsystem, is provided.

Such a transceiver includes a plurality of switching means arranged to steer a microwave frequency signal provided bythe radar system through an nonreciprocal phase shifterto the phased array antenna during a transmit mode. and to steer a microwave frequency signal providedfromthe phased array antenna through the nonreciprocal 120 phase shifterto the radarsystem during a receive mode.The microwave frequency signal passes through the phase shifter in the same direction during both the transmit and receive mode. A set of control signals is fed to such switching means to control the 125 steering of the microwave frequency signal between the radar system and the phased array antenna. With such an arrangement, two signal paths through an active nonreciprocal phase shifter are provided. This arrangement reduces the cost and size of the trans- GB 2 165 397 A 1 ceiverelement by permittingthe use of a single active nonreciprocal phase shifter. Further, since each of the elements of the transceiver element may be realized as monolithic microwave integrated circuits this structure results in a compact transceiver element modular in form and less expensive to produce.

The invention will now be described by way of examplewith reference to the accompanying drawings,inwhich:

FIG. 1 is an overall block diagram of a radar system coupled to a phased array antenna system through a plurality of transceiver elements; FIG. 2 is a block diagram of one of the plurality of transceiver elements shown in Fig. 1; FIG. 3 is a block diagram of the transceiver element, utilizing a five port switch; FIG. 4 is a block diagram of a transceiver using a dual channel phase shifter; FIG. 5 is a block diagram of a 4-bit nonreciprocal phaseshifter; FIG. 6 is a diagrammatical view of a 180'phase shift increment stage of a 4-bit nonreciprocal phase shifter used in the one of thetransceiver elements; FIG. 6A is an isometric view of a bias line and output line insulated from each otherwith an air gap plated overlay; FIG. 6B is a cross sectional view of a pa rallel plate capacitorformed on the substrate,, FIG. 7 is a block diagram of the phase shifter stage depicted in Fig. 5; FIG. 8 is a detailed schematic diagram of the phase shifterstage depicted in Fig. 5; FIGS. 9A-91) are plan views of pairs of transmission lines providing electrical pathlength differences used to realize a 4-bit phase shifter.

FIG. 10 is a blockdiagram of a 4-bit dual channel phaseshifter; FIG. 11 is a detailed schematic of one stage of a reciprocal phase shifter; FIG. 12 is a diagrammatical view of the stage of a dual channel phase shifter depicted in Fig. 11; FIG. 13 is a detailed schematic of an alternate embodiment of a four bit nonreciprocal phase shifter; FIG. 14 is a block diagram of the nonreciprocal phase shifter of Fig. 13, including reciprocating switches; FIG. 15 is a detailed schematic diagram of a variable phase shifter utilizing a quadrature coupler.

FIG. 16 is a plan view of the variable phase shifter shown in Fig. 15; FIG. 17 is a block diagram of one stage of the n-bit variable phase shiftershown in Fig. 16; FIG. 18 is a diagrammatical view of a bidirectional three port switch; FIG. 19 is a schematic diagram of the bidirectional switch shown in Fig. 18; FIG. 20 is a schematic diagram of a preferred field effect transistor FET used in the bidirectional switch of Fig. 18.

Referring nowto FIG. 1, a phased array antenna 10 is coupledto a radarsystem 11 by a feed network 14, as shown. The phased array antenna 10 includes a plurality of, here n, identical transmitter/receiver (transceiver) elements 12a-1 2n, coupled to a like plurality of corresponding antenna elements 26a-26% 2 GB 2 165 397 A 2 as shown.Thefeed network 14, here a parallel feed network, provides a signal path fora microwave signal passing from the radarsystem 11 tothe phased array antenna 10fortransmission to a target (notshown), 5 and a signal path forreception of echo signaisfrom thetarget (notshown) to the radarsystem 11. A plurality of control buses 29a-29n, 19-aT9-n are provided from the radarsystem 11. Signals on such buses 29a-29n, 2-9ai9-n are used to control the transceiver elements 12a-1 2n of the phase arrayantenna 10. The microwave signal from the feed network 14 is coupled to each of the transceiver elements 12a-1 2n, as indicated bythe open arrows 13. The portion of microwave signal coupled to each one of the trans ceiver elements 12a-1 2n isthen coupled to the corresponding one of the antenna elements 26a-26n.

Similarly, a portion of the microwave echo signal from thetarget is coupled to each of the antenna elements 26a-26n, the corresponding transceiver elements 12a-1 2n, and thefeed network 14 as indicated by solid 85 arrows 15, for processing bythe radar system 11. The control signals on buses 29a-29n, 29ajf9-n during the transmit mode allowthe transceiver elements 26a-26n to produce collimated and directed beams of transmit ted microwave energy and control signals on such buses during the receive mode allowsuch transceiver elements 26a-26n to produce collimated and directed beams of received microwave energy.

Referring nowto FIG. 2, a representative one of the transceiver elements 12a-1 2n, heretransceiver ele ment 12i is shown coupled, via a transmission line 33i, to a portion of the feed netWork 14 and to an antenna element 26i, via a transmission line 35i, as shown.

Transceiver element 12i here includes 50 ohm trans mission lines 32a to 32h, fourtransmitter/receiver (TIR) switches 18a-1 8d, each having a common port 20a-20d, a pair of branch ports 19a-1 9d and 21 a-21 cl, and a control input 22a-22d. Each one of the control inputs 22a-22d is fed by a pair of control lines 29il, 195i, of buses 29i, 19k The T/R switches 18a-1 8d are here of 105 a type to be further explained in conjunction with Figs.

18-19. Suffice itto say here, however, that com plementary, binary or logical signals arefed to the control lines 29il, f9Jil, respectively, and such logical signals are usedto control the electrical coupling 110 between the common port and the branch ports. Thus, for example, using an exemplary one of the T/R switches 18a1 8d, hereTIR switch 18a, such switch 18a has common port 20a coupled to branch port 19a in responseto a first pair of logical states of control 115 signals fed to lines 29il, f9-il i.e. a logical 1 on line 29i, and a logical 0 on line ill and such common port 20a is coupled to branch port 21 a in response to the complementary pair of logical states of the control signals fed to line 29il, 2gil, i.e. a logical 0 on line 29i, 120 and a logical 1 on line 211. The common port20a of TIR switch 18a is coupled to the feed network 14, via thetransmission line 33i, as shown. Branch ports 19a and 21 a of TIR switch 18a are coupled to branch ports 19d and 21 b, via transmission lines 32a and 32h, respectively. Branch port 19b of TIR switch 18b is coupled to an irput of a transmitter amplifier 24, via the transmission line 32d. The transmitter amplifier 24 is hereformed on a semi-insulating substrata, here a gallium arsenide (GaAs) substrate. The output of 130 transmitter amplifier 24 is coupled to the branch port 19cof TIR switch 18c, via transmission line 32e.The common port 20c of TIR switch 18c is coupled to the antenna element 26i, via transmission line 35i. The branch port 21 c of T/R switch 18c is coupledto an input of the receiver amplifier28, via transmission line 32f. The receiver amplifier 28, here a low noise amplifier, is heref6rmed on a semi-insulating substrate (here GaAs).The output of the receiver amplifier 28 is coupled tothe branch port21 d ofTIR switch 18d,via transmission line 329. The common port20d of TIR switch 18d is coupledtothe inputof an active phase shifter40, here a nonreciprocal active phase shifter having a plurality of stages (notshown,to be described in detail in connection with Figs. 5,6 and7), viatransmission line 32b. Suffice itto say here, however, that each stage of the active phase shifter includes a field effect transistor suitably biased to provide gain to the radio frequency sig nal passing through it. Control signaisforthe active phase shifter 40 are fed thereto, via buses 29i2, :F9i2 of bus 29i. The output of the active phase shifter 40 is coupled to the common port 23b of T/R switch 18b, via transmission line32c.

Du ring a transmit mode, the transceiver element 12i couples a microwave frequency signal from the radar system 11 to the antenna element 26i. Atransmit signal path for coupling a signal from the radar system 11, via feed network 14, to the antenna element 26i is depicted in FIG. 2 by an open arrow 13, as shown. In thetransmit mode, the control signals on lines 2gil, Hil are used to couple each one of the common ports 20a-20d to the corresponding branch ports 19a-1 9d of the respective TIR switches 18a-11 8d. Thus a portion of the microwave signal is coupled from the radar system 11 to the input of the active phase shifter40. The active phase sh ifter 40 is here used to vary the phase shift of the applied microwave frequency signal by a predetermined amount in accordance with control signals on buses 29i2j9i2 which are fed to a control input 42, of the active phase shifter40. The microwave frequency phase shifted sig nai is then coupled to the inputofthe transmitter amplifier 24. The signal atthe output of the transmitter amplifier 24 is coupled to the antenna element 26i.

During a receive mode, a portion of a received echo signal is coupled from the antenna element26i to the radarsystem 1 LA receive signal path for coupling the received echo signal from the antenna element 26i to the radar system 11 is depicted in FIG. 2 by solid arrows 15, as shown. During the receive mode the complementary logical states of the control signals previously on lines 29i,-:Y911 are nowfed to lines 29il, 29iI, and such signals are used to couple each one of the common ports 20a-20d to the branch ports 21 a-21 d of the respective T/R switches 18a-18d. Thus the echo signal is coupled from the antenna element 26i to the receiver amplifier28. The signal atthe output of the receiver amplifier 28 is coupled to the input of the active phase shifter element 40. The signal passing through the phase shifter is again phase shifted in accordancewith the control signaisfed on buses 29i2-29i2. The phase shifted signal produced at the output of the active phase shifter element 40 is then coupled to the radar system 11, via the feed 3 network 14. Thus it is noted thatthe microwave frequency signal is coupled through the active phase shifter40 in the same direction for both the transmit mode and the received mode. Thus, referring again to FIG. 1 in a similar manner, each of the plurality of transceiver elements 12a-1 2n are used to couple a portion of a microwave signal between the radar system 11, via thefeed network 14 and the plurality of antenna elements 26a-26n,to produce in combination a collimated and directed beam (not shown) during thetransmit mode and the receive mode.

Referring nowto FIG. 3 an alternative the embodi ment of a transceiver element 12i'suitablefor use in the phased array antenna 10 of FIG. 1 is shown coupled to a portion of thefeed network 14 and the 80 antenna element 26i. Transceiver element 12i'here includes a five port switch 310, the active phase shifter 40, thetransmitter amplifier 24, the receiver amplifier 28, and thethree portTIR switch 18c, as shown. The five port switch 310 isformed on a substrate, (not 85 shown) here semi-insulating gallium arsenide (GaAs) having a ground plane (not shown) here plated gold formed on the bottom surface of the substrate.

Formed in active regions on portions of thetop surface of the semi-insulating substrate are FET's 50a-50d 90 here GaAs FETs, each having gate electrodes 52a-52d (Fig. 3), a drain electrode 54a-54d and a source electrode 56a-56d. The gate electrodes 52a, 52d of FET's 50a, 50d, are connected to control fine 29il, and the gate electrodes 52b, 52c of FET's 50b, 50c are connected to control line!9-il, as shown. The FET's are here connected in a common (grounded) sou rce configuration. The T/R switch 310 fu rther incl udes transmission lines 60a-60f. Each transmission line 60a-60f has an electrical length, corresponding to one 100 quarter wavelength (AJ4), where Ac is the wavelength of the corresponding nominal or operating center band frequency (f,,) of the circuit. The feed network 14 is electrically connected to a first end 60a, of Ac/4 transmission line 60a and a first end 60f, of Ac/4 transmission line 60a and a first end of 60f, of Ac/4 transmission line 60f, via transmission line 33i. The drain electrode 54c of FET 50c is electrically connected to a second end 60a2 of Ac/4transmission line 60a. A first end 60b, of Ac/4 transmission line 60b is electrical ly connected to the second end 60a2 of transmission line 60a and drain electrode 54c. A second end 60b2 Of AJ4transmission line 60b is electrically connected to the input port of the active phase shifter40, via transmission line 32b and to a first end 60d, of A.14 115 transmission line 60d. The second end 60c12 Of transmission line 50d is electrically connected to the output of the receiver amplifier 28 and to the drain electrode 54d of FET 50d. A second end 60f2 of AJ4 transmission line 60f is electrically connected to a first 120 and 60e, of Ac/4 transmission line 60e, and drain electrode 54a of FET50a. Asecond end 60e2 of AJ4 transmission line 60e is coupled tothe output of the active phaseshifter40, via transmission line 32c and to a firstend 60c, of A,14 transmission line 60c. A 125 second end 60c2of Ac/4 transmission line 60c is coupled tothe input of thetransmitter amplifier24and tothe drain electrode 54b of FET50b. The connections of transmitter amplifier24 and receiver amplifier28to T/R switch 18d are the same, as explained above in GB 2 165 397 A 3 conjunction with FIG. 2.

During the transmit mode, asshown bythe open arrows 13 a logical control signal on line 2911 of bus 29i isfed to the gate electrodes 52a, 52d of FETs 50a, 50d and the complement of such logical control signal is fed (via line:9il of busY9-i) to gates 52b, 52c of FETs 50b, 50c. In response to such signals FET's 50a, 50d are placed in a conducting state and FET's 50b, 50c are placed in a nonconducting state. The AJ4transmis- sion lines 60d, 60e and 60f have ends 60c12, 60e, and 60f2 electrically connected to FET's 50a and 50b, as previously described. When FET's 50a, 50d are placed in a conducting state, a shortcircuit (low impedance path to ground designated by(g) is produced atthe ends 60c12,60e, and 60f2 of transmission lines 60d-60f coupled to the FET's 50a, 50d. One quarter wavelength therefrom (atthe second end 60c11, 60e2, and 60f, of each transmission line 60d-60f) the short circuits at ends 60d2,60el, 60f2 appear as open circuits (high impedance paths to ground designated by @) at ends 60d,, 60e2,60fl,to a microwave frequency signal having a wavelength substantially equal to the wavelength ofthe corresponding nominal or centerbandfrequency of operation, forthe transceiver. Thus, no signal path is provided during thetransmit mode through line 60f and the transmitted energy passes through lines 60a and 60b. Further because end 60d, appears as an open circuito the transmitted energy passesfrom line 60b through line 32b,through the phase shifter40 and through line 32c. Since end 60e2 appears as an open circuit@the transmitted, and now phase shifted energy passesthrough line 60c, transmitteramplifier 24, TIR switch 18c and to the antenna 26i, as previously described in conjunction with FIG. 2.

During the receive mode as shown bythe closed arrows 15, the control signals on lines 29i,,19-il are switched (or complemented) in logic state placing FET's 50a and 50d in a nonconducting state, and placing FET's 50b and 50c in a conducting state. The ends 60a2,60bl, and 60c2 of the AJ4transmission lines 60a, 60b and 60c which are coupled to the drain electrodes 54b and 54c of FET's 50b and 50d are thus coupled to ground and the other ends 60al, 601J2, and 60c, of thetransmission lines 60a, 60b, and 60c present impedances corresponding to open circuits. Thus, a received microwave signal from antenna element 26i is coupled tothe output of the receiver amplifier 28 as explained in conjunction with FIG. 2. The received signal is then coupled through transmi.s sion line 60d to the active phase shifter element40. The signal on the output of the active phase shifter40 is thus coupled to the radar system 10 through transmission lines 60e and 60f.

Referring nowto Fig. 4, an alternative embodiment of a transceiver, here transceiver 12V' suitablefor use in the phased array antenna 10 of FIG. 1 is shown coupled to a portion of the feed network 14, via transmission line 33i and to the antenna element 26i, via transmission line 35i, as shown. Transceiver element 12i--- includes T/R switches 18a and 18c, transmitter amplifier 24, receiver amplifier 28. Here, however, a dual channel active phase shifter44is provided. Dual channel active phase shifter44 has a plurality of cascade interconnected phase shifter stages here 44a-44d of a type to be further described in 4 detail in conjunction with Figs. 10-12. The T/R switch 18a has common port 20a coupled to the feed network 14 via transmission line 33i. Branch ports 19a and 21 a of T/R switch 18a are coupled to the input 47a of a first channel 47 and the output 49b of a second channel 49 70 of dual channel phase shifter 44, respectively, as indicated. The output 47b of the firstchannel 47 is coupled to the input of the transmitter amplifier 24, via transmission line 32b. The output of the receiver amplifier 28 is coupled to the input 49a of the second channel 49, via transmission line 32e. The connection of the transceiver 12i" to antenna element 26i (FIG. 1) is as previously explained.

During the transmit mode, as shown by the open arrows 13, in response to complementary control signals on lines 2gil, Sil a microwave signal fed to common port 20a from the radar system 11 is coupled to branch port 1 ga. Such signal from branch port 19a is coupled to the input 47a of the dual channel phase shifter44. The signal is shifted in phase and coupled to 85 the transmitter amplifier 24 and to the antenna 26, as previously described. During a receive mode, as shown bythe closed arrows 15, in responseto the complements of the previous control signals on lines 29il,Y9-i the microwave signal fed tothe common port 20cfrom antenna 26i is coupled to the branch port 21 c and thisto the receiver amplifier 28.The signal atthe output of the receiver amplifier 28 isfed tothe input 49a of the phase shifter44.The signal shifted in phase isthen fed totheTIR switch 18a to the radar system 11, as previously described.

Referring nowto FIG. 5, a single channel digitally controlled phase shifter40 suitablefor use in trans ceiver element 1 2i (Fig. 2) and transceiver element 12V (Fig. 3) is shown to include a plurality of cascade interconnected stages40a-40d with like parts of each stage being designated by the same numeral. An exemplary one of such stages40a-40d, here stage 40a, is discussed in detail in conjunction with FIGS. 6-8.

Referring nowto FIG. 6, the phase shifter stage 40a is formed on a substrate 41 here GaAs having a ground plane 43, as shown. Referring also to FIGS. 7,8 the phase shifter stage 40a includes a microwavetrans mission line 512, here having an impedance of 50 ohms, coupled to an input impedance matching circuit 513. Transmission line 512 is herefed by a microwave frequencysignal from transmission line 32b (Fig. 2).

Input impedance matching circuit 513 is here used to match the input impedance of the phase shifter stage 40ato the characteristic impedance of the transmis sion line 512. The input matching circuit 513, here includes a firsttransmission line section 514, having a reactancewhich is primarily inductive, coupled in shurittothe inputtransmission linesection 512, via a bottom plate 526cof a capacitor526. Bottom plate 526c of capacitor 526 is coupled to one end of the shunt mounted transmission line section 514. The upper plate 518a of a second series connected capacitor 518 is coupled to line 516 andthe bottom plate of 518 is coupledto ground by a via hole 518b,as 125 shown. Ground pad 522 is coupled to ground by a via hole connecticn 522a. As shown in Fig. 6B, capacitor 526 is formed on the top surface of the su bstrate 41 here includes atop plate 526a which is coupled via an air bridge 526d to the strip conductor portion of a 130 GB 2 165 397 A 4 transmission line 528. Aligned underthistop plate is a bottom plate 526c of evaporated gold formed on the substrate41.Thetop plate 526a and bottom plated 526care separated by a 5000 Angstrom (A) layer526b of silicon nitride (Si3N4). The bottom plate 526chas a finger526e (Fig. 6) which is usedto connectthe second circuitelement, here transmission line section 514,tothe capacitor526. The connection is provided bya metalto metal contactwhich couplestothe bottom plate 526c. A second transmission line section 516, herehaving a reactancewhich is primarily inductive iscoupledto shunt between capacitors 518 and 526. The connection of capacitor518to inductor section 516 providesthe biasfeed 520forthe gate electrode. The input matching circuit 513 further includes the third transmission linesection 528 here also having a reactancewhich is primarily inductive, connected between the junction of capacitor 526 with shunt mounted transmission linesection 516and a common inputjunction 532. The phase shifter stage 40a further includes a FETswitch 530 having a dual gate FET, 530a-530b, as shown. FET's 530a and 530b include first gate electrodes 532a-532b coupled to the common junction 532, second gate electrodes 534a, 534b, separate drain electrodes 536a, 536b and separate source electrodes 538a, 538b. FETs 530a, 530b are here connected in a common (grounded) source configuration. FET530a, 530b are fabricated such thatthe gains and phases provided by each FET to signaisfed to the gate electrode and coupled tothe drain electrode are substantially equal. In other words, IS21 1,, the fraction of power coupled to the drain electrode 536a or530afrom a signal on gate electrode 532a substantially equals, IS21 IbAhe fraction of power available atthe drain electrode 536b of FET 530b from an incident input signal provided signal gate electrode 532b of FET530b. Similarly, tP S211a = qJ. S21 1b that is, the phases of the instantaneous power delivered to each drain electrode of FET530a, 530b are substantially equal. Control gate electrodes 534a, 534b are fed control signals on lines 29i2,,,!9i2a (Fig. 2). These control signals are used to control the coupling of an input signal fed to the gate electrode 532a, 532b to the corresponding drains 536a, 536b of FET's 530a, 530b. High frequency components in the signals on control lines 29i2a, i9i2a are shorted to ground, via capacitors 527a, 527b. The drain electrodes 536a, 536b are electrically connected to identical impedance matching circuits 545a-545b, as shown. The matching circuit 545a (Fig. 8), here includes a firsttransmission line section 548a coupled in series between the drain electrode 536a and a coupling capacitor 552a. A second transmission line section 549a is coupled in shuntwith thejunction of the first transmission line section 548a, the bottom plate of capacitor 552a, and an upper plate of a dc blocking capacitor544. The bottom plate ofthe dc blocking capacitor 544 is connected to ground by a via hole connection 544a (Fig. 6). The impedance matching circuit 545b is formed in a similar manner on the substrate 41 (Fig. 6) forthe drain electrode 536b. The impedance matching circuit 545b includes a transmission line section 548b, a coupling capacitor 552b, and a second transmission line section 549b, coupled to the drain electrode 536b in a similar manner asthe corresponding elements of GB 2 165 397 A 5 imped ance matching circuit545a.The common con nection of transmission line sections 549a-549b and the dc blocking capacitor 544 provides the bias feed 546for drain electrodes 536a, 536b. As shown in Fig.

6A, the bias feed 542 here is insulated from the transmission line section 548b by a conventional air gap plated overlay. In general, such overlays are here used in all embodiments to insulate such crossing signal paths. The upper plates of coupling capacitors 552a-552b of the impedance matching circuits 545a, 545b respectively, are integrally formed with the strip conductor portion of transmission lines 554a and 553, r espectively. Transmission line 554a has an electrical length which provides a phase shift (p, + A4)a to an input signal coupled thereto and transmission line 553 80 has an electrical length which provides a phase shift of 1), to an input signal coupled thereto. Such pair of transmission lines 554a, 553 as shown in FIG. 9a and described in more detail hereinafter provides one path having an unique phase shift increment Aq),. Each second end of transmission line section 554a, 553 is coupled to a corresponding input port 565,567 of a conventional three port coupler, which couples power from two input ports and provides the coupled power to an output port, via branch arms 564,566. Such a coupler is described in an article entitled "GaAs Monolithic Lange and Wilkinson Couplers" by Raymond C. Waterman Jr. et al IEEE Transactions on Electron Devices, Vol. ED-28, No. 2, February 1981.

The output of the three port coupler is electrically connected to an output port 570. Capacitors 518,526, 544,552a, 552b 527a and 527b are here formed in a similar manner, as explained for capacitor526.

In operation, an input signal fed to transmission line 512 is coupled to each gate electrode 532a, 532b. Such 100 signal is coupled to one of the drain electrodes 536a, 536b selectively in accordance with the control signals fed on lines 29i2a, f9i2a to the control gate electrodes 534a, 534b..If the input signal in response to such control signals on lines29i2,,,19i2,, is coupled to drain electrode 536a, the phase of such signal is shifted by an amount (p, + A1)a through transmission line 554a.

Conversely, the electrical path from drain electrode 536b tothe coupler 560 provides a pathlength corresponding to a phase shift of 1)1. Thus, if in 110 response to the control signals on lines 29i2a, f9i2., the input signal is coupled to drain electrode 536b, the phase of such signal atthe output 570 is shifted by an amount of (p, through transmission line 553. Thus, a phase shift of an input signal of (p, or 4), + A(Pa atthe 115 output 570 is selected in response.to control signals on lines 29i2wY9i2a. A plurality of such stages are cascade interconnected to form the phase shifter40 (Fig. 5).

Each stage has two paths which correspond to phase shifts of an input signal of 1), through one path an 120 amount 1), + A(pi through the second path where i is the numberof the stage. For, four cascade intercon nected stages, the phase shift A1)i for each stage is here A(pa = 180', A1)b = 90', A1)c = 4Wand A1)d = 22.5'.

Referring again to FIG. 5, with like parts in each 125 stage being designated bythe same numeral, the active nonreciprocal phase shifter 40 used to produce an output signal at port 570d having a predetermined phase shift relativeto an input signal on transmission line 512 includes four cascaded interconnected phase 130 shifter stages 40a-40d, as shown. Each phase shifter stage 40a-40d realized in accordance with Figs. 6-8, selectively provides a unique phase shiftto an input signal Of A(Pa = 180', A(Pb = 90', A1)c = 45'and A1)d = 22.50, respectively. Each phase shift stage includes a unique length of triansmission line between output matching circuit 545a and the three port coupler 560. Each length of transmission line, in conjunction with the length of transmission line 553, provides each stage with a unique pathlength difference corresponding to the unique phase shift. In response to control signals on lines 29i2,-29i2d, and- 29i2a29i2d selective combinations of phase shift increments of Wor 180', Wor90', WorWand Wor 22.5'are provided by phase shifter stages 40a-40d, respectively of control signals fed by lines 296 to 29i2d and29i2a tOY9i2d are represented byAto D and7-toU,- respectively. The phase shift 1) of an input signal through phase shifter 40 may be represented bythe following logical equation as:

= E(A(Sh i +A4..) + X 1)) + M 411 +A Sh b) + V(SW) + (C( 55 +A, 0 C)+ -6 (01)) +(D( 4,1 +A0d) + fi(Sh 1)3.

The phase shifter40, thus, is used to varythe phase of a signal fed to transmission line 512 of stage 40a from 0 to 360' in here 22.5'phase shift increments.

Referring nowto FIGS. 9A-91D transmission line sections 553 and 554a-554d used to provide unique incremental phase shifts for stages 40c-40d respectively, of the phase shifter40b shown in FIG. 5, have like parts being designated by the same numeral. The transmission lines 553 and 554a-554d are coupled to the input ports 565,567 of the three port coupler 560, having a thin film load resistor 562 and branch arms 564,566, and to a portion of the impedance matching networks 545a-545b, as shown. Thetransmission lines 554a-554d are formed on the semi- insulating substrate 41 by strip conductors 555a-555d and 557, respectively, and the 9 round plane 43, which is separated by a dielectric, here the semi-insulating su bstrate 41. Strip conductors 555a-555d and 557 are designed to provide the corresponding transmission lines 554a-554d and 553 each with a 50 ohm characteristic impedance. The transmission lines 554a-554d each have an electrical length equal to a corresponding precise fractional wavelength A,12% with respectto transmission line section 553, where Ac isthe wavelength of the nominal or centerband operating frequency (fc) forthe active phase shifter n is the total number of stages. Thus, transmission line section 554a has a pathiength (A(pa) equal to hJ2 with respect to transmission line section 553. In a similar manner, the pathlengthsfor segments 554b-554d with respect to transmission line 553 are Ac/4, AJ8, and AJ1 6. Thus, the transmission lines 554a-554d, with respeetto transmission line section 553, here represent pathlength differences corresponding to a phase shift of an applied signal with respectto the phase of such signal of 180', 90', Wand 22.5', respectively.

Referring nowto FIG. 10, a dual channel phase shifter44 having channels 47 and 49 which is suitable for use in the transceiver 12i--- shown in FIG. 4 includes four one bit phase shifter stages (P. S. Stages) 44a-44d cascade interconnected together, as shown. The dual channel phase shifter stages 44a-44d are here identical exceptforthe pathiength differences (phase shift 6 GB 2 165 397 A 6 increment) (A(pi) forming the phase shift networks of each stage. Each channel of the dual channel phase shifter provides one of two signal paths, such path being selected in responseto control signals fed on lines 29i2A9i2d and 19i2a-2d. Such paths provide either 70 a phase shift of (p, or a phase shift of q), + A(piwhere i is the numberof the stage. The phase shift increment (Aoi) foreach of the fourstages 44a-44d shown in FIG.

are, = 180',A(Pb = 90', 90', A4)c = 4Wand A0d = 22.5'forstages 44a-44d, respectively as explained in 75 conjunction with Figs. 9a-9d.

Referring nowto FIG. 11, an exemplary one of such phase shifter stages, here phase shifterstage 44a is shown. The phase shifter stage 44a includes FETs 530a-530d each having a pair of gate electrodes 80 532a-532d, and 534a-534d, a drain electrode 536a 536d, and a common source electrode 538. FET's 530a-530d are here realized as a double pole double throw FETswitch 530 of a type disclosed in U.S. Patent No. 4,313,126filed May 21,1979, and assigned to the 85 assignee of this invention. Each of the FET's 530a-530d are here connected in a common (grounded) source configuration, as shown. Each FET 530a-530d is formed on the substrate 41 within close proximity to the other FET's 530a-530d, as shown. FETs 530a-530d 90 are fabricated such that gains and phases provided to an inputsig nal are substantial ly equal, as explained in conjunction with Figs. 6-7.

The first phase shifter channel 47 includes a microwave transmission line 512, here coupled to the transceiver 12i--- (Fig. 4), via transmission line 32a providing a signal inputforthe phase shifter stage 44a. The microwave transmission line 512 is electrical ly connected to an impedance matching circuit 513a previously described in conjunction with FIGS. 6-8.

Matching circuit 513 is electrically connected to the common inputjunction 532. Inputjunction 532 is coupled to input gate electrodes 532a, 532b of FET's 530a, 530b, respectively. Signaisfed on lines 29i2,,, f9i2. fromthe radarsystem 11 (Fig. 1) are fed to the second gate electrodes 534a, 534b for controlling the conduction of an input signal on input gate electrodes 532a, 532b to the corresponding drain electrodes 536a, 536b of FET 530a, 530b, respectively. High frequency signal components on control signals fed on lines 29i 2 a,19i2. are shorted to ground by capacitors 527a, 527b. An input signal fed equallyto input gate electrodes 532a, 532b is selectively cou pled, to the corresponding drain electrode 536a, 536b, in accordancewith the control signals on lines 29i2., 115 :Z9i2.fedtothe control gate electrodes 534a, 534b. The drain electrode 536a is electrically connected to an impedance matching network545a as described in conjunction with FIGS. 5-7. The drain electrode 536b is similarly electrically connected to the impedance 120 matching network 545b, as shown. The impedance matching network 545a is coupled here, the micro wave transmission line 554a. In a similar manner, the impedance matching network545b is coupled to the microwave transmission line 553a. Each second end of transmission lines 553a and 554a is coupled to the pairof input pcAs 565,567 of the conventional three portcoupler560.

The second channel 49 of digital phase shifter stage 44a includes microwave transmission line 512'cou- pled to transceiver 12i--- (FIG. 4) via transmission line 32g (Fig. 2) for providing the signal input for channel 49. The microwave transmission line 512'is electrically connected to an impedance matching circuit 51Xas previously disclosed in conjunction with FIGS. 5-7. A second matching circuit 513'is electrically connected to a common junction 532'. Common junction 532'is electrically connected to input gate electrodes 532c, 532d of FET's 530c, 530d. Control gates 534c, 534d of FET 530c, 530d are electrical ly connected to gate electrode pads 524 and 527, respectively. The control gates 534c, 534d are fed sig nals on lines 29i2a, Mi2a from the radar system 11 (Fig. 1) for controlling conduction of an input signal on input gate electrodes 532c, 532d to the drain electrodes 536cm 536d of FET's 530a, 530b, respectively. Drain electrodes 536c-536d are electrically connected to impedance matching networks 545c-545d as disclosed in conjunction with FIGS. 6-8. Transmission lines 553'and 554', are coupled between the impedance matching networks 545c-545d and the three port coupler 560'. Thethree port coupler 560'is electrically connected to output port570'.

The total pathiength difference of the connection of drain electrode 536a to thethree port coupler 560, for channel 47 is then selected to provide a corresponding phase shift equal to 41 + A,,, as explained in conjunction with FIGS. 9a-9d. Thetotal pathlength difference of the connection of drain electrode 536b to thethree port coupler for channel 47 is selected to provide a corresponding phase shift equal to (p,. Thus, the phase of a signal applied to the gate electrodes 532a,532b is shifted by an amount (p, + Aq), or (p, selectively in accordance with control signals fedto control gate electrodes 534a, 534b. In the same manner, transmission lines 55X, 554a'provide pathlengths to channel 49 between drains 536c, 536d of (p, +A(P,Or(P1.

Referring again to Fig. 10, the dual channel phase shifter44 having channels 47 and 49 has stages 44a-44d, each stage providing a unique phase shiftto an applied signal. Each channel provides selective combinations of phase shift increments A0a = 180', A0b = 90', Aq)c = 45', and A0d = 22.5' in response to control signals on lines 29i2e,-29i2d,29i2.-29i2d.

Referring nowto FIG. 12, the phase shifterstage 44a is shown, formed on a semi-insulating substrate 41 having a ground plane 43 on one side thereof, as shown. A lowinductance ground connection 537 is here made through the source electrode region 538. Parallel plate capacitors such.as 526 areformed on the substrate 41, as previously described in conjunction with FIG. 6B. Crossing signal paths are insulated one from another by conventional air gap plated overlays as described in conjunction with FIG. 6A.

Referring alsoto FIG. 5,the netoverall gain for each four bit phase shifter40 and 44'is approximately 8 decibels (db) or approximately 2 db per stage. Each stage contributes 3 db of loss from splitting ofthe input signal and another 3 db of loss due to power recombining atthethree port coupler 560. The total losses due to parasitic losses and the matching networks are lessthan 1 db. Allowing forsubstantial mismatch, a gain &approximately 8 db generally is realizablefrom a dual gate FET, operating atX-band, 7 GB 2 165 397 A 7 1 35 for example. Thus, a net gain of approximately 2db per stage orapproximately 8 db forthe phase shifters of FIG. 9 and FIG. 12 is realized. Since onlyfour FETs, one perstage, at any given time are operating for each phase shifter, 40,44the d.c. power consumption will be fourtimesthat for one FET.

Now referring to FIG. 13, an alternative embodiment for a four bit digitally controlled phase shifter40' suitable for use in transceivers 12i and 12V(Fig. 2 and Fig. 3) includes a first stage 4Whaving a single pole fourthrow (SP4T) FET switch 1330 and a second stage 40Whaving SP4T FET switch 1370, as shown. The SP4T FET switches 1330 and 1370 are here of a type disclosed in the above mentioned U.S. Patent No.

4,313,126. Each stage 40a', 40Wis formed on a substrate (notshown), having a ground plane (not shown).

The firststage 40a'of thefour bit digital phase shifter40'further includes FET's 1330a-1330d, as shown. FET's 1330a-1330d are fabricated such that gains and phases provided to an inputsignal are substantially equal, as explained in conjunction with Fig. 5-7. Each FET 1330a-1 330d, includes a input gate 1332a-1332d, a control gate 1334a-1334d, drain elec trodes 1336a-1 336d and a source region 1338. FET's 1330a-1330d are hereconnected in a common (grounded) source configuration. A low inductance ground connection is here madefrom the source electrode 1338to the ground plane 43 (notshown) by a conventional via hole connection.

A microwave transmission line 512, here having an impedance of 50 ohms is coupled to an impedance matching circuit 513, as previously explained in conjunction with FIGS. 4-6. The impedance matching circuit is coupled to input gate electrodes 1332a- 100 1332d. The drains 1336a-1 336d are electrically con nected to identical impedance matching networks 545a-545d of a type previously described in conjunc tionwith FIG. 8. Impedance matching networks 545a-545d are each coupled to a transmission line 105 1320 having a characteristic impedance Z, here 50 ohms. Transmission line 1320 is terminated at one end in a resistor 1322, here having a value equal to 50 ohms, the characteristic impedance of the transmis sion line 1320. The resistor 1322 is coupled in shunt 110 between thetransmission line 1320 and ground. Drain electrode 1336d is electrically connected to the end of transmission line 1320 through the impedance to matching network 545d. Drain 1336c of FET 1330c is electrically connected to transmission line 1320, 115 through the matching network 545c defining a section of transmission line 1326, drain electrode 1336b of FET 1330b is electrically connected to transmission line 1320through the matching network 545b defining a section of transmission line 1324, and drain electrode 120 1336a of FET 1330a is electrica 1 ly co n nected to tra nsm issio n 1 i n e 1320, th ro u g h th e m atch i rig n etwo rk 545a, defining a section of transmission line 1322.

Here, all the transmission line sections 1322-1326 havethe same electrical length and thus each section 125 shifts the phase of an applied signal by an equal amount. The total phase shift of an output signal with respectto the phase of the input signal fedthrough transmission line 512 is the sum of the phase shifts provided by each of the equal electrical length 130 transmission line sections 1322,1324 a"nd'l 326 of which the output signal passes through from a selected one of the drain electrodes 1336a-1 336d to the output port 1331.

1 n operation, an input sig nal is cou pled or decoupled between the gate electrode 1332a-1 332d and the corresponding drain electrode 1332a-1 332d and the corresponding drain electrode 1336a-1 336d selectively in accordance with control sig nals fed to control gate electrodes 1334a-1 334d on lines 29i2.-29!2d provided by suitable modification of the radar system 11 (Fig. 1). Sig nals on control li nes 29iW29i2d are here logical control signals. One of such signals on lines 29i2,729i2d is selected to be in an "on" state, whilethe remaining ones of such signals on lines 29i2,-29i2d are placed in an--- ofF' state,thus placing only one FETof the FETs 1330a-1 330d, in a conductive state and the remaining ones of such FET's 1330a-1330d, in a non-conductive state. Similarlythe output signal from -85 the firststage is coupled or decoupled between the gate electrodes 1372a-1372d and the corresponding drain electrode 1376a-1376d selectively in responseto control signaisfed to control gate electrodes 1374a1374d, via lines 29iW29i2h, as shown.

In response to a control signal fed to one of the control gate electrodes 1334a-1 334d the corresponding one of the FET's 1330a-1 330d is placed in a conducting state, coupling the input signal on the input gate electrode of such FET, to the corresponding drain electrode of such FET. The remaining FET's of the FET's 1330a-1330d are held in a nonconducting state by control signals fed to remaining ones of the control gates 1334a-1334d. Thus, a signal coupled to the transmission line 132 from drain electrode 1336a will have a net phase shift of 3 Aep with respectto phase of an input signal on drain electrode 1336a, because the signal coupledfrom drain electrode 1336a will pass througRthe-three phase shiftsections 1322,1324and 1326of transmission line 1320 before arriving atthe outputport 1330. In a like mannera signal appliedfomthe drain electrode 1336b to transmission,Iine 1320 will have a net phase of 2 A(p, a signal applied from drain electrode 1331 c to transmission line 1320 will have an incremental phase shift of A4), and a signal applied from drain electrode 1336d to transmission line 1320 will have an incremental phase shift of G'With respectthe signal on drain electrode 1336d. Thus by selective application of control sig nals fed to control gates 1334a-1 334d an incremental phase shift of 3 A(p, 2 A(pr A(p, of Wmay be obtained. By selecting the electrical length of each incremental phase shift (Aq)) of the first stage equal to be 225', a total phase shift of up to 67.Wis provided bythe first stage. The phase shift provided bythe matching network 545a-545d is the same for each drain electrode matching circuit and thus does not affect the differential phase shift produced.

The output of the first stdge 4Wis electrically connectedtothe ' input of the second stage 40W, as shown. The second stage 40Wof the four bit digital phase 40'is identical to the first stage 40a'exceptfor the electrical length of the transmission line 1320'. In a like manner, as discussed forthe first stage 40a', the second stage of the four bit digital phase shifter 40' has drain electrodes, here 1376a-1 376d electrically 8 GB 2 165 397 A 8 connected to a portion of a transmission line 1320'.

The incremental phase shift of transmission line 1320' is heresetto 90'. Thus,a total phase shift of 27Wat the output 133Vis obtainable in the second stage 40W.

This in combination with thefirststage 4Whaving a total available phase shift of 67.5'proV-tdes the four bit digital phase shifter40', having a capability of providing a 360'phase shift, in 22.5' increments.

Now referring to FIG. 14, a digitally controlled phase shifter section 50 suitable for use in thetransceiver 12i 75 (Fig. 2), by replacing TIR switches 18b, 18d and phase shifter40, and fortransceiver 12i--- (Fig. 4) by replacing phase shifter44, includes the single channel phase shifter40'of FIG. 13, and FET's 141 Oa-141 Od. Each FET 141 Oa-141 Od has a signal gate electrode 1412a-1 412d, 80 a control gate electrode 1414a-1 414d, drain electrodes 1416a-1 416d, and source electrodes 1418a-1 418d, as shown. FET's 141 Oa 141 Od are connected in a common (grounded) source configuration. The signal gate electrodes 1412a, 1412b of FET's 141 Oa, 141 Ob are here coupled to thetransmission lines 32a and 32g of the tranceiver 12i (FIG. 2) respectively, th rough a pair of impedance matching circuits 513, as described in conjunction with FIG. 5. Each drain electrode 1416a, 1416b is coupled to the phase shifter40'via transmission line 1420. The outputof the phase shifter40'is coupled to the input gate electrodes 1412c, 1412dof FET's 141 Oc, 141 Od, respectively, via transmission line 1422 and impedance matching circuit 513. The drain electrodes 1416c, 1416d are coupled to transmission lines 32h and 32d, respectively, of thetransceiver 1 2i (FIG. 2). In operation, one of a pair of input signalsfed to the signal gate electrodes 1412a, 1412b of input channels 1430,1432 is selectively coupled to the corresponding drain electrodes 1416a, 1416b in re sponseto signaisfed to control gate electrodes 1414a, 1414b on lines 29il,19-il. Such selectively coupled signal isfedto the phase shifter 40'and the phase of such signal is shifted in responseto control signals 29i2.-29i2h as previously described. One of the pairs of 105 outputchannels 1434,1436 is selected, by signals on lines 29il, f911 fed to control gates 1414c, 1414d. The phase shifted signal, is coupledto the input gate electrodes 1412c, 1412d of FETs 141 0c, 141 Od. The phase shifted signal fedto each of the input gate electrodes 1412c, 1412d is coupled to one of the drain electrodes 1416c, 1416d selectively in response to control signals on lines 29i,,:9-il fed to control gates 1414c, 1414d, respectively, as previously explained.

The signal on the selected one of the drain electrodes 115 1416c, 1416d is coupled to transmission lines 32h during the receive mode or 32d of thetransceiver 12i (FIG. 2) during the transmit mode.

Assuming one milliwatt of power consumption per FET, the power consumption of the phase shifter 50 is four milliwatts since four FET's are conducting atthe same time. Two FETs of the four reciprocating switches conductand one FETin each of stages 40a' and 40b'(FIG. 13) conducts, during operation of the phase shifter. The net overall-gain forthe phase shifter section 50 is approximately 4 db. This assumes a 6 db loss due to input signal division into the four channels, FET's 1330a-1 330d of phase shifterstage 40a'(FIG. 13) and 6 db of loss dueto input signal division forstage 40b1FIG. 13). In addition,there is a loss of 3 db in each stage (40a', 40W) attributable to the terminating resistors 1322fortransmission lines 1320 and 1320' (Fig. 13), and there is a loss of 1 db per stage due to parasiticsand the matching circuits. These losses are partially compensated for by a minimum of 8 db gain for each FET resulting in a net loss of at most2 db per stage. Moreover, the FET switches 141 Oa-1 41 Od contribute 16 db of gain (8 db per switch, two switches active at one time). This gain is reduced, however, by 3 db due to signal division into the two channels of FET's 141 Oa, 141 Od and 1 db due to parasitics and the matching circuits-Thus, the net gain forthe phase shifter 50 is approximately 4 db.

Referring nowto FIG. 15, an alternative embodiment of an phase shifter40--suitablefor use in transceiver 1 2i (Fig. 2) and 12V(Fig. 3), includes a first phase shifterstage 40a% a second phase shifterstage 40b-, and a third phase shifterstage 40c" cascade interconnected, as shown. Each phase shifter stage 40a-, 40W' and 40c" is similarto the digitally controlled phase shifterstage 40a described in conjunction with FIGS. 6-8. Phase shifter stage 40a--- is here used, however,to provide a variable continuous phase shift between O'and 90'. Phase shifting stage 40Wis used to produce a phaseshift of (p = Wora phase shift of d) = 90', and phase shifter stage 40c--- is used to produce a phase shift of q) = Wor g) = 1BO'. The cascade interconnection of phase shifter stages 40a-, 40C and 40c--- provides the phase shifter40---which is capable of varying the phase of an input signal continuously overthe range of Wto 360'.

Referring also to Fig. 16-Fig. 17, an exemplary one of the stages 40a"40c--- here 40a" isformed on the substrate 41 having a ground plane 43. The phase shifter stage 40a" is coupled to transmission line 32b of the transceiver 12i (FIG. 2). The phase shifter stage 40a--- includes a transmission line 512 coupled between the input matching network 513 as explained in conjunction with FIG. 5 and the transmission line 32b of transceiver 12i (FIG. 2). The matching network 513 is coupled to input gate electrodes 532a, 532b of a pair of FET's 530a-530b, as shown. FET's 530a-530b further include control gate electrodes 534a-534b, source electrodes 538a- 538b, and drain electrodes 536a- 536b. FET's 530a-530b arefabricated, such that gains and phases provided to an input signal fed to the input gate electrodes 532a, 532b are substantially equal at the drain electrodes 536a, 536b, as explained in conjunction with FIG.6. FET's 530a-530b are here connected in a common (grounded) source configuration, as shown. The control gate electrodes 534a-534b arefed voltage level control signals on control lines 29i3,1, 29i3b. The radarsystem (Fig. 2) providesthe control signals on lines 29i3. ,29i3b (notshown in Fig.

2).The levels of such signals on the control lines 296., 29i3b are used to control the operating point of each FET and hence the ampliturle of signals coupled to the drain electrodes 536a, 536b. The drain electrodes 536a, 536b are electrically connected to capacitor 544 and impedance matching networks 545a, 545b as described in conjunction with FIGS. 6-8. In the preferred embodiment of the invention,the impedancematching networks 545a, 545b are electrically connected to a conventional four port orquadrature coupler 1560. Such a coupler is described in an article 9 GB 2 165 397 A 9 entitled---GaAsMonolithic Lange and Wilkinson Couplers- by Raymond C. Waterman, Jr. et a], IEEE Transactions on Electron Devices, Vol, ED-28, No. 2, February 1981. A quadrature coupler is here used to couple input signals on each input of the coupler, in quadrature, to the output. In otherwords,the phase of the input signal drain electrode 536b as coupleto the output 1570 of the couplerwill lag the phase of the input signal from drain electrode 536a as coupled to 10 the output 1570 of the coupler by 90'.

Thus, unlike prior embodiments of the invention where signaisfed to the control gate electrodes 534a-534b are complementary pairs of control signals, such signals provided to place an FET in an off-state or an on-state, the signals fed on lines 296, 296btO the control gate electrodes 534a, 534b, here are selectable voltage levels between pinchoff and zero volts "on" levels of such FET.

An output voltage signal V, when measu red at the drain electrode, of an input sig nal Vi fed to the input gate electrode is given as: Vi = A.eM, is V. = BA.ej(,'2+'p), for embodiments disclosed in conjunction with FIGS. 5-14 where B is the gain and qi is the phase provided tothdinputsignal bythe FET.

However, if the control signals on lines 29i3,,,29i3,, fed to the control gates 534a-534b provide voltage level signals which change the operating point of the FET between the off state and the on state, the FErs 530a, 530b no longerfunction as switches, and, instead the FETs530a, 530bfunction asvariable gain amplifiers. When the outputvoltage V.(') of the FET 530a is a function of the control gate voltage V(,) fed to control gate 534a,the portion of the outputvoltage V,t atthe output of the coupler 1560 from the voltage V.1A) is given as: V. = BAA,)ej(wt+tp+A(Pn), where BA isthe 80 gain of FET 530a as a function of the control gate voltage, A(Pn isthe phase shift corresponding to the pathlength between the drain electrode of the nth FET and the output of the coupler 1560. The outputvoltage of FET 530a and FET 85 530b may be represented as:

VO (A); VOM where - (A) = BAAe j(b't ±0). (B). B E----1k) vo vo B A0e Since the quadrature coupler 1560 combines the twoinputsignals V.W and V.(B) in quadrature, the outputvoltage atthe coupler 1560 may be repre sented as:

VOT - vo (A) _jO(B) VOT BA A o CE"t +"' + '69"A) + Bjoei (tt + Ir + j21 13) or 95 VOT = A0A(Lt +1r+'69V t, + BE. -j77.12 1 which maybe simplified to:

V.T = A.'B'eP 2)l where B' = (BA2 + BB and tan C BB/BA.

Thus, the phase of an input signal Vi (Fig. 15) is shifted in accordance with the ratio of the amplitudes V.1M, V.(B) of such input signal as coupled to each drain electrode 536a, 536b coupled in quadrature to provide the signal Vt (Fig. 15) atthe output of the quadrature coupler 1560.

Thus by selecting the relative values of B, and B2 any phase between 0 and 7T/2 may be realized. Since onlythe ratio of B, and B2 determinesthe phase, it is possible to keep B'heneethe overall gain of the stage 40a--substantially constant. This is accomplished by separately adjusting the values of B, and B2. This provides an additional flexibility of amplitude control 60 along with phase adjustment.

As an examplejora minimum phase shift increment of 7T11 6, the values of B, and B2which will yield all eight phase shift increments between 0 and712 with substantially constant amplitude B'are given in 65 the Table below.

TABLE 1 Phase 1 bl b2 -T Shift 1 0 1 1.000 0 1 1 w 116 1 0.9131 1 0.195 1 1 1r

18 1 0.924 1 0.383 1 b2B B2 1 3 v 116 1 0.832 1 0.556 1 1 r 14 1 0.707 1 0.707 1 r 116 1 0.556 1 O.S32 1 3718 1 0.383 1 0.924 1 1 7 w 116 1 0.195 1 0.981 1 1 712 1 0 1 1.000 1 1 1 The minimal phase shift increment provided bythe variable phase shiftstage 40a" is limited only bythe degree of control of the voltage applied to the control gate electrodes 534a-534b of FET 530a-530b of phase shifter stage 40a".

Phase shift stage 40a--- is cascade interconnected to phase shift stage 40b% as shown. The phase shift stage 40V is identical to phase shift stage 40a". The only difference between the stages 40a" and 40V, is the technique for producing the phase shift. A phase shift of O'or 900 provided by phase shifter stage 40b--is determined by controlling which FET 530a-530b is biased in the on state, as previously described in conjunction with Figs. 6-8.

Phase shift 40c--- stage is similarto phase shift stage 40a" exceptforthe inclusion of an additional 90'of pathlength difference such astransmission line section 554b (Fig. 9b) coupled between the impedance matching network 545a and the coupler 1560.

Referring nowto FIGS. 18-19, bidirectional switch 18a having afirst branch port 19a coupled to transmission line32a (Fig. 2), a second branch port 21a, coupled to transmission line32h (Fig. 2), and a common port20a coupled to transmission line33i, go (Fig. 2) ' is shown. The bidirectional switch 18a is formed on the substrate 41, having the g round plane 43 formed on the bottom surface of substrate 41, as shown. FETs 50a-50b are formed on a portion of the su bstrate 41. In the preferred embodiment, FET's 50a, 50b include a plurality of FET cel Is, each cell having a reactive component (C1 coupled between the drain and source electrode of each cell as shown in Fig.20. A network, here the FET 50a isformed interconnecting each one of such drain electrodes of each FET cell.

Such network isformed having a characteristic impedance equal to the characteristic impedance of the transmission line sections 58a, 58b, here 50 ohms. The network isformed asfollows: a length (d) of a microstrip conductor 59 having a distributed induct- ance per unit length (L0 and a distributed capacitance per unit length (CL) is chosen such thatwhen coupled between the cells of each FET itwill provide such networkwith the predetermined characteristic impedance given as: Z. = (LL(CL + 2 (C"1d)))"2. The GB 2 165 397 A 10 bidirectional switch further includes a pairoftrans mission lines 58a-58b, each having a electrical length substantially equal to one quarterof awavelength (Ac/4) whereAc isthewavelength ofthe nominal operating frequencyforthe circuit. The first drain electrode 54a of FET50a is coupled between thefirst branch port 19a andto one end oftransmission line 58a. Thetransmission line 58a is coupled betweenthe branch port 19a andthe common port20a. Adrain electrode 54b of a second FET50b is coupledtothe second branch port21a, and one end of thetransmission line 58b.The otherend of thetransmission line 58b is coupledtothe common port20a. The sources 56a-56bof FET50a-50b are electrical iy connected to ground. The gate electrodes 52a-52b of FET's 50a-50b are electrically connected to control lines29il,29il, and arefed complementary signals on such lines.

TheT/Rswitch 18a is usedto couple a signal on transmission line 33i of the transceiver 12i (Fig.2)fed tothecommon part20ato one of the branch ports 19a or21ain accordancewith a pairof complementary control signals on lines 29lil, 19-il,fed to gate electrodes 52a, 52b. TheTIR switch 18a couples an inputsignal from common port 20a to branch portl 9a, as follows: the control signal on line 2gil, is fed to the gate electrode 52a of FET 50a, placing FET 50a in a nonconducting state; correspondingly,the control signal fed on linell, is applied tothe gate electrode 52b of FET 50b placing FET 50b in a conducting state, by placing FET50b in a conducting state, a short circuit(glow impedance path to ground) is produced atthe end 58Wof transmission line 58b coupled to the drain electrode 54b; one quarterof a wavelength from this point (atthe second end of transmission line 58b) the short circuit atthe firstend appears as an open eircuit@(high impedance) to a microwave frequency signal having a wavelength substantially similarto the wavelength of the corresponding centerband frequency of opera- tion forthe bidirectional switch 18a. The transmission line 58a and the open circuit resulting from FET50a being in a nonconducting state, appears as a 50 ohm transmission line atthe common portside 58a'ofthe transmission line 58a. Thus, a signal on common port 20a is coupled to the branch port 19a. In a similar manner, bychanging the state of the complementary pairof control signals on lines29il,T9il, a microwave frequencysignal on common port 20a may be coupled to the branch port21 a.

Having described preferred embodiments of the invention, itwill now become readily appareritto those of skill in the artthat other embodiments incorporating the invention may be realized. It isfelt, therefore, thatthis invention should not be limited to the disclosed embodiments but rathershould be limited onlyto the scope of the appended claims.

Matterdescribed hereinbefore is described and claimed in co-pending patent application No. 8305509from which the present application is

Claims (3)

divided. CLAIMS

1. Atransc,-iverelementforcoupling transmitted and received electromagnetic energy between a pair ofterminals comprising: means for providing gain and a selected phase shiftto both transmitted and received electromagnetic energy passing therethrough; and meansfor directing transmitted and received electromagnetic energy in the same direction through said gain and phase shift means. 70

2. A transceiver element according to claim 1, wherein the directing means provides a pair of signal paths between the pair ofterminals of the transceiver element.

3. A transceiver element according to claim 2, wherein there is provided a transmitter amplifier and a receiver amplifier; and wherein a first one of such paths is a transmission path and in such path is disposed the transmitter amplifier and a second one of such paths is a receiving path and in such path is disposed the receiver amplifier.

Printed in the United Kingdom for Her Majesty's Stationery Office, 8818935, 4186 18996. Published at the Patent Office, 25 Southampton Buildings, London WC2A lAY, from which copies may be obtained.