GB2159333A - Transceiver element - Google Patents

Description

1 GB 2 159 333A 1

SPECIFICATION

Transceiver element This invention relates to antenna systems and more particularly to phased array antenna systems.

As is known in the art, an array antenna includes a plurality of individually radiating elements.

In some systems the individual radiating elements are coupled to a transmitter through a transmitter element for controlling the phase and amplitude of the transmitted signal. Similarly, the individual radiating elements are coupled to a receiver through a receiver element, for controlling the phase and amplitude of the received signal. In other systems the individual radiating elements are coupled to both the transmitter and receiver through a single element here referred to as a transceiver for controlling the phase and amplitude of both transmitted and received signals. The relative phase and amplitude of the microwave frequency signal passing between the plurality of radiating elements and a corresponding plurality of individual tran sceiver elements are controlled to obtain a desired radiation pattern. The pattern obtained is a result of the combined action of all the individual transceiver and radiating elements. Many devices such as ferrite phase shifters are used to control the phase of the microwave frequency signal. Many of such phase shifters are reciprocal, that is, the phase shift of a signal passing through one of such devices is independent of the direction which the signal passes through. In 20 some applications it is desirable to provide an active phase shifter to provide gain to a signal passing there through. Such a phase shifter is generally inherently nonreciprocal. Thus, the use of an nonreciprocal phase shifter in a transceiver would require the use of two of such phase shifters. A developing trend in phased array antenna systems is toward production of the transceiver elements in monolithic integrated circuit form. This is desired in order to reduce cost 25 and size factors generally associated with phased array antenna systems and to provide phased array antennas adapted for certain applications where size and cost are critical such as airborne or space based radar systems.

In accordance with the present invention, a transceiver for coupling a microwave signal between an antenna element and a radar system, is provided. Such a transceiver includes a plurality of switching means arranged to steer a microwave frequency signal provided by the radar system through an nonreciprocal phase shifter to the phased array antenna during a transmit mode, and to steer a microwave frequency signal provided from the phased array antenna through the nonreciprocal phase shifter to the radar system during a receive mode. The microwave frequency signal passes through the phase shifter in the same direction during both 35 the transmit and receive mode. A set of control signals is fed to such switching means to control the steering of the microwave frequency signal between the radar system and the phased array antenna. With such an arrangement, two signal paths through an active nonreciprocal phase shifter are provided. This arrangement reduces the cost and size of the transceiver element by permitting the use of a single active nonreciprocal phase shifter. Further, since each of the elements of the transceiver element may be realized as monolithic microwave integrated circuits this structure results in a compact transceiver element, modular in form and less expensive to produce.

The invention will now be described by way of example with reference to the accompanying drawings, in which:

Figure 1 is an overall block diagram of a radar system coupled to a phased array antenna system through a plurality of transceiver elements; Figure 2 is a block diagram of one of the plurality of transceiver elements shown in Fig. 1; Figure 3 is a block diagram of the transceiver element, utilizing a five port switch; Figure 4 is a block diagram of a transceiver using a dual channel phase shifter; Figure 5 is a block diagram of a 4-bit nonreciprocal phase shifter; Figure 6 is a diagrammatical view of a 180 phase shift increment stage of a 4-bit nonreciprocal phase shifter used in the one of the transceiver elements; Figure 6A is an isometric view of a bias line and output line insulated from each other with an air gap plated overlay; Figure 6B is a cross sectional view of a parallel plate capacitor formed on the substrate; Figure 7 is a block diagram of the phase shifter stage depicted in Fig. 5; Figure 8 is a detailed schematic diagram of the phase shifter stage depicted in Fig. 5; Figures 9A-9D are plan views of pairs of transmission lines providing electrical pathlength differences used to realize a 4-bit phase shifter.

Figure 10 is a block diagram of a 4-bit dual channel phase shifter; Figure 11 is a detailed schematic of one stage of a reciprocal phase shifter; Figure 12 is a diagrammatical view of the stage of a dual channel phase shifter depicted in Fig. 11; Figure 13 is a detailed schematic of an alternate embodiment of a four bit nonreciprocal 65 2 GB 2 159 333A 2 phase shifter; Figure 14 is a block diagram of the nonreciprocal phase shifter of Fig. 13, including reciprocating switches; Figure 15 is a detailed schematic diagram of a variable phase shifter utilizing a quadrature 5 coupler.

Figure 16 is a plan view of the variable phase shifter shown in Fig. 15; Figure 17 is a block diagram of one stage of the n-bit variable phase shifter shown in Fig. 16; Figure 18 is a diagrammatical view of a bidirectional three port switch; Figure 19 is a schematic diagram of the bidirectional switch shown in Fig. 18; Figure 20 is a schematic diagram of a preferred field effect transistor FET used in the bidirectional switch of Fig. 18.

Referring now to Fig. 1, a phased array antenna 10 is coupled to a radar system 11 by a feed network 14, as shown. The phased array antenna 10 includes a plurality of, here n, identical transmitter/ receiver (transceiver) elements 1 2a-1 2n, coupled to a like plurality of corresponding antenna elements 26a-26n, as shown. The feed network 14, here a parallel feed network, provides a signal path for a microwave signal passing from the radar system 11 to the phased array antenna 10 for transmission to a target (not shown), and a signal path for reception of echo signals from the target (not shown) to the radar system 11. A plurality of control buses 29a-29n, 29a-2-9n are provided from the radar system 11. Signals on such buses 29a-29n, 2-9a-T9-n are used to control the transceiver elements 1 2a- 1 2n of the phase array antenna 10. 20 The microwave signal from the feed network 14 is coupled to each of the transceiver elements 1 2a- 1 2n, as indicated by the open arrows 13. The portion of microwave signal coupled to each one of the transceiver elements 1 2a-1 2n is then coupled to the corresponding one of the antenna elements 26a-26n. Similarly, a portion of the microwave echo signal from the target is coupled to each of the antenna elements 26a-26n, the corresponding transceiver elements 1 2a- 1 2n, and the feed network 14 as indicated by solid arrows 15, for processing by the radar system 11. The control signals on buses 29a-29n, 29a-ffn during the transmit mode allow the transceiver elements 26a-26n to produce collimated and directed beams of transmitted microwave energy and control signals on such buses during the receive mode allow such transceiver elements 26a-26n to produce collimated and directed beams of received microwave 30 energy.

Referring now to Fig. 2, a representative one of the transceiver elements 1 2a- 1 2n, here transceiver element 1 2i is shown coupled, via a transmission line 33i, to a portion of the feed network 14 and to an antenna element 26i, via a transmission line 35i, as shown. Transceiver element 1 2i here includes 50 ohm transmission lines 32a to 32h, four tra nsm itter/ receiver (T/R) switches 1 8a- 1 8d, each having a common port 20a-20d, a pair of branch ports 1 9a- 1 9d and 21 a-21 d, and a control input 22a-22d. Each one of the control inputs 22a-22d is fed by a pair of control lines 29i, 29i, of buses 29i, 29i. The T/R switches 18a-1 8d are here of a type to be further explained in conjunction with Figs. 18-19. Suffice it to say tere, however, that complementary, binary or logical signals are fed to the control lines 29i, 29i, respectively, and such logical signals are used to control the electrical coupling between the common port and the branch ports. Thus, for example, using an exemplary one of the T/R switches 18a-1 8d, here T/R switch 18a, such switch 18a has common port 20a coupled to branch port 1 9a in response to a first pair of logical stat es of control signals fed to lines 29i, 29i, i.e. a logigal 1 on line 29i, and a logical 0 on line 29i, and such common port 20a is coupled to branch port 21 a in rqponse to the complementary pair of logical states of the control signals fed to line 29i, 29i, i.e. a logical 0 on line 29i, and a logical 1 on line T9-i,.

The common port 20a of T/R switch 18a is coupled to the feed network 14, via the transmission line 33i, as shown. Branch ports 19a and 21 a of T/R switch 18a are coupled to branch ports 1 9d and 21 b, via transmission lines 32a and 32h, respectively. Branch port 1 9b 50 of T/R switch 1 8b is coupled to an input of a transmitter amplifier 24, via the transmission line 32d. The transmitter amplifier 24 is here formed on a semi-insulating substrate, here a gallium arsenide (GaAs) substrate. The output of transmitter amplifier 24 is coupled to the branch port 1 9c of T/R switch 18c, via transmission line 32e. The common port 20c of T/R switch 18c is coupled to the antenna element 26i, via transmission line 35i. The branch port 21 c of T/R switch 1 8c is coupled to an input of the receiver amplifier 28, via transmission line 32f. The receiver amplifier 28, here a low noise amplifier, is here formed on a semi-insulating substrate (here GaAs). The output of the receiver amplifier 28 is coupled to the branch port 21 d of T/R switch 18d, via transmission line 32g. The common port 20d of T/R switch 18d is coupled to the input of an active phase shifter 40, here a nonreciprocal active phase shifter having a plurality of stages (not shown, to be described in detail in connection with Figs. 5, 6 and 7), via transmission line 32b. Suffice it to say here, however, that each stage of the active phase shifter includes a field effect transistor suitably biased to provide gain to the radio frequency signal passing through it. Control signals for the active phase shifter 40 are fed thereto, via buses 29'2, 65 -2712 of bus 29i. The output of the active phase shifter 40 is coupled to the common port 23b of 65

3 GB 2 159 333A 3 T/R switch 18b, via transmission line 32c.

During a transmit mode, the transceiver element 12i couples a microwave frequency signal from the radar system 11 to the antenna element 26i. A transmit signal path for coupling a signal from the radar system 11, via feed network 14, to the antenna element 26i is depicted in Fig. 2 by an open arrow 13, as shown. In the transmit mode, the control signals on lines 29i, 5 29i, are used to couple each one of the common ports 20a-20d to the corresponding branch ports 1 9a-1 9d of the respective T/R switches 18a-1 8d. Thus a portion of the microwave signal is coupled from the radar system 11 to the input of the active phase shifter 40. The active phase shifter 40 is here used to vary the phase shift of the applied microwave frequency signal by a predetermined amount in accordance with control signals on buses 29i2-29i, which 10 are fed to a control input 42, of the active phase shifter 40. The microwave frequency phase shifted signal is then coupled to the input of the transmitter amplifier 24. The signal at the output of the transmitter amplifier 24 is coupled to the antenna element 26i.

During a receive mode, a portion of a received echo signal is coupled from the antenna element 26i to the radar system 11. A receive signal path for coupling the received echo signal 15 from the antenna element 26i to the radar system 11 is depicted in Fig. 2 by solid arrows 15, as shown. During the receive mode the complementary logical states of the control signals previously on lines 29il-T9-il are now fed to lines 29i, 29i, and such signals are used to couple each one of the common ports 20a-20d to the branch ports 21 a-21 d of the respective T/R switches 18a-18d. Thus the echo signal is coupled from the antenna element 26i to the 20 receiver amplifier 28. The signal at the output of the receiver amplifier 28 is coupled to the input of the active phase shifter element 40. The signal passing through the phase shifter is again phase shifted in accordance with the control signals fed on buses 29'2-29i2. The phase shifted signal produced at the output of the active phase shifter element 40 is then coupled to the radar system 11, via the feed network 14. Thus is is noted that the microwave frequency signal is coupled through the active phase shifter 40 in the same direction for both the transmit mode and the received mode. Thus, referring again to Fig. 1 in a similar manner, each of the plurality of transceiver elements 1 2a- 1 2n are used to couple a portion of microwave signal between the radar system 11, via the feed network 14 and the plurality of antenna elements 26a-26n, to produce in combination a collimated and directed beam (not shown) during the 30 transmit mode and the receive mode.

Referring now to Fig. 3 an alternative the embodiment of a transceiver element 1 2i' suitable for use in the phased array antenna 10 of Fig. 1 is shown coupled to a portion of the feed network 14 and the antenna elements 26i. Transceiver element 1 2i' here includes a five port switch 310, the active phase shifter 40, the transmitter amplifier 24, the receiver amplifier 28, and the three port T/R switch 1 8c, as shown. The five port switch 310 is formed on a substrate, (not shown) here semi-insulating gallium arsenide (GaAs) having a ground plane (not shown) here plated gold formed on the bottom surface of the substrate. Formed in active regions on portions of the top surface of the semi-insulating substrate are FET's 50a-50d here GaAs FETs, each having gate electrodes 52a-52d (Fig. 3), a drain electrode 54a-54d and a 40 source electrode 56a-56d. The gate electrodes 52a, 52d of FET's 50a, 50d, are connected to control line 29i, and the gate electrodes 52b, 52c of FET's 50b, 50c are connected to control line 29i, as shown. The FET's are here connected in a common (grounded) source configura tion. The T/R switch 310 further includes transmission lines 60a-60f. Each transmission line 60a-60f has an electrical length, corresponding to one quarter wavelength (A,/4), where Ac is 45 the wavelength of the corresponding nominal or operating centerband frequency (fJ of the circuit. The feed network 14 is electrically connected to a first end 60. 1 Of 1\2/4 transmission line 60a and a first end 60f, of Xc/4 transmission line 60f, via transmission line 33i. The drain electrode 54c of FET 50c is electrically connected to a second end 60a2 of Ac/4 transmission line 60a. A first end 60b, of Xc/4 transmission line 60b is electrically connected to the second 50 end 60a2 of transmission line 60a and drain electrode 54c. A second end 60IJ2 of Xc/4 transmission line 60b is electrically connected to the input port of the active phase shifter 40, via transmission line 32b and to a first end 60d, of X,,/4 transmission line 60d. The second end 60d2 of transmission line 60d is electrically connected to the output of the receivier amplifier 28 and to the drain electrode 54d of FET 50d. A second end 60f2 of Xc/4 transmission line 60f is 55 electrically connected to a first end 60e, of Ac/4 transmission line 60e, and drain electrode 54a of FET 50a. A second end 60e2 of Ac/4 transmission line 60e is coupled to the output of the active phase shifter 40, via transmission line 32c and to a first end 60c, of Ac/4 transmission line 60c. A second end 60C2 of Ac/4 transmission line 60c is coupled to the input of the transmitter amplifier 24 and to the drain electrode 54b of FET 50b. The connections of 60 transmitter amplifier 24 and receiver amplifier 28 to T/R switch 1 8d are the same, as explained above in conjunction with Fig. 2.

During the transmit mode, as shown by the open arrows 13 a logical control signal on line 29i, of bus 29i is fed to the gate electrodes 52a, 52d of FETs 50a, 50d and the complement of such logical control signal is fed (via line 2-9i, of bus -2-9i) to gates 52b, 52c of FETs 50b, 50c. 65 4 GB 2 159 333A 4 In response to such signals FET's 50a, 50b are placed in a conducting state and FET's 50b, 50c are placed in a nonconducting state. The A.

J4 transmission lines 60d, 60e and 60f have ends 60d2, 60e, and 60f2 electrically connected to FET's 50a and 50b, as previously described. When FET's 50a, 50d are placed in a conducting state, a short circuit (low impedance path to ground designated by g)) is produced at the ends 60d2, 60e, and 60f2 of transmission lines 60d-60f coupled to the FET's 50a, 50d. One quarter wavelength therefrom (at the second end 60d, 60e2, and 60f, of each transmission line 60d-60f) the short circuits at ends 60d2, 60e, 60f2 appear as open circuits (high impedance paths to ground designated by C) at ends 60d, 60e2, 60f, to a microwave frequency signal having a wavelength substantially equal to the wavelength of the corresponding nominal or centerband frequency of operation, for the transceiver. Thus, no signal path is provided during the transmit mode through line 60f and the transmitted energy passes through lines 60a and 60b. Further because end 60d, appears as an open circuit 0, the transmitted energy passes from line 60b through line 32b, through the phase shifter 40 and through line 32c. Since end 60e2 appears as an open circuit C the transmitted, and now phase shifted energy passes through line 60c, transmitter amplifier 24, 15 T/R switch 18c and to the antenna 26i, as previously described in conjunction with Fig. 2.

During the receive mode as shown by the closed arrows 15, the control signals on lines 29i, 29i, are switched (or complemented) in logic state placing FET's 50a and 50d in a nonconducting state, and placing FET's 50b and 50c in a conducting state. The ends 60a2l 60b, and 60C2 of the A.

J4 transmission lines 60a, 60b and 60c which are coupled to the drain 20 electrodes 54b and 54c of FET's 50b and 50d are thus coupled to ground and the other ends 60a, 60b2, and 60c, of the transmission lines 60a, 60b, and 60c present impedances corresponding to open circuits. Thus, a received microwave signal from antenna element 26i is coupled to the output of the receiver amplifier 28 as explained in conjunction with Fig. 2. The received signal is then coupled through transmission line 60d to the active phase shifter element 25 40. The signal on the output of the active phase shifter 40 is thus coupled to the radar system through transmission lines 60e and 60f.

Referring now to Fig. 4, an alternative embodiment of a transceiver, here transceiver 1 2i" suitable for use in the phased array antenna 10 of Fig. 1 is shown coupled to a portion of the feed network 14, via transmission line 33i and to the antenna element 26i, via transmission line 30 35i, as shown. Transceiver element 12i" includes T/R switches 18a and 18c, transmitter amplifier 24, receiver amplifier 28. Here, however, a dual channel active phase shifter 44 is provided. Dual channel active phase shifter 44 has a plurality of cascade interconnected phase shift stages here 44a-44d of a type to be further described in detail in conjunction with Figs.

10-12. The T/R switch 18a has common port 20a coupled to the feed network 14 via transmission line 33i. Branch ports 1 9a and 21 a of T/R switch 1 8a are coupled to the input 47a of a first channel 47 and the output 49b of a second channel 49 of dual channel phase shifter 44, respctively, as indicated. The output 47b of the first channel 47 is coupled to the input of the transmitter amplifier 24, via transmission line 32b. The output of the receiver amplifier 28 is coupled to the input 49a of the second channel 49, via transmission line 32e. 40 The connection of the transceiver 1 2i" to antenna element 26 i (Fig. 1) is as previously explained.

During the transmit mode, as shown by the open arrows 13, in response to complementary control signals on lines 29i, T9-il a microwave signal fed to common port 20a from the radar system 11 is coupled to branch port 1 9a. Such signal from branch port 1 9a is coupled to the 45 input 47a of the dual channel phase shifter 44. The signal is shifted in phase and coupled to the transmitter amplifier 24 and to the antenna 26, as previously described. During a receive mode, as shown by the closed arrows 15, in response to the complements of the previous control signals on lines 29i, T9-i the microwave signal fed to the common port 20c from antenna 26i is coupled to the branch port 21 c and thus to the receiver amplifier 28. The signal 50 at the output of the receiver amplifier 28 is fed to the input 49a of the phase shifter 44. The signal shifted in phase is then fed to the T/R switch 1 8a to the radar system 11, as previously described.

Referring now to Fig. 5, a single channel digitally controlled phase shifter 40 suitable for use in transceiver element 1 2i (Fig. 2) and transceiver element 1 2i' (Fig. 3) is shown to include a plurality of cascade interconnected stages 40a-40d with like parts of each stage being designated by the same numeral. An exemplary one of such stages 40a-40d, here stage 40a, is discussed in detail in conjunction with Figs. 6-8. Referring now to Fig. 6, the phase shifter stage 40a is formed on a substrate 41 here GaAs having a ground plane 43, as shown.

Referring also to Figs. 7, 8 the phase shifter stage 40a includes a microwave transmission line 60 512, here having an impedance of 50 ohms, coupled to an input impedance matching circuit 513. Transmission line 512 is here fed by a microwave frequency signal from transmission line 32b (Fig. 2). Input impedance matching circuit 513 is here used to match the input impedance of the phase shifter stage 40a to the characteristic impedance of the transmission line 512. The input matching circuit 513, here includes a first transmission line section 514, having a 65 GB 2 159 333A reactance which is primarily inductive, coupled in shunt to the input transmission line section 512, via a bottom plate 526c of a capacitor 526. Bottom plate 526c of capacitor 526 is coupled to one end of the shunt mounted transmission line section 514. The upper plate 51 8a of a second series connected capacitor 518 is coupled to line 516 and the bottom plate of 518 is coupled to ground by a via hole 518b, as shown. Ground pad 522 is coupled to ground by a via hole connection 522a. As shown in Fig. 613, capacitor 526 is formed on the top surface of the substrate 41 here includes a top plate 526a which is coupled via an air bridge 526d to the strip conductor portion of a transmission line 528. Aligned under this top plate is a bottom plate 526c of evaporated gold formed on the substrate 41. The top plate 526a and bottom plated 526c are separated by a 5000 Angstrom (A) layer 526b of silicon nitride (Si,N4). The bottom 10 plate 526c has a finger 526e (Fig. 6) which is used to connect the second circuit element, here transmission line section 514, to the capacitor 526. The connection is provided by a metal to metal contact which couples to the bottom plate 526c. A second transmission line section 516, here having a reactance which is primarily inductive is coupled in shunt between capacitors 518 and 526. The connection of capacitor 518 to inductor section 516 provides the bias feed 520 15 for the gate electrode. The input matching circuit 513 further includes the third transmission line section 528 here also having a reactance which is primarily inductive, connected between the junction of capacitor 526 with shunt mounted transmission line section 516 and a common input junction 532. The phase shifter stage 40a further includes a FET switch 530 having a dual gate FET, 530a-530b, as shown. FET's 530a and 530b include first gate electrodes 20 532a-532b coupled to the common junction 532, second gate electrodes 534a, 534b, separate drain electrodes 536a, 536b and separate source electrodes 538a, 538b. FETs 530a, 530b are here connected in a common (grounded) source configuration. FET 530a, 530b are fabricated such that the gains and phases provided by each FET to signals fed to the gate electrode and coupled to the drain electrode are substantially equal. In other words, IS211., the 25 fraction of power coupled to the drain electrode 536a of 530a from a signal on gate electrode 532a substantially equals, IS211b, the fraction of power available at the drain electrode 536b of FET 530b from an incident input signal provided signal gate electrode 532b of FET 530b.

Similarily, 1P S21 la 41 S21 lb that is, the phases of the instantaneous power delivered to each drain electrode of FET 530a, 530b are substantially equal. Control gate electrodes 534a, 534b are 30 fed control signals on lines 29'2a, 9'2a (Fig. 2). These control signals are used to control the coupling of an input signal fed to the gate electrode 532a, 532b to the corresponding drains 536a, 536b of FET's 530a, 530b. High frequency components in the signals on control lines 29i2a, 29i2a are shorted to ground, via capacitors 527a, 527b. The drain electrodes 536a, 536b are electrically connected to identical impedance matching circuits 545a- 545b, as shown. The 35 matching circuit 545a (Fig. 8), here includes a first transmission line section 548a coupled in series between the drain electrode 536a and a coupling capacitor 552a. A second transmission line section 549a is coupled in shunt with the junction of the first transmission line section 548a, the bottom plate of capacitor 552a, and an upper plate of a dc blocking capacitor 544.

The bottom plate of the dc blocking capacitor 544 is connected to ground by a via hole 40 connection 544a (Fig. 6). The impedance matching circuit 545b is formed in a similar manner on the substrate 41 (Fig. 6) for the drain electrode 536b. The impedance matching circuit 545b includes a transmission line section 548b, a coupling capacitor 552b, and a second transmis sion line section 549b, coupled to the drain electrode 536b in a similar manner as the corresponding elements of impedance matching circuit 545a. The common connection of 45 transmission line sections 549a-549b and the dc blocking capacitor 544 provides the bias feed 546 for drain electrodes 536a, 536b. As shown in Fig. 6A, the bias feed 542 here is insulated from the transmission line section 548b by a conventional air gap plated overlay. In general, such overlays are here used in all embodiments to insulate such crossing signal paths. The upper plates of coupling capacitors 552a-552b of the impedance matching circuits 545a, 545b respectively, are integrally formed with the strip conductor portion of transmission lines 554a and 553, respectively. Transmission line 554a has an electrical length which provides a phase shift (p, + A(p,, to an input signal coupled thereto and transmission line 553 has an electrical length which provides a phase shift of (P, to an input signal coupled thereto. Such pair of transmission lines 554a, 553 as shown in Fig. 9a and described in more detail hereinafter provides one path having an unique phase shift increment AOa. Each second end of transmission line section 554a, 553 is coupled to a corresponding input port 565, 567 of a conventional three port coupler, which couples power from two input ports and provides the coupled power to an output port, via branch arms 564, 566. Such a coupler is described in an article entitled "GaAs Monolithic Lange and Wilkinson Couplers" by Raymond C. Waterman Jr. et al, IEEE Transactions on Electron Devices, Vol. ED-28, No. 2, February 1981. The output of the three port coupler is electrically connected to an output port 570. Capacitors 518, 526, 544, 552a, 552b, 527a and 527b are here formed in a similar manner, as explained for capacitor 526.

In operation, an input signal fed to transmission line 512 is coupled toeach gate electrode 532a, 532b. Such signal is coupled to one of the drain electrodes 536a, 536b selectively in 6 GB 2 159 333A 6 accordance with the control signals fed on lines 29'2a, 29i,2,, to the control glte electrodes 534a, 534b. If the input signal in response to such control signals on lines 29'2., 29i2. is coupled to drain electrode 536a, the phase of such signal is shifted by an amount 01 + A0. through transmission line 554a.

Conversely, the electrical path from drain electrode 536b to the coupler 560 provides a 5 pathlength corresponding to a phase shift of 0, Thus, if in response to the control signals on lines 29'2a, 9'2a, the input signal is coupled to drain electrode 536b, the phase of such signal at the output 570 is shifted by an amount of 0, through transmission line 553. Thus, a phase shift of an input signal of (p, or 01 + A0a at the output 570 is selected in response to control signals on lines 29i2v 29i2a. A plurality of such stages are cascade interconnected to form the 10 phase shifter 40 (Fig. 5). Each stage has two paths which correspond to phase shifts of an input signal of (p, through one path an amount 01 + A(pi through the second path where i is the number of the stage. For, four cascade interconnected stages, the phase shift AO, for each stage is here A(P,, = 180, AO, = 90', A0. = 45' and A0d = 22.5'.

Referring again to Fig. 5, with like parts in each stage being designated by the same numeral, 15 the active nonreciprocal phase shifter 40 used to produce an output signal at port 570d having a predetermined phase shift relative to an input signal on transmission line 512 includes four cascaded interconnected phase shifter stages 40a-40d, as shown. Each phase shifter stage 40a-40d realized in accordance with Fits. 6-8, selectively provides a unique phase shift to an input signal Of AO. = 1 80',A0b = 90',Aor = 45' and A0d = 22.5', respectively. Each phase shift 20 stage includes a unique length of transmission line between output matching circuit 545a and the three port coupler 560. Each length of transmission line, in conjunction with the length of transmission line 553, provides each stage with a unique pathlength difference corresponding to the unique phase shift. In response to control signals on lines 29'2,,- 29i2d, and 29'2,-29'2d selective combinations of phase shift increments of 0' or 180', 0 or 90', 0 or 45' and 0, or 25 22.5' are provided by phase shifter stages 40a-40d, respectively of control signals fed by lines 29'2a to 29'2d and 2ha to 29'2d are represented by A to D and A to 5, respectively. The phase shift 0 of an input signal through phase shifter 40 may be represented by the following logical equation as:

0 = [(A(0i + A0,J + M0,)) + (B(O, + A0J + 9(0,)) + (C(O, + A(p,:) + C(Offl + (D(O, +'k(pd) + 30 The phase shifter 40, thus, is used to vary the phase of a signal fed to transmission line 512 of stage 40a from 0 to 360' in here 22.5' phase shift increments.

Referring now to Figs. 9A-91) transmission line sections 553 and 554a554d used to provide unique incremental phase shifts for stages 40c-40d respectively, of the phase shifter 35 40b shown in Fig. 5, have like parts being designated by the same numeral. The transmission lines 553 and 554a-554d are coupled to the input ports 565, 567 of the three port coupler 560, having a thin film load resistor 562 and branch arms 564, 566, and to a portion of the impedance matching networks 545a-545b, as shown. The transmission lines 554a-554d are formed on the semi-insulating substrate 41 by strip conductors 555a-555d and 557, respectively, and the ground plane 43, which is separated by a dielectric, here the semi insulating substrate 41. Strip conductors 555a-555d and 557 are designed to provide the corresponding transmission lines 554a-554d and 553 each with a 50 ohm characteristics impedance. The transmission lines 554a-554d each have an electrical length equal to a corresponding precise fractional wavelength X./2 n, with respect to transmission line section 553, where X. is the wavelength of the nominal or centerband operating frequency (f.) for the active phase shifter n is the total number of stages. Thus, transmission line section 554a has a pathlength (AO.) equal to XJ2 with respect to transmission line section 553. In a similar manner, the pathlengths for segments 554b-554d with respect to transmission line 553 are AC 4, Xc 50 J8, and XJ 16. Thus, the transmission lines 554a-554d, with respect to transmission line section 553, here represent path length differences corresponding to a phase shift of an applied signal with respect to the phase of such signal of 180', 90', 45 and 22.5 respectively.

Referring now to Fig. 10, a dual channel phase shifter 44 having channels 47 and 49 which is suitable for use in the transceiver 1 2V' shows in Fig. 4 includes four one bit phase shifter stages (P.S.Stages) 44a-44d cascade interconnected together, as shown, The dual channel phase shifter stages 44a-44d are here identical except for the pathlength differences (phase shift increment) (A(pi) forming the phase shift networks of each stage. Each channel of the dual channel phase shifter provides one of two signal paths, such path being selected in response to control signals fed on lines 29'2,,-29i,, and 29'2a-29'2d Such paths provide either a phase shift 60 of (p, or a phase shift of 4), + Aq), where i is the number of the stage. The phase shift increment (AO,) for each of the four stages 44a-44d shown in Fig. 10 are a = 180', AO, = W, 90',A(p,: = 45' and A0d = 22.5 for stages 44a-44d, respectively as explained in conjunction with Figs, 9a-9d.

Referring now to Fig. 11, an exemplary one of such phase shifter stages, here phase shifter 7 GB 2 159 333A 7 stage 44a is shown. The phase shifter stage 44a includes FET's 530a-530d each having a pair of gate electrodes 532a-532d, and 534a-534d, a drain electrode 536a-536d, and a common source electrode 538. FET's 530a-530d are here realized as a double pole double throw FET switch 530 of a type disclosed in U.S. Patent No. 4,313,126 filed May 21, 1979, and assigned to the assignee of this invention. Each of the FET's 530a-530d are here connected in 5 a common (grounded) source configuration, as shown. Each FET 530a-530d is formed on the substrate 41 within close proximity to the other FET's 530a-530d, as shown. FETs 530a-530d are fabricated such that gains and phases provided to an input signal are substantially equal, as explained in conjunction with Figs. 6-7.

The first phase shifter channel 47 includes a microwave transmission line 512, here coupled 10 to the transceiver 1 2i" (Fig. 4), via transmission line 32a provided a signal input for the phase shifter stage 44a. The microwave transmission line 512 is electrically connected to an impedance matching circuit 51 3a previously described in conjunction with Figs. 6-8. Matching circuit 513 is electrically connected to the common input junction 532. Input junction 532 is coupled to input gate electrodes 532a, 532b of FET's 530a, 530b, respectively. Signals fed on 15 lines 29i2a' 2-9i2,, from the radar system 11 (Fig. 1) are fed to the second gate electrodes 534a, 534b for controlling the conduction of an input signal on input gate electrodes 532a, 532b to the corresponding drain electrodes 536a, 536b of FET 530a, 530b, respectively. High frequency signal components on control signals fed on lines 29i2a, 2-9i2i, are shorted to ground by capacitors 527a, 527b. An input signal fed equally to input gate electrodes 532a, 532b is 20 selctively coupled, to the corresponding drain electrode 536a, 536b, in accordance with the control signals on lines 29i2a, 29'2a fed to the control gate electrodes 534a, 534b. The drain electrodes 536a is electrically connected to an impedance matching network 545a as described in conjunction with Figs. 5-7. The drain electrode 536b is similarly, electrically connected to the impedance matching network 545b, as shown. The impedance matching network 545a is 25 coupled to here, the microwave transmission line 554a. In a similar manner, the impedance matching network 545b is coupled to the microwave transmission line 553a. Each second end of transmission lines 553a and 554a is coupled to the pair of input 565, 567 of the conventional three port coupler 560.

The second channel 49 of digital phase shifter stage 44a includes microwave transmission 30 line 512' coupled to transceiver 1 2i" (Fig. 4) via transmission line 32g (Fig. 2) for providing the signal input for channel 49. The microwave transmission line 512' is electrically connected to an impedance matching circuit 513' as previously disclosed in conjunction with Figs. 5-7. A second matching circuit 513' is electrically connected to a common junction 532. Common junction 532' is electrically connected to input gate electrodes 532c, 532d of FET's 530c, 530d. Control gates 534c, 534d of FET 530c, 530d are electrically connected to gate electrode pads 524 and 527, respectively. The control gates 534c, 534d are fed signals on lines 29'2.1 29'2, from the radar system 11 (Fig. 1) for controlling conduction of an input signal on input gate electrodes 532c, 532d to the drain electrodes 536c, 536d of FET's 530a, 530b, respectively. Drain electrodes 536c-536d are electrically connected to impedance matching 40 networks 545c-545d as disclosed in conjunction with Figs. 6-8. Transmission lines 553' and 554a', are coupled between the impedance matching networks 545c-545d and the three port coupler 560'. The three port coupler 560' is electrically connected to output port 570'.

The total pathlength difference of the connection of drain electrode 536a to the three port coupler 560, for channel 47 is then selected to provide a corresponding phase shift equal to 0, + Aqa, as explained in conjunction with Figs. 9a-9d. The total pathlength difference of the connection of drain electrode 536b to the three port coupler for channel 47 is selected to provide a corresponding phase shift equal to (p, Thus, the phase of a signal applied to the gate electrodes 532a, 532b is shifted by an amount (p, + Ao,, or q), selectively in accordance with control signals fed to control gate electrodes 534a, 534b. In the same manner, transmission 50 lines 553', 554a' provide pathlengths to channel 49 between drains 536c, 536d of 0, + Aq),, or 01.

Referring again to Fig. 10, the dual channel phase shifter 44 having channels 47 and 49 has stages 44a-44d, each stage providing a unique phase shift to an applied signal. Each channel provides selective combinations of phase shift increments A(p. 1 80,Aob 90oA4)c = 45', and 55 Aq), = 22.5' in response to control signals on lines 29'2a-29i2d, Y9i2a-2- 9'2d Referring now to Fig. 12, the phase shifter stage 44a is shown, formed on a semi-insulating substrate 41 having a ground plane 43 on one side thereof, as shown. A low inductance ground connection 537 is here made through the source electrode region 538. Parallel plate capacitors such as 526 are formed on the substrate 41, as previously described in conjunction with Fig. 60 6B. Crossing signal paths are insulated one from another by conventional air gap plated overlays as described in conjunction with Fig. 6A.

Referring also to Fig. 5, the net overall gain for each four bit phase shifter 40 and 44' is approximately 8 decibels (db) or approximately 2db per stage. Each stage contributes 3db of loss from splitting of the input signal and another 3 db of loss due to power recombining at the 65 8 GB 2 159 333A 8 three port coupler 560. The total losses due to parasitic losses and the matching networks are less than 1 db. Allowing for substantial mismatch, a gain of approximately 8 db generally is realizable from a dual gate FET, operating at X-band, for example. Thus, a net grain of approximately 2 db per stage or approximately 8db for the phase shifters of Fig. 9 and Fig. 12 is realized. Since only four FETs, one per stage, at any given time are operating for each phase shifter, 40, 44 the d.c. power consumption will be four times that for one FET.

Now referring to Fig. 13, an alternative embodiment for a four bit digitally controlled phase shifter 401 suitable for use in transceivers 1 2i and 1 2V (Fig. 2 and Fig. 3) includes a first stage 40a' having a single pole four throw (SP4T) FET switch 1330 and a second stage 40b' having an SP4T FET switch 1370, as shown. The SP4T FET switches 1330 and 1370 are here of a 10 type disclosed in the above mentioned U.S. Patent No. 4,313,126. Each stage 40a', 40b' is formed on a substrate (not shown), having a ground plane (not shown).

The first stage 40a' of the four bit digital phase shifter 40' further includes FET's 1 330a-1 330d, as shown, FET's 1330a-1 330d are fabricated such that gains and phases provided to an input signal are substantially equal, as explained in conjunction with Fig. 5-7. Each FET 1 330a-1 330d, includes a input gate 1 332a-1 332d, a control gate 1 334a-1 334d, drain electrodes 1 336a-1 336d and a source region 1338. FET's 1 330a-1 330d are here connected to a common (grounded) source configuration. A low inductance ground connection is here made from the source electrode 1338 to the ground plane 43 (not shown) by a conventional via hole connection.

A microwave transmission line 512, here having an impedance of 50 ohms is coupled to an impedance matching circuit 513, as previously explained in conjunction with Figs. 4-6. The impedance matching circuit is coupled to input gate electrodes 1 332a-1 332d. The drains 1 336a- 1 336d are electrically connected to identical impedance matching networks 545a-545d of a type previously described in conjunction with Fig. 8. Impedance matching 25 networks 545a-545d are each coupled to a transmission line 1320 having a characteristic impedance Z0, here 50 ohms. Transmission line 1320 is terminated at one end in a resistor 1322, here having a value equal to 50 ohms, the characteristic impedance of the transmission line 1320. The resistor 1322 is coupled in shunt between the transmission line 1320 and ground. Drain electrode 1 336d is electrically connected to the end of transmission line 1320 30 through the impedance matching network 545d. Drain 1 336c of FET 1 330c is electrically connected to transmission line 1320, through the matching network 545c defining a section of transmission line 1326, drain electrode 1 336b of FET 1 330b is electrically connected to transmission line 1320 through the matching network 545b defining a section of transmission line 1324, and drain electrode 1 336a of FET 1 330a is electrically connected to transmission 35 line 1320, through the matching network 545a, defining a section of transmission line 1322.

Here, all the transmission line sections 1322-1326 have the same electrical length and thus each section shifts the phase of an applied signal by an equal amount. The total phase shift of an output signal with respect to the phase of the input signal fed through transmission line 512 is the sum of the phase shifts provided by each of the equal electrical length transmission line 40 sections 1322, 1324 and 1326 of which the output signal passes through from a selected one of the drain electrodes 1 336a-1 336d to the output port 1331.

In operation, an input signal is coupled or decoupled between the gate electrodes 1 332a-1 332d and the corresponding drain electrode 1 336a-1 336d selectively in accordance with control signals fed to control gate electrodes 1 334a-1 334d on lines 29i2,,-29'2d provided 45 by suitable modification of the radar system 11 (Fig. 1). Signals on control lines 29'2,-29'2, are here logical signals. One of such signals on lines 29'2a-29'2d is selected to be in an "on" state, while the remaining ones of such signals on lines 29'2,,-29'2d are placed in an "off" state, thus placing only one FET of the FETs 1 330a-1 330d, in a conductive state and the remaining ones of such FET's 1 330a-1 330d, in a non-conductive state. Similarly the output signal from the 50 first stage is coupled or decoupled between the gate electrodes 1 372a-1 372d and the corresponding drain electrode 1 376a-1 376d selectively in response to control signals fed to control gate electrodes 1 374a-1 374d, via lines 29'2,-29i2,, as shown.

In response to a control signal fed to one of the control gate electrodes 1 334a-1 334d the corresponding one of the FET's 1 330a-1 330d is placed in a conducting state, coupling the 55 input signal on the input gate electrode of such FET, to the corresponding drain electrode of such FET. The remaining FET's of the FET's 1 330a-1 330d are held in a nonconducting state by control signals fed to remaining ones of the control gates 1 334a-1 334d. Thus, a signal coupled to the transmission line 1320 from drain electrode 1 336a will have a net phase shift of 3A(P with respect to phase of an input signal on drain electrode 1 336a, because the signal coupled from drain electrode 1 336a will pass through the three phase shift sections 1322, 1324 and 1326 of transmission line 1320 before arriving at the output port 1330. In a like manner, a signal applied from the drain electrode 1 336b to transmission line 1320 will have a net phase shift of 21, a signal applied from drain electrode 1331 c to transmission line 1320 will have an incremental phase shift of A(p, and a signal applied from drain electrode 1 336d to 65 9 GB 2 159 333A 9 transmission line 1320 will have an incremental phase shift of 0 with respect the signal on drain electrode 1 336d. Thus by selective application of control signals fed to control gates 1 334a- 1 334d an incremental phase shift of 3A0, 2Aq),AO, or 0' may be obtained. By selecting the electrical length of each incremental phase shift (A0) of the first stage equal to be 22.5, a total phase shift of up to 67.5' is provided by the first stage. The phase shift provided by the matching network 545a-545d is the same for each drain electrode matching circuit and thus does not affect the differential phase shift produced.

The output of the first stage 40a' is electrically connected to the input of the second stage 40W, as shown. The second stage 40W of the four bit digital phase 40' is identical to the first stage 40a' except for the electrical length of the transmission line 13201. In a like manner, as 10 discussed for the first stage 40a', the second stage of the four bit digital phase shifter 40' has drain electrodes, here 1 376a-1 376d electrically connected to a portion of a transmission line 1320'. The incremental phase shift of transmission line 1320' is here set to 90'. Thus, a total phase shift of 270' at the output 1331' is obtainable in the second stage 40W. This in combination with the first stage 40a' having a total available phase shift of 67.5 provides the 15 four bit digital phase shifter 40', having a capability of providing a 360' phase shift, in 22.5 increments.

Now referring to Fig. 14, a digitally controlled phase shifter section 50 suitable for use in the transceiver 1 2i (Fig. 2), by replacing T/ R switches 1 8b, 1 8d and phase shifter 40, and for transceiver 1 2i" (Fig. 4) by replacing phase shifter 44, includes the single channel phase shifter 20 40' of Fig. 13, and FET's 141 Oa-1 41 Od. Each FET 141 Oa-1 01 4d has a signal gate electrode 141 2a- 141 2d, a control gate electrode 141 4a- 141 4d, drain electrodes 141 6a- 141 5d, and source electrodes 141 8a-1 418d, as shown. FET's 141 Oa 141 Od are connected in a common (grounded) source configuration. The signal gate electrodes 141 2a, 141 2b of FET's 141 Oa, 141 Ob are here coupled to the transmission lines 32a and 32g of the transceiver 1 2i (Fig. 2) respectively, through a pair of impedance matching circuits 513, as described in conjunction with Fig. 5. Each drain electrode 141 6a, 141 6b is coupled to the phase shifter 40' via transmission line 1420. The output of the phase shifter 40' is coupled to the input gate electrodes 141 2c, 141 2d of FET's 141 Oc, 141 Od, respectively, via transmission line 1422 and 30 impedance matching circuit 513. The drain electrodes 141 6c, 141 6d are coupled to transmis- 30 sion lines 32h and 32d, respectively, of the transceiver 1 2i (Fig. 2). In operation, one of a pair of input signals fed to the signal gate electrodes 141 2a, 141 2b of input channels 1430, 1432 is selectively coupled to the corresponding drain electrodes 141 6a, 141 6b in response to signals fed to control gate electrodes 1414a, 141 4b on lines 29i, 29i, Such selectively coupled signal is fed to the phase shifter 40' and the phase of such signal is shifted in response to control signals 29'2a-29'2h as previously described. One of the pair of output channels 1434, 1436 is selected, by signals on lines 29i, 29i, fed to control gates 1414c, 1414d. The phase shifted signal, is coupled to the input gate electrodes 141 2c, 141 2d of FETs 141 Oc, 141 Od.

The phase shifted signal fed to each of the input gate electrodes 141 2c, 141 2d is coupled to one of the drain electrodes 141 6c, 141 6d selectively in response to control signals on lines 40 29i, 29i, fed to control gates 141 4c, 141 4d, respectively, as previously explained. The signal on the selected one of the drain electrodes 141 6c, 141 6d is coupled to transmission lines 32h during the receive mode or 32d of the transceiver 1 2i (Fig. 2) during the transmit mode.

Assuming one milliwatt of power consumption per FET, the power consumption of the phase shifter 50 is four milliwatts since four FET's are conducting at the same time. Two FET's of the four reciprocating switches conduct and one FET in each of stages 40a' and 40W (Fig. 13) conducts, during operation of the phase shifter. The net overall gain for the phase shifter section is approximately 4 db. This assumes a 6 db loss due to input signal division into the four channels, FET's 1 330a-1 330d of phase shifter stage 40a' (Fig. 13) and 6 db of loss due to input signal division for stage 40W (Fig. 13). In addition, there is a loss of 3 db in each stage 50 (40a', 40W) attributable to the terminating resistors 1322 for transmission lines 1320 and 1320' (Fig. 13), and there is a loss of 1 db per stage due to parasitics and the matching circuits. These losses are partially compensated for by a minimum of 8 db gain for each FET resulting in a net loss of at most 2 db per stage. Moreover, the FET switches 141 Oa- 141 Od contribute 16 db of gain (8 bd per switch, two switches active at one time). This gain is 55 reduced, however, by 3 db due to signal division into the two channels of FET's 141 Oa, 141 Od and 1 db due to parasitics and the matching circuits. Thus, the net gain for the phase shifter 50 is approximately 4 db.

Referring now to Fig. 15, an alternative embodiment of an phase shifter 4W' suitable for use in transceiver 1 2i (Fig. 2) and 1 2V (Fig. 3), includes a first phase shifter stage 40a,', a second 60 phase shifter stage 40C, and a third phase shifter stage 40c" cascade interconnected, as shown. Each phase shifter stage 40a", 40W' and 4W' is similar to the digitally controlled phase shifter stage 40a described in conjunction with Figs. 6-8. Phase shifter stage 40a" is here used, however, to provide a variable continuous phase shift between 0' and 90. Phase shifting stage 40W is used to produce a phase shift of (p = 0' or a phase shift of 0 = W, and 65 GB 2 159 333A 10 phase shifter stage 40c" is used to produce a phase shift of 0 = 0 or 0 = 180% The cascade interconnection of phase shifter stages 40a", 40b" and 40c" provides the phase shifter 40" which is capable of varying the phase of an input signal continuously over the range of 0 to 360% Referring also to Fig. 16-Fig. 17, an exemplary one of the stages 40a"- 40c" here 40a" is formed on the substrate 41 having a ground plane 43. The phase shifter stage 40a" is coupled to transmission line 32b of the transceiver 1 2i (Fig. 2). The phase shifter stage 40a" includes a transmission line 512 coupled between the input matching network 5 13 as explained in conjunction with Fig. 5 and the transmission line 32b of transceiver 12i (Fig. 2). The matching network 513 is coupled to input gate electrodes 532a, 532b of a pair of FET's 530a-530b, as 10 shown. FET's 530a-530b further include control gate electrodes 534a-534b, source electrodes 538a-538b, and drain electrodes 536a-536b. FET's 530a-530b are fabricated, such that gains and phases provided to an input signal fed to the input gate electrodes 532a, 532b are substantially equal at the drain electrodes 536a, 536b, as explained in conjunction with Fig.6.

FET's 530a-530b are here connected in a common (grounded) source configuration, as shown. 15 The control gate electrodes 534a-534b are fed voltage level control signal on control lines 29'3a, 29'3b. The radar system (Fig. 2) provides the control signals on lines 29'3., 29'3b (not shown in Fig. 2). The levels of such signals on the control lines 29'3a, 29'3b are used to control the operating point of each FET and hence the amplitude of signals coupled to the drain electrodes 536a, 536b. The drain electrodes 536a, 536b are electrically connected to capacitor 20 544 and impedance matching networks 545a, 545b as described in conjunction with Figs.

6-8. In the preferred embodiment of the invention, the impedance matching networks 545a, 545b are electrically connected to a conventional four port or quadrature coupler 1560. Such a coupler is described in an article entitled "GaAs Monolithic Lange and Wilkinson Couplers" by Raymond C. Waterman, Jr, et a[, IEEE Transactions on Electron Devices, Vol. ED-28, No. 2, February 198 1. A quadrature coupler is here used to couple input signals on each input of the coupler, in quadrature, to the output. In other words, the phase of the input signal from drain electrode 536b as coupled to the output 1570 of the coupler will lag the phase of the input signal from drain electrode 536a as coupled to the output 1570 of the coupler by 90'.

Thus, unlike prior embodiments of the invention where signals fed to the control gate 30 electrodes 534a-534b are complementary pairs of control signals, such signals provided to place an FET in an off-state or an on-state, the signals fed on lines 29'3a, 29'3b to the control gate electrodes 534a, 534b, here are selectable voltage levels between pinchoff and zero volts 11 on" levels of such FET.

An output voltage signal V, when measured at the drain electrode, of an input signal Vi fed to 35 the input gate electrode is given as: V, = AeM, is VO = BA.0---1 P), for embodiments disclosed in conjunction with Figs. 5-14 where B is the gain and ip is the phase provided to the input signal by the FET. However, if the control signals on lines 29'3ii, 29'3a fed to the control gates 534a-534b provide voltage level signals which change the operating point of the FET between the off state and the on state, the FET's 530a, 530b no longer function as switches, and, instead the FETs 530a, 530b function as variable gain amplifiers. When the output voltage V,)(A) of the FET 530a is a function of the control gate voltage V(,) fed to control gate 534a, ti-., portion of the output voltage VO, at the output of the coupler 1560 from the voltage V"(A) is given as: V. = B,A,ei(,""P+",,'n), where BA is the gain of FET 530a as a function of the control gate voltage, 164)n is the phase shift corresponding to the pathlength between the drain electrode of 45 the n th FET and the output of the coupler 1560. The output voltage of FET 530a and FET 530b may be represented as:

V.(A); VJB) where 0 V.(A) = BAA,,ei(wl + 0; VJ') = BBA.ej(," + 44 Since the quadrature coupler 1560 combines the two input signals V,, (A) and V.(B) in quadrature, the output voltage at the coupler 1560 may be represented as:

V.T = V.(A)_jV 0 (B) or VoT = BA,011 + 4, + 10.) + BA.ej(," 1 + 10.) or VoT = A,ei(""'+"A)[BA + Be -iz/2] which may be simplified to:

VoT = A.B'ej where B' = (BA2 + B B2) and tanO = 13J13A Thus, the phase of an input signal Vi (Fig. 15) is shifted in accordance with the ratio of the amplitudes V.(A), V Offi) of such input signal as coupled to each drain electrode 536a, 536b 65 GB 2 159 333A coupled in quadrature to provide the signal V,, (Fig. 15) at the output of the quadrature coupler 1560.

Thus by selecting the relative values of B, and B2 any phase between 0 and 1r/2 may be realized. Since only the ratio of B, and B2 determines thephase, it is possible to keep B' and hence the overall gain of the stage 40W' substantially constant. This is accomplished by separately adjusting the values of B, and B2. This provides an additional flexibility of amplitude control along with phase adjustment.

As an example, for a minimum phase shift increment of irl 16, the values of B, and B2 which will yield all eight phase shift increments between 0 and ff/2 with substantially constant 10 amplitude B' are given in the Table below.

TABLE

1 Phase bl b2 1 15 1 Shift 1 where:

1 1 1 1 0 1.000 0 blB' B1 v/16 0.981 0-195 1 7 /a 0.924 0.383 b2B' B2 20 1 3 w/16 0.832 0.556 1 ir14 0.707 0.707 ir 116 0.556 0.832 3 w18 0.383 0.924 7 ir /16 0.195 0-981 25 ir /2 0 1.000 The minimal phase shift increment provided by the variable phase shift stage 40a" is limited only by the degree of control of the voltage applied to the control gate electrodes 534a-534b 30 of FET 530a-530b of phase shifter stage 40a".

Phase shift stage 40a" is cascade interconnected to phase shift stage 40b", as shown. The phase shift stage 40b" is identical to phase shift stage 40a". The only difference between the stages 40a" and 40b", is the technique for producing the phase shift. A phase shift of 0 or 90' provided by phase shifter stage 40b" is determined by controlling which FET 530a-530b 35 is biased in the on state, as previously described in conjunction with Figs. 6-8.

Phase shift 40c" stage is similar to phase shift stage 40a" except for the inclusion of an additional 90 of path-length difference such as transmission line section 554b (Fig. 9b) coupled between the impedance matching network 545a and the coupler 1560.

Referring now to Figs. 18-19, bidirectional switch 1 8a having a first branch port 1 9a 40 coupled to transmission line 32a (Fig. 2), a second branch port 21 a, coupled to transmission line 32h (Fig. 2), and a common port 20a coupled to transmission line 33i, (Fig. 2), is shown.

The bidirectional switch 1 8a is formed on the substrate 41, having the ground plane 43 formed on the bottom surface of substrate 41, as shown. FETs 501 -50b are formed on a portion of the substrate 41. In the preferred embodiment, FET's 50a, 50b include a plurality of FET cells, each cell having a reactive component (C") coupled between the drain and source electrode of each cell as shown in Fig. 20. A network, here the FET 50a is formed interconnecting each one of such drain electrodes of each FET cell. Such network is formed having a characteristic impedance equal to the characteristic impedance of the transmission line sections 58a, 58b, here 50 ohms. The network is formed as follows: a length (d) of a microstrip conductor 59 having a distributed inductance per unit length (LL) and a distributed capacitance per unit length (Q is chosen such that when coupled between the cells of each FET it will provide such network with the predetermined characteristic impedance given as: Z. = (LL(CL + 2(C"/d))), /2.

The bidirectional switch further includes a pair of transmission lines 58a-58b, each having a electrical length substantially equal to one quarter of a wavelength (X, /4) where X. is the 55 wavelength of the nominal operating frequency for the circuit. The first drain electrode 54a of FET 50a is coupled between the first branch port 1 9a and to one end of transmission line 58a.

The transmission line 58a is coupled between the branch port 1 9a and the common port 20a. A drain electrode 54b of a second FET 50b is coupled to the second branch port 21 a, and one end of the transmission line 58b. The other end of transmission line 58b is coupled to the 60 common port 20a. The sources 56a-56b of FET 50a-50b are electrically connected to ground.

The gate electrodes 52a-52b of FET's 50a-50b are electrically connected to control lines 29i, 29,, and are fed complementary signals on such lines.

The T/R switch 1 8a is used to couple a signal, on transmission line 33i of the transceiver 1 2i (Fig. 2) fed to the common port 20a to one of the branch ports 1 9a or 21 a in accordance with a 6 5 12 GB 2 159 333A 12 pair of complementary control signals on lines 29i, -29i-,, fed to gate electrodes 52a, 52b. The T/R switch 1 8a couples an input signal from common port 20a to branch port 1 9a, as follows:

the control signal on line 29i, is fed to the gate electrode 52a of FET 50a, placing FET 50a in a nonconducting state; correspondingly, the control signal fed on line 29i, is applied to the gate electrode 52b of FET 50b placing FET 50b in a conducting state; by placing FET 50b in a 5 conducting state, a short circuit ()(Iow impedance path to ground) is produced at the end 58b' of transmission line 58b coupled to the drain electrode 54b; one quarter of a wavelength from this point (at the second end of transmission line 58b) the short circuit at the first end appears as an open circuit @ (high impedance) to a microwave frequency signal having a wavelength substantially similar to the wavelength of the corresponding centerband frequency of operation 10 for the bidirectional switch 1 8a. The transmission line 58a and the open circuit resulting from FET 50a being in a nonconducting state, appears as a 50 ohm transmission line at the common port side 58a' of the transmission line 58a. Thus, a signal on common port 20a is coupled to the branch port 1 9a. In a sinjLilar manner, by changing the state of the complementary pair of control signals on lines 29i, 29i, a microwave frequency signal on common port 20a may be 15 coupled to the branch port 21 a.

Having described preferred embodiments of the invention, it will now become readily apparent to those of skill in the art that other embodiments incorporating the invention may be realized. It is felt, therefore, that this invention should not be limited to the disclosed embodiments but rather should be limited only to the scope of the appended claims.

Matter described hereinbefore is described and claimed in co-pending patent application No. 8305509 from which the present application is divided.

Claims (18)

1. A transceiver element for coupling electromagnetic energy between a pair of terminals 25 comprising:

a phase shifter; a transmitter amplifier; a receiver amplifier; and a switching means for steering electromagnetic energy from one of the terminals through the 30 phase shifter, through the transmitter amplifier, and to the second terminal during a transmit mode; and for steering electromagnetic energy from the second terminal through the receiver amplifier through the phase shifter, and to the first terminal during a receive mode; such that the electromagnetic energy passes through the phase shifter in the same direction during the transmit and receive modes.

2. A transceiver element according to claim 1, wherein the phase shifter provides gain to transmitted and received electromagnetic energy as such electromagnetic energy propagates through the phase shifter.

3. A transceiver element according to claim 1, wherein the switching means comprises: a plurality of switches, each one of such switches having a common port and a pair of branch 40 ports; the common port of each one of a first pair of such switches is coupled to a corresponding one of such pair of terminals of the transceiver element; the common port of each one of a second different pair of such switches is coupled to a corresponding one of the pair of terminals of the phase shifter; the branch ports of a first one of such first pair of switches are coupled to corresponding first branch ports of each one of the second pair of switches; and the 45 branch ports of a second one of such first pair of switches are coupled by the said amplifiers to second branch ports of each one of such second pair of switches.

4. A transceiver element according to claim 1, wherein the switch means comprises: a first pair of transmission lines coupled together at a first common junction and to a first one of the pair of terminals of the radio frequency circuit; a second pair of transmission lines coupled together at a second common junction and to a first one of the pair of terminals of the phase shifter, having a first end coupled to a first end of the first pair of transmission lines, and having a second end coupled to the receiver amplifier; a third pair of transmission lines coupled together at a third common junction and to a second one of the pair of terminals of the phase shifter, having a first end coupled to a second end of the first pair of transmission fines, and having a second end coupled to the transmitter amplifier; a first pair of transistors, each transistor having output and control electrodes, with the output electrode of each one of such transistors being coupled to a corresponding end of the second pair of transmission lines; and a second pair of transistors, each transistor having output and control electrodes, with the output electrode of each one of such transistors being coupled to a corresponding end of the third pair 60 of transmission fines.

5. A transceiver element according to claim 4, wherein there is provided a switch having a common port and a pair of branch ports with the common port coupled to a second one of a pair of terminals of the transceiver, and each one of the branch ports of the said switch coupled to a corresponding one of such amplifiers.

13 GB 2 159 333A 13

6. A transceiver element according to claim 5, wherein a first control signal is fed to first transistors of each pair of transistors and a second different control signal is fed to second transistors of each pair of transistors to steer electromagnetic energy through the phase shifter and through the receiver amplifier in response to a first state of the control signals and to steer electromagnetic energy through the phase shifter and through the transmitter amplifier in 5 response to a second, different state of the control signals.

7. A transceiver element according to claim 5, wherein each one of such transmission lines has an electrical length equal to an odd multiple of a quarter of a wavelength of a corresponding operating frequency.

8. A transceiver element according to claim 1, wherein the phase shifter further comprises: 10 (i) a first independently controllable phase shifter channel having a first pair of terminals; (ii) a second independently controlled phase shift channel having a second pair of terminals; wherein the switching means further comprises:

(i) a pair of switches having a common port and a pair of branch ports; wherein the common port of each one of the switches is coupled to a corresponding one of 15 the pair of terminals of the transceiver elements, a first branch port of a first one of the switches is coupled to an input one of the pair of terminals of the first phase shift channel, a second branch port of the first switch is coupled to an output one of the pair of terminals of the second channel, and each one of the branch ports of the second switch is coupled through one of such amplifiers to a corresponding remaining one of the pair of terminals of the first and second 20 channels.

9. A microwave transceiver element susbtantially as described hereinbefore with reference to Figs. 2 or 3 of the accompanying drawings.

10. A microwave transceiver element substantially as described hereinbefore with reference to Fig. 4 of the accompanying drawings.

11. A microwave transceiver element according to claim 9 and susbtantially as described hereinbefore with reference to Figs. 5, 6, 7 and 8 of the accompanying drawings.

12. A microwave transceiver element according to claim 10 and substantially as described hereinbefore with reference to Figs. 10 and 11 of the accompanying drawings.

13. A microwave transceiver element according to claim 12 and substantially as described 30 hereinbefore with reference to Fig. 12 of the accompanying drawings.

14. A microwave transceiver element according to claim 9 and substantially as described hereinbefore with reference to Fig. 13 of the accompanying drawings.

15. A microwave transceiver element according to claim 9 or 10 and substantially as described hereinbefore with reference to Fig. 14 of the accompanying drawings.

16.. A microwave transceiver element according to claim 9 and substantially as described hereinbefore with reference to Fig. 15 of the accompanying drawings.

17. A microwave transceiver element according to claim 16 and substantially as described hereinbefore with reference to Figs. 16 and 17 of the accompanying drawings.

18. A microwave transceiver element according to any preceding claim and substantially as 40 described hereinbefore with reference to Figs. 18 to 20 of the accompanying drawings.

Printed in the United Kingdom for Her Majesty's Stationery Office. Dd 8818935, 1985. 4235Published at The Patent Office, 25 Southampton Buildings. London, WC2A lAY, from which copies may be obtained.