GB2158996A - Phased array antenna - Google Patents

Description

1

SPECIFICATION

Phased array antenna This invention relates to antenna systems and more particularly to phased array antenna systems.

As is knwon in the art, an array antenna includes a plurality of individually radiating elements. In some systems the individual radiating elements are coupled to a transmitterthrough a transmitter elementfor controlling the phase and amplitude of thetransmit ted signal. Similarly, the individual radiating elements are coupled to a receiverthrough a receiver element, for controlling the phase and amplitude of the received signal. In other systernsthe individual 80 radiating elements are coupled to both thetransmitter and receiverthrough a single element here referred to as a transceiverfor controlling the phase and ampli tude of both transmitted and received signals. The relative phase and amplitude of the microwave frequency signal passing between the plurality of radiating elements and a corresponding plurality of individual transceiver elements are controlled to obtain a desired radiation pattern. The pattern obtained is a result of the combined action of all the individual transceiver and radiating elements. Many devices such asferrite phase shifters are used to control the phase of the microwave frequency signal.

Many of such phase shifters are reciprocal, that is,the phase shift of a signal passing through one of such devices is independent of the direction which the signal passes through. In some applications it is desirableto provide an active phase shifterto provide gain to a signal passing there through. Such a phase shifter is generally inherently nonreciprocal. Thus, the use of an nonreciprocal phase shifter in a transceiver would require the use of two of such phase shifters. A developing trend in phased array antenna systems is toward production of the transceiver elements in monolithic integrated circuitform. This is desired in orderto reduce cost and sizefactors generally associated with phased array antenna systems and to provide phased array antennas adapted for certain applications where size and cost are critical such as airborne or space based radar systems.

In accordance with the present invention, a trans ceiverfor coupling a microwave signal between an antenna element and a raclarsystem, is provided.

Such a transceiver includes a plurality of switching means arranged to steer a microwave frequency signal provided bythe radarsystem through an nonreciprocal phase shifterto the phased array antenna during a transmit mode, and to steer a microwave frequency signal provided from the phased array antenna through the nonreciprocal phase shifterto the radar system during a receive mode. The microwave frequency signal passes through the phase shifter in the same direction during both the transmit and receive mode. Aset of control signals is fed to such switching means to control the steering of the microwave frequency signal between the radar system and the phased array antenna. With such arrangement, two signal paths through an active nonreciprocal phase shifter are provided. This arrangement reduces the cost and size of the trans- GB 2 158 996 A 1 ceiverelement by permitting the use of a single active nonreciprocal phaseshifter. Further, sinceeach of the elements of the transceiver element may be realized as monolithic microwave integrated circuitsthis structure results in a compact transceiver element, modularinform and less expensiveto produce.

The invention will now be described bywayof examplewith referencetothe accompanying drawings, in which:

FIG. 1 is an overall block diagram of a radar system coupled to a phasee array antenna system through a plurality of transceiver elements; FIG. 2 is a block diagram of one of the plurality of transceiver elements shown in Fig. 11; FIG. 3 is a block diagram of the transceiver element, utilizing a five port switch; FIG. 4 is a block diagram of a transceiver using a dual channel phase shifter; FIG. 5 is a block diagram of a 4-bit nonreciprocal phaseshifter; FIG. 6 is a diagrammatical view of a 180'phase shift incrementstage of a 4-bit nonreciprocal phase shifter used in the one of thetransceiver elements; FIG. 6A is an isometrieview of a bias line and output line insulated from each other with an air gap plated overlay; FIG. 613 is across sectional view of a parallel plate capacitorformed on the substrate; FIG. 7 is a block diagram of the phase shifter stage depicted in Fig. 5; FIG. 8 is a detailed schematic diagram of the phase shifter stage depicted in Fig. 5; FIGS. 9A-91) are plan views of pairs of transmission lines providing electrical pathlength differences used to realize a 4-bit phase shifter; FIG. 10 is a blockcliagrarn of a 4-bit dual channel phaseshifter; FIG. 11 is a detailed schematic of one stage of a reciprocal phase shifter; FIG. 12 is a diagrammatical view of the stage of a dual channel phase shifter depicted in Fig. 111; FIG. 13 is a detailed schematic of an alternate embodiment of a four bit nonreciprocal phase shifter; FIG. 14 is a block diagram of the nonreciprocal phase shifter of Fig. 13, including reciprocating switches; FIG. 15 is a detailed schematic diagram of a variable phase shifter utilizing a quadrature coupler; FIG. 16 is a plan view of the variable phase shifter showninFig.15; FIG. 17 is a block diagram of one stage of the n-bit variable phase shifter shown in Fig. 16; FIG. 18 is a diagrammatical view of a bidirectional three port switch; FIG. 19 is a schematic diagram of the bidirectional switch show i Fig. 18; FIG. 20 is a schematic diagram of a preferred field effect tra nsisto r FET used in the bidirectional switch: of Fig. 18.

Referring nowto FIG. 1, a phased array antenna 10 is coupled to a radarsystern 11 by a feed network 14, as.-;,,-iown. The phased array antenna 10 includes a plurality of, here n, identical transmitter/receiver (transceiver) elements 12a-1 2n, coupled to a like plurality of corresponding antenna elements 26a26n, 2 as shown. The feed network 14, here a parallel feed network, provides a signal path for a microwave signal passing from the radarsystern 11 to the phased array antenna 1 Ofortransmission to a target (not shown), and a signal path for reception of echo signals from the target (not shown) to the radar system 11. A plurality of control buses 29a-29n, 9_a49_n are provided from the radar system 11. Signals on such buses 29a- 29n,!9_a-_T9_n are used to control the transceiver elements 12a-1 2n of the phase array antenna 10. The microwave signal from the feed network 14 is coupled to each of the transceiver elements 12a-1 2n, as indicated bythe open arrows 13. The portion of microwave signal coupled to each one of the trans- ceiver elements 12a-1 2n is then coupled to the corresponding one of the antenna elements 26a-26n. Similarly, a portion of the microwave echo signal from the target is coupled to each of the antenna elements 26a-26n, the corresponding transceiver elements 12a-1 2n, and the feed network 14 as indicated by solid arrows 15, for processing bythe radar system 11. The control signals on buses 29a-29n,f9a9n during the transmit mode allow the transceiver elements 26a-26n to produce collimated and directed beams of transmit ted microwave energy and control signals on such buses during the receive mode allow such transceiver elements 26a-26n to produce collimated and directed beams of received microwave energy.

Referring nowto FIG. 2, a representative one of the transceiver elements 12a-1 2n, here transceiver ele ment 12i is shown coupled, via a transmission line 33i, to a portion of thefeed network 14 and to an antenna element26i, via a transmission line 35i, as shown.

Transceiver element 12i here includes 50 ohm trans mission lines 32a to 32h,fourtransmitter/receiver (T/R) switches 18a-1 8d, each having a common port 20a-20d, a pair of branch ports 19a-1 9d and 21 a-21 d, and a control input 22a-22d. Each one of the control inputs 22a-22d is fed by a pair of control lines 29il, M, of buses 29i, 19-i. The T/R switches 18a-1 8d are hereof a type to be further explained in conjunction with Figs.

18-19. Suffice itto say here, however, that com plementary binary or logical signals are fed to the control lines 29il, 29il, respectively, and such logical signals are used to control the electrical coupling 110 between the common port and the branch ports. Thus, for example, using an exemplary one of the T/R switches 18a-1 8d, here T/R switch 18a, such switch 18a has com mon port 20a coupled to branch port 19a in response to a f irst pair of logical states of control 115 signals fed to lines 29il, 29i, i.e. a logical 1 on line 29i, and a logical 0 on lineT9i, and such common porl:20a is coupledto branch port2la in responseto the complementary pairof logical states of the control signals fed to line 29il, Oil, i.e. a logical 0 online 29i, 120 and a logical 1 online Nil. The common port 20a of T/R switch 18a is coupled to the feed network 14, via the transmission line 33i, as shown. Branch ports 19a and 21a ofTIR switch 18a are coupled to branch ports 19d and 21 b, via transmission lines 32a and 32h, respectively. Branch port 19b of T/R switch 18b is coupled to an input of a transmitter amplifier 24, via thetransmission line 32d. The transmitter amplifier 24 is here formed on a semi-insulating substrate, here gallium arsenside (GaAs) substrate. The output of GB 2 158 996 A 2 transmitter amplifier 24 is coupled to the branch port 19c of T/R switch 18c, via transmission line 32e. The common port 20c of T/R switch 18c is coupled to the antenna element 26i, via transmission line 35i. The branch port 21 c of T/R switch 18c is coupled to an input of the receiver amplifier 28, via transmission line 32f. The receiver amplifier 28, here a low noise amplifier, is here formed on a semi-insulating substrate (here GaAs). The output of the receiver amplifier 28 is coupled to the branch port 21 d of TIR switch 18d, via transmission line 32g. The common port 20d of T/R switch 18d is coupled to the input of an active phase shifter 40, here a nonreciprocal active phase shifter having a plurality of stages (notshown, to be described in detail in connection with Figs. 5,6 and 7), via transmission line 32b. Suffice it to say here, however, that each stage of the active phase shifter includes a field effect transistor suitably biased to provide gain to the radio frequency signal passing through it. Control signals forthe active phase shifter 40 are fed thereto, via buses 29i2, T9i2 of bus 29i. The output of the active phase shifter 40 is coupled to the common port 23b of T/R switch 18b, via transmission line32c.

During a transmit mode, thetransceiver element 12i couples a microwave frequency signal from the radar system 11 to the antenna element 26i. Atransmit signal path for coupling a signal from the radarsystern 11, via feed network 14,to the antenna element 26i is depicted in FIG. 2 byan open arrow 13, as shown. In the transmit mode, the control signals on lines 29il, 29i, are used to couple each one of the common ports 20a-20d to the corresponding branch ports 19a-19d of the respective T/R switches 18a-18d. Thus a portion of the microwave signal is coupled from the radar system 11 to the input of the active phase shifter40. The active phase shifter 40 is here used to vary the phase shift of the applied microwave frequency signal by a predetermined amount in accordance with control signals on buses M229i2 which are fed to a control input 42, of the active phase shifter 40. the microwave frequency phase shifted signal is then coupled to the input of the transmitter amplifier 24. The signal atthe output of the transmitter amplifier 24 is coupled to the antenna element 26i.

During a receive mode, a portion of a received echo signal is coupled from the antenna element 26i to the radarsystern 11. A receive signal path for coupling the received echo signal from the antenna element 26i to the radarsystem 11 is depicted in FIG. 2 by solid arrows 15, as shown. During the receive mode the complementary logical states of the control signals previously on lines 29il-T9-il are nowfed to lines 29il, 29il, and such signals are used to couple each one of the common ports 20a-20d to the branch ports 21 a-21 d of the respective T/R switches 18a-18d. Thus the echo signal is coupled from the antenna element 26i to the receiver amplif ier 28. The signal atthe output of the receiver amplifier 28 is coupled to the input of the active phase shifter element40. The signal passing through the phase shifter is again phase shifted in accordance with the control signals fed on the buses 29i2-29i2. The phase shifted signal produced atthe output of the active phase shifter element 40 is then coupled to the radar system 11, via the feed 3 GB 2 158 996 A 3 network 14. Thus it is noted that the microwave frequency signal is coupled through the active phase shifter40 in the same direction for both the transmit mode and the received mode. Thus referring again to FIG. 1 in a similar manner, each of the plurality of transceiver elements 12a-1 2n are used to couple a portion of a microwave signal between the radar system 11, via the feed network 14 and the plurality of antenna elements 26a-26n, to produce in combination a collimated and directed beam (not shown) during the transmit mode and the receive mode.

Referring nowto FIG. 3 an alternative the embodi ment of a transceiver element 12i'suitable for use in the phased array antenna 10 of FIG. 1 is shown coupled to a portion of the feed network 14 and the antenna element 26i. Transceiver element 12i'here includes a five port switch 310, the active phase shifter 40, the transmitter amplifier 24, the receiver amplifier 28, and the three portT/R switch 18c, as shown. The five port switch 310 isformed on a substrate, (not shown) here semi-insulating gallium arsenide (GaAs) having a ground plane (not shown) here plated gold formed on the bottom surface of the substrate.

Formed in active regions on portions of the top surface of the semi-insulating substrate are FET's 50a-50d 90 here GaAs FETs, each having gate electrodes 52a-52d (Fig. 3), a drain electrode 54a-54d and a source electrode 56a-56d. The gate electrodes 52a, 52d of FET's 50a, 50d, are connected to control line 29il, and the gate electrodes 52b, 52cof FET's 50b, 50c are connected to control line 19-il, as shown. The FET's are here connected in a common (grounded) source configuration. The T/R switch 310 further includes transmission lines 60a-60f. Each transmission line 60a-60f has an electrical length, corresponding to one 100 quarter wavelength (X,,/4), where Xr is the wavelength of the corresponding nominal or operating center band frequency (f,,) of the circuit. The feed network 14 is electrically connected to a first end 60a, of;kc/4 transmission line 60a and a first end 60f, of Ac/4 transmission line 60f, via transmission line 33i. The drain electrode 54c of FET 50c is electrically connected to a second end 60a2 of Ac/4transmission line 60a. A first end 60b, of A.14 transmission Ii e 60b is electrically connected to the second end 60a2 of transmission line 60a and drain electrode 54c. Asecond end 60b2 of Ac/4 transmission line 60b is electrically connected to the input port of the active phase shifter 40, via transmis sion line 32b and to a first end 60d, of,\c/4transmis sion line 60d. The second end 60d2 of transmission line 50d is electrically connected to the output of the receiver amplifier 28 and to the drain electrode 54d of FET50d. A second end 60f2 of A,/4 transmission line 60f is electrically connected to a first end 60e, of AJ4 transmission line 60e, and drain electrode 54a of FET 50a. A second end 60e2 of Ac/4 transmission line 60e is coupled to the output of the active phase shifter40, via transmission line 32c and to a first end 60c, of A,/4 transmission line 60c. A second end 60C2 of A,/4 transmission line 60c is coupled to the input of the transmitter amplifier 24 and to the drain electrode 54b of FET 50b. The connections of transmitter amplifier 24 and receiver amplifier 28 to T/R switch 18d are the same, as explained above in conjunction with FIG. 2.

During the transmit mode, as shown bythe open arrows 13 a logical control signal on line 29i, of bus 29i is fed to the gate electrodes 52a, 52d of FETs 50a, 50d and the complement of such logical control signal is fed (via linef6i, of busY9-i) to gates 52b, 52c of FETs 50b, 50c. In response to such signals FET's 50a, 50d are placed in a conducting state and FET's 50b, 50c are placed in a nonconducting state. The A,/4transmission lines 60d, 60e and 60f have ends 60d2,60e, and 60f2 electrically connected to FET's 50 a and 50b, as previously described. When FET's 50a, 50d are placed in a conducting state, a short circuit (low impedance path to ground designated by 0) is produced atthe ends 60d2,60e, and 60f2 of transmission lines 60d-60f coupled to the FET's 50a, 50d. One quarter wavelength therefrom (atthe second end 60dl, 60e2, and 60f, of each transmission line 60d-60f) the short circuits at ends 60d2,60el, 60f2 appear as opn circuits (high impedance pathsto ground designated by@) at ends 60di, 60e2,60fl, to a microwave frequency signal having a wavelength substantially equal to the wavelength of the corresponding nominal or centerband frequency of operation, forthe transceiver. Thus, no signal path is provided during the transmit mode through line 60f and the transmitted energy passes through lines 60a and 60b. Further because end 60d, appears as an open circuit @, thetransmitted energy passes from line 60b through line 32b, through the phase shifter40 and through line 32c. Since end 60e2 appears as an open circuit@ thetransmitted, and now phase shifted energy passes through line 60c, transmitter amplifier 24,T/R switch 18c and to the antenna 26i, as previously described in conjunction with FIG. 2.

During the receive mode as shown by the closed arrows 15, the control signal on lines 29il, 2791, are switched (or complemented) in logic state placing FET's 50a and 50d in a nonconducting state, and placing FET's 50b and 50c in a conducting state. The ends 60a2,60bl, and 60C2 of the A,/4 transmission lines 60a, 60b and 60c which are coupled to the drain electrodes 54b and 54c of FET's 50b and 50d are thus coupled to ground a e the other ends 60al, 60b2, and 60c, of thetransmission lines 60a, 60b, and 60c present impedances corresponding to open circuits.

Thus, a received microwave signal from antenna element 26i is coupled to the output of the receiver amplifier 28 as explained in conjunction with FIG. 2. The received signal is then coupled through transmission line 60d to the active phase shifter element40.

The signal on the output of the active phase shifter 40 is thus coupled to the radarsystem 10 through transmission lines 60e and 60f.

Referring nowto Fig. 4, an alternative embodiment of a transceiver, here transceiver 12i" suitablefor use in the phased array antenna 10 of FIG. 1 is shown coupled to a portion of the feed network 14, via transmission line 33i and to the antenna element 26i, via transmission line 35i, as shown. Transceiver element 12i" includes TIR switches 18a and 18c, transmitter amplifier 24, receiver amplifier 28. Here, however, a dual channel active phase shifter44 is provided. Dual channel active phase shifter 44 has a plurality of cascade interconnected phase shift stages here 44a-44d of a type to be further described in detail in conjunction with Figs. 10-12. The T/R switch 18a has 4 common port 20a coupled to the feed network 14via transmission line 33i. Branch ports 19a and 21 a of T/R switch 18a are coupled to the input 47a of a first channel 47 and the output 49b of a second channel 49 of dual channel phase shifter44, respectively, as indicated. The output 47b of the first channel 47 is coupled to the input of the transmitter amplifier 24, via transmission line 32b. The output of the receiver amplifier 28 is coupled to the input 49a of the second channel 49, via transmission line 32e. The connection 75 of the transceiver 12i" to antenna element 26i (FIG. 1) is as previously explained.

During the transmit mode, as shown by the open arrows 13, in response to complementary control signals on lines 29i,,Y9-il a microwave signal see to common port 20a from the radar system 11 is coupled to branch port 19a. Such signal from branch port 19a is coupled to the input47a of the dual channel phase shifter44. The signal is shifted in phase and coupled to the transmitter amplifier24 and to the antenna 26, as previously described. During a receive mode, as shown by the closed arrows 15, in response to the complements of the previous control signals on lines 29i,,'29i the microwave signal fed to the common port 20cfrom antenna 26i is coupled to the branch port 21 c and thus to the receiver amplifier 28. The signal atthe output of the receiver amplifier 28 is fed to the input 49a of the phase shifter44. The signal shifted in phase isthen fed to theT/R switch 18a to the radar system 11, as previously described.

Referring nowto FIG. 5, a single channel digitally controlled phase shifter40 suitableforuse in trans ceiverelement 12i (Fig. 2) and transceiver element 12i' (Fig. 3) isshown to include a plurality of cascade interconnected stages40a-40d with like parts of each 100 stage being designated bythe same numeral.An exemplary one of such stages40a-40d, here stage40a, is discussed in detail in conjunction with FIGs. 6-8.

Referring nowto FIG. 6, the phase shifter stage 40a is formed on a substrate 41 here GaAs having a ground 105 plane 43, as shown. Referring also to FIGS. 7,8 the phase shifter stage40a includes a microwave trans mission line 512, here having an impedance of 50 ohms, coupled to an input impedance matching circuit 513. Transmission line 512 is here fed by a microwave 110 frequencysignal from transmission line 32b (Fig. 2).

Input impedance matching circuit 513 is here used to match the input impedance of the phase shifterstage 40ato the charactertic impedance of the transmission line 512. The input matching circuit 513, here includes 115 a first transmission line section 514, having a react ance which is primarily induitive, coupled in shuntto the input transmission line section 512, via a bottom plate 526c of a capacitor 526. Bottom plate 526c of capacitor 526 is coupled to one end of the shunt mounted transmission line section 514. The upper plate 518a of a second series connected capacitor 518 is coupled to line 516 and the bottom plate of 518 is coupled to ground by a via hole 518b, as shown.

Ground pad 522 is coupled to ground by a via hole connection 522a. As shown in Fig. 613, capacitor526 is formed on the.op surface of the substrate 41 here includes a top plate 526a which is coupled via an air bridge 526d to the strip conductor portion of a transmission line 528. Aligned underthis top plate is a130 GB 2 158 996 A 4 bottom plate 526c of evaporated gold formed on the substrate 41. The top plate 526a and bottom plated 526c are separated by a 5000 Angstrom (A) layer 526b of silicon nitride (Si3N4). The bottom plate 526c has a finger 526e (Fig. 6) which is used to connectthe second circuit element, here transmission line section 514, to the capacitor 526. The connection is provided by a metal to metal contactwhich couples to the bottom plate 526c. A second transmission line section 516, here having a reactance which is primarily inductive is coupled in shunt between capacitors 518 and 526. The connection of capacitor 518 to inductor section 516 provides the bias feed 520 forthe gate electrode. The input matching circuit 513 further includes thethird transmission line section 528 here also having a reactance which is primarily inductive, connected between thejunction of capacitor 526with shunt mounted transmission line section 516 and a common inputjunction 532. The phase shifterstage 40a further includes a FETswitch 530 having a dual gate FET, 530a-530b, as shown. FET's 530a and 530b include first gate electrodes 532a-532b coupled to the common junction 532, second gate electrodes 534a, 534b, separate drain electrodes 536a, 536b and separate source electrodes 538a, 538b. FETs 530a, 530b are here connected in a common (grounded) source configuration. FET 530a, 530b are fabricated such thatthe gains and phases provided by each FET to signals fed to the gate electrode and coupled tothe drain electrode are substantially equal. In other words, IS21 la, thefraction of power coupled to the drain electrode 536a of 530a from a signal on gate electrode 532a substantially equals, IS21 b,the fraction of power available atthe drain electrode 536b of FET 530bfrom an incident input signal provided signal gate electrode 532b of FET530b. Similarly, tP S21 la IP S21 1b that is,the phases of the instantaneous power delivered to each drain electrode of FET 530a, 530b are substantially equal. Control gate electrodes 534a, 534b arefed control signals on lines 29i2a, 29i2a (Fig. 2). These control signals are used to control the coupling of an input signal fed to the gate electrode 532a, 532b to the corresponding drains 536a, 536b of FET's 530a, 530b. High frequency components in the signals on control lines 29i2a,29i2a are shorted to ground, via capacitors 527a, 527b. The drain electrodes 536a, 536b are electrically connected to identical impedance matching circuits 545a-545b, as shown. The matching circuits 545a (Fig. 8), here includes a first transmission line section 548a coupled in series between the drain electrode 536a and coupling capacitor 552a. A second transmission line section 549a is coupled in shunt with the junction of the first transmission line section 548a, the bottom plate of capacitor 552a, and an upper plate of a dc blocking capacitor 544. The bottom plate of the dc blocking capacitor 544 is connected to ground by a via hole connection 544a (Fig. 6). The impedance matching circuit 545b is formed in a similar manner on the substrate 41 (Fig. 6) forthe drain electrode 536b.

The impedance matching ci rcuit 545b includes a transmission line section 548b, a coupling capacitor 552b, and a second transmission line section 549b, coupled to the drain electrode 536b in a similar manner as the corresponding elements of impedance matching circuit 545a. The common connection of transmission line sections 549a-549b and the dc blocking capacitor 544 provides the bias feed 546 for drain electrodes 536a, 536b. As shown in Fig. 6A, the bias feed 542 here is insulated from the transmission line section 548b by a conventional air gap plated overlay. In general, such overlays are here used in all embodiments to insulate such crossing signal paths. The upper plates of coupling capacitors 552a-552b of the impedance matching circuits 545a, 545b respec- tively, are integrallyformed with the strip conductor portion of transmission lines 554a and 553, respectively. Transmission line 554a has an electrical length which provides a phase shift 01 + AO. to an input signal coupled thereto and transmission line 553 has an electrical length which provides a phase shift of 01 80 to an input signal coupled thereto. Such pair of transmission lines 554a, 553 as shown in FIG. 9a and described in more detail hereinafter provides one path having an unique phase shift increment AOa. Each second end of transmission line section 554a, 553 is coupled to a corresponding input port 565,567 of a conventional three port coupler, which couples power from two input ports and provides the coupled power to an output port, via branch arms 564,566. Such a coupler is described in an article entitled "GaAs Monolithic Lange and Wilkinson Couplers" by Raymond C. Waterman Jr. et al, IEEE Transactions on Electron Devices, Vol. ED-28, No. 2, February 1981. The output of the three port coupler is electrically connected to an output port 570. Capacitors 518,526, 544,552a, 552b, 527a and 527b are hereformed in a similar manner, as explained for capacitor 526.

In operation, an input signal fed totransmission line 512 is coupledto each gate electrode 532a, 532b. Such signal is coupled to one of the drain electrodes 536a, 536b selectively in accordancewith the control signals fed on lines 29i2a,19i2atO the control gate electrodes 534a, 534b. If the inputsignal in response to such control signals on lines 29i2a, 29i2a is coupled to drain electrode 536a,the phase of such signal is shifted by anamount 01 + AOathrough transmission line 554a.

Conversely,the electrical path from drain electrode 536btothe coupler 560 provides a pathlength correspondingto a phase shiftof OI.Thus, is in response to the control signals on lines 29i2a, 29i2a, the 110 input signal is coupled to drain electrode 536b, the phase of such signal at the output 570 is shifted by an amount of 01 through transmission line 553. Thus, a phase shift of an input signal of 01 or 01 +AO,,atthe output of570 is selected in response to control signals 115 on lines 29iz,,Ai2a. A plurality ofsuch stages are cascade interconnected to form the phase shifter40 (Fig. 5). Each stage has two paths which correspond to phase shifts of an input signal of 01 through one path an amount 01 + A01 through the second path where i isthe number ofthe stage. For, fourcascade interconnected stages, the phase shift A01 foreach stage is here AOa 180', AOb 90'f AOc = 45and AOd = 22.5'.

Referring again to FIG. 5, with I ike parts in each 125 stage being designatee by the same numeral, the active non reciprocal phase shifter 40 used to produce an output signal at port 570d having a predetermined phase shift relative to an input sig nal on transmission line 512 includes four cascade interconnected phase 130 GB 2 158 996 A 5 shifter stages 40a-40d, as shown. Each phase shifter stage40a-40d realized in accordancewith Figs. 6-8, selectively provides a unique phase shiftto an input signal of AO, = 180', A0b = 90', A0c = 45'and A0d = 22.5', respectively. Each phase shift stage includes a unique length of transmission line between output matching circuit 545a and the three port coupler 560. Each length of transmission line, in conjunction with the length of transmission line 553, provides each stage with a unique pathlength difference corresponding to the unique phase shift. In response to control signals on lines 29i2a-29i2d, and 9i2a-19i2d seictive combinations of phase shift increments of O'or 180% O'or 90', O'or 45'and O'or 22.5'are provided by phase shifter stages 40a- 40d, respectively of control signals fed by lines 296 to 29i2d and 196 to 2182d are represented byAto D and A to D respectively. The phase shift 0 of an input signal through phase shifter 40 may be represented bythefollowing logical equation as: 0 = [(A(Oi + A0a) + A (01)) + (13(01 + A0b) + B (01D + (C)01 + AO, ) + C (01)) + (D(O1 + A0d)+ D (01)1. The phase shifter 40, thus, is used to vary the phase of a signal fed to transmission line 512 of stage 40a from 0 to 360'in here 22.5' phase shift increments.

Referring nowto FIGS. 9A913 transmission line sections 553 and 554a-554d used to provide unique incremental phase shifts for stages 40c-40d respectively, of the phase shifter 40b shown in FIG. 5, have likeparts being designated bythesame numeral.The transmission lines 553 and 554a-554d arecoupledto the input ports 565,567 of the three portcoupler560, having athinfilm load resistor562and branch arms 564,566, and to a portion of the impedance matching networks 545a-545b, as shown. The transmission lines 554a-554d are formee on the semi-insulating substrate41 by strip conductors 555a-555d and 557, respectively, and the ground plane 43, which is separated by a dielectric, here the semi-insulating substrate41. Strip conductors 555a-555d and 557 are designed to provide the corresponding transmission lines 554a-554d and 553 each with a 50 ohm characteristic impedance. The transmission lines 554a-554d each have an electrical length equal to a correspond ing precise fractional wavelength A,12% with respectto transmission line section 553, whereh, isthe wavelength of the nominal or centerband operating frequency (fc) forthe active phase shifter n is the total number of stages. Thus, transmission line section 554a has a pathiength (AO.) equal to AJ2 with respect to transmission line section 553. In a similar manner, the pathlengths for segments 554b-554d with respect to transmission line 553 are Ac/4, AJ8, and Ac/1 6. Thus, the transmission lines 554a-554d, with respectto transmission line section 553, here represent pathlength differences corresponding to a phase shift of an applied signal with respecttothe phase of such signal of 180', 90% 45'and 22.5', respectively.

Referring nowto FIG. 10, a dual channel phase shifter44 having channels 47 and 49which is suitable for use in thetransceiver 12i--- shown in FIG. 4 includes fourone bit phase shifterstages (P.S. Stages) 44a-44d cascade interconnected together, as shown. The dual channel phase shifter stages 44a-44d are here identical exceptforthe pathlength differences (phase shift 6 GB 2 158 996 A 6 increment) (AOi) forming the phase shift networks of each stage. Each channel of the dual channel phase shifter provides one of two signal paths, such path being selected in response to control signals fed on lines 29i2a-29i2d and f9i2a-!9i2d- Such paths provide 70 either a phase shift of 01 ora phase shift of 01 + AOi where i isthe number of the stage. The phase shift increment (AOi) for each of the fourstages 44a-44d shown in FIG. 10 are 180', 'Wb = 900,90', We = 45' and AOd = 22.5'fo r stages 44a-44d, respectively as 75 explained in conjunction with Figs. 9a-9d.

Referring nowto FIG. 11, an exemplary one of such phase shifterstages, here phase shifterstage 44a is shown. The phase shifterstage 44a includes FET's 530a-530d each having a pair of gate electrodes 80 532a-532d, and 534a-534d, a drain electrode 536a 536d, and a common source electrode 538. FETs 530a-530d are here realized as a double pole double throw FETswitch 530 of a type disclosed in U.S. Patent No. 4,313,126 filed May 21,1979, and assigned to the 85 assignee of this invention. Each of the FET's 530a-530d are here connected in a common (grounded) source configuration, as shown. Each FET 530a-530d is formed on the substrate 41 within close proximityto the other FET's 530a-530d, as shown. FETs 530a-530d are 90 fabricated such that gains and phases provided to an input signal are subsequently equal, as explained in conjunction with Figs. 6-7.

Thefirst phase shifter channel 47 includes a microwave transmission line 512, here coupledto the 95 transceiver 12i" (Fig. 4), via transmission line 32a providing a signal inputforthe phase shifter stage 44a. The microwave transmission line 512 is electrical ly connected to an impedance matching circuit5l3a previously described in conjunction with FIGS. 6-8.

Matching circuit 513 is electrically connected to the common inputjunction 532. lnputjunction 532 is coupled to input gate electrodes 532a, 532b of FET's 530a, 530b, respectively. Signals fed on lines 29i2a, 29i2afrom the radarsystem 11 (Fig. 1) are fed to the second gate electrodes 534a, 534b for controlling the conduction of an input sigrral on input gate electrodes 532a, 532b to the corresponding drain electrodes 536a, 536b of FET 530a, 530b, respectively. High frequencysi - 1-nal components on control signals fed on 110 lines 29i2a, T9i2a are shorted to ground by capacitors 527a, 527b. An inputsignal fed equallyto input gate electrodes 532a, 532b is selectively coupled,to the corresponding drain electrode 536a, 536b, in accord ance with the control signals on lines 29i2a, 29i2a fed to the control gate electrodes 534a, 534b. The drain electrode 536a is electrically connected to an impe dance matching network 545a as described in con junction with FIGS. 5-7. The drain electrode 536b is similarly, electrically connected to the impedance matching network545b, as shown. The impedance matching network 545a is coupled to here,the microwave transmission line 554a. In a similar man ner, the impedance matching network 545b is coupled tothe microwave transmission line 553a. Each second end oftransmission lines 553a and 554a is coupled to the pair of inpL;E ports 565,567 ofthe conventional three port coupler 560.

The second channel 49 of digital phase shifter stage 44a includes microwave transmission line 512'cou- 130 pled to transceiver 12i" (FIG. 4) via transmission line 32g (Fig. 2) for providing the signal input for channel 49. The microwave transmission line 512'is electrically connected to an impedance matching circuit 513'as previously disclosed in conjunction with FIGS. 5-7. A second matching circuit 513'is electrically connected to a common junction 532'. Common junction 532'is electrically connected to input gate electrodes 532c, 532d of FET's 530c, 530d. Control gates 534c, 534d of FET 530c, 530d are electrically connected to gate electrode pads 524 and 527, respectively. The control gates 534c, 534d are fed signals on lines 29i2,, '29i2, from the radar system 11 (Fig. 1) for controlling conduction of an input signal on input gate electrodes 532c, 532d to the drain electrodes 536c, 536d of FET's 530a, 530b, respectively. Drain electrodes 536c-536d are electrically connected to impedance matching networks 545c-545d as disclosed in conjunction with FIGS. 6-8. Transmission lines 553'and 554a', are coupled between the impedance matching networks 545c-545d and the three port coupler560'. Thethree port coupler 560'is electrically connected to output port 570'.

The total pathlength difference of the connection of drain electrode 536a to the three port coupler 560, for channel 47 is then selected to provide a corresponding phase shift equal to 01 + Wa, as explained in conjunction with FIGS. 9a-9d. The total pathlength difference of the connection of drain electrode 536b to the three port couplerfor channel 47 is selected to provide a corresponding phase shift equal to 01. Thus, the phase of a signal applied to the gate electrodes 532a, 532b is shifted by an amount 01 + AOa or 01 selectively in accordance with control signals fed to control gate electrodes 534a, 534b. In the same manner, transmission lines 553', 554a'provide pathlengthsto channel 49 between drains 536c, 536d of 01 +,&Oaor0l.

Referring again to Fig. 10,the dual channel phase shifter44 having channels 47 and 49 has stages 44a-44d, each stage providing a unique phase shiftto an applied signal. Each channel provides selective combinations of phase shift increments AOa = 180', AOb = 90', AOr = 45', and 1&Od = 22.5'in response to control signals on lines 29i2a- 29i2d, 29i2a -'-29i2dReferring nowto FIG. 12,the phase shifterstage 44a is shown,formed on a semi-insulating substrate 41 having a ground plane 43 on one side thereof, as shown. A low inductance ground connection 537 is here made through the source electrode region 538. Parallel plate capacitors such as 526 areformed on the substrate 41, as previously described in conjunction with FIG. 6B. Crossing signal paths are insulated one from another by conventional air gap plated overlays as described in conjunction with FIG. 6A.

Referring also to FIG. 5, the net overall gain for each four bit phase shifter40 and 44'is approximately 8 decibels (db) or approximately 2 db perstage. Each stage contributes 3 db of loss from splitting of the input signal and another 3 db of loss due to power losses due to parasitic losses and the matching networks are less than 1 db. Allowing for substantial mismatch, a gain of approximately 8 db generally is realizable from a dual gate FET, operating at X-band, for example. Thus, a net gain of approximately 2 db 7 per stage or approximately 8dbforthe phase sifters of FUG. 9 and FIG. 12 is realized. Since only four FETs, one per stage, at any given time are operating for each phase shifter, 40,44the d.c. power consumption will be fourtimes that for one FET.

Now referring to FIG. 13, an alternative embodiment for a four bit digitally controlled phase shifter40' suitable for use in transceivers 12i and 12i'(Fig. 2 and Fig. 3) includes a first stage 40a'having a single pole fourthrow (SP4T) FET switch 1330 and a second stage 40b'having an SP4T FETswitch 1370, as shown. The SP4T FETswitches 1330 and 1370 are here of a type disclosed in the above mentioned U.S. Patent No.

4,313,126. Each stage 40a', 40b'isformed on a substrate (notshown), having a ground plane (not shown).

The first stage 40a'of thefour bit digital phase shifter40'further includes FET's 1330a-1330d, as shown. FET's 1330a-1330d arefabricated such that gains and phases providedto an inputsignal are substantially equal, as explained in conjunction with Fig. 5-7. Each FET 1330a-1330d, includes a input gate 1332a-1332d, a control gate 1334a-1334d, drain elec trodes 1336a-1336d and a source region 1338. FET's 1330a-1 330d are here connected in a common (grounded) source configuration. A low inductance ground connection is here made from the source electrode 1338to the ground plane 43 (not shown) by a conventional via hole connection.

A microwave transmission line 512, here having an 95 impedance of 50 ohms is coupled to an impedance matching circuit 513, as previously explained in conjunction with FIGS. 4-6. The impedance matching circuit is coupled to input gate electrodes 1332a 1332d. The drains 1336a-1 336d are electrically con nected to identical impedance matching networks 545a-545d of a type previously described in conjunc tion with FIG. 8. Impedance matching networks 545a-545d are each coupled to a transmission line 1320 having a characteristic impedance Z., here 50 ohms. Transmission line 1320 istermi atee at one end in a resistor 1322, here having a value equal to 50 ohms, the characteristic impedance of the transmis sion line 1320. The resistor 1322 is coupled in shunt between thetransmission line 1320 and ground. Drain 110 electrode 1336d is electrically connected to the end of transmission line 1320through the impedance match ing network 545d. Drain 1336c of FET 1330c is electrically connected to transmission line 1320, through the matching network 545c defining a section115 of transmission line 1326, drain electrode 1336b of FET 1330b is electrically connected to transmission line 1320 through the matching network 545b defining a section of transmission line 1324, and drain electrode 1336a of FET 1330a is electrically connected to transmission line 1320, through the matching network 545a, defining a section of transmission line 1322. Here, all the transmission line sections 1322-1326 have the same electrical length and thus each section shifts the phase of an applied signal by an equal amount. The total phase shift of an output signal with respectto the phase of the input signal fed through transmission line 512 is the sum of the phase shifts provided by each of the equal electrical length transmission line sections 1322,1324 and 1326 of GB 2 158 996 A 7 which the outputsignal passesthrough from a selected one of the drain electrodes 1336a-1336d to the output port 1331.

In operation, an input signal is coupled or decou- pled between the gate electrodes 1332a-1 332d and the corresponding drain electrode 1336a-1336d selectively in accordance with control signalsfed to control gate electrodes 1334a-1 334d on lines 29i2a-29i2d provided by suitable modification of the radar system 11 (Fig. 1). Signals on control lines 29i2a-29i2d are here logical control signals. One of such signals on lines 29i2a-29i2d is selected to be in an "on" state,whilethe remaining ones of such signals on lines 29i2,,-29i2d are placed in an "off" state, thus placing only on FETof the FETs 1330a-1330d, in a conductive state and the remaining ones of such FET's 1330a-1330d, in a non-conductive state. Similarlythe outputsignal from the firststage is coupled or clecoupled between the gate electrodes 1372a-1372d and the corresponding drain electrode 1376a-1376d selectively in responseto control signalsfed to control gate electrodes 1374a1374d, via lines 296,-296, as shown.

In responseto a control signal fed to one of the control gate electrodes 1334a-1 334d the correspond- ing one of the FET's 1330a-1 330d is placed in a conducting state, coupling the input signal on the input gate electrode of such FET, to the corresponding drain electrode of such FET. The remaining FET's of the FET's 1330a-1330d are held in a nonconducting state by control signalsfedto remaining ones of the control gates 1334a-1 334d. Thus, a signal coupled to thetransmission line 1320from drain electrode 1336a will have a net phaseshiftof 3AOwith respectto phase of an input signal on drain electrode 1336a, because the signal coupledfrom drain electrode 1336a will passthrough thethree phase shift sections 1322,1324and 1326 oftransmission line 1320 before arriving atthe output port 1330. In a like manner,a signal applied from the drain electrode 1336b to transmission line 1320 will have a net phase shift of 2AO, a signal applied from drain electrode 1331 c to transmission line 1320 will have an incremental phase shift of AO, and a signal applied from drain electrode 1336d to transmission line 1320 will have an incremental phase shift of 00with respectthe signal on drain electrode 1336d. Thus by selective application of control signals fed to control gates 1334a-1 334d an i iremental phase shift of 3AO, 2AO, AO, or O'may be obtained. By selecting the electrical length of each incremental phase shift (WAO) of the first stage equal to be 22.5", a total phase shift of up to 67H is provided bythe first stage. The phase shift provided by the matching network 545a-545d isthe samefor each drain electrode matching ciriuit and thus does not affectthe differential phase shift produced.

The output of thefirst stage 40a'is electrically connected tothe input of the second stage 40b', as shown. The second stage 40b'of the four bit digital phase 40'is identical to the first stage 40a'exceptfor the electrical length of the transmission line 1320'. In a like manner, as discussed forthe first stage 40a', the zacond stage of the four bit digital phase shifter40' has drain electrodes, here 1376a-1 376d electrically connected to a portion of a transmission line 1320'.

The incremental phase shift of transmission line 1320' 8 is here set to 90'. Thus, a total phase shift of 270' at the output 133Vis obtainable in the second stage 40b'.

This in combination with the first stage 40a'having a total available phase shift of 67.5'provides the four bit digital phase shifter40', having a capability of 70 providing a 360'phase shift, in 22.5' increments.

Now referring to FIG. 14, a digitally controlled phase shifter section 50 suitable for use in thetransceiver 12i (Fig. 2), by replacing T/R switches 18b, 18d and phase shifter40, and fortransceiver 1 2i--- (Fig. 4) by replacing phase shifter44, includes the single channel phase shifter40'of FIG. 13, and FET's 141 Oa-1 41 Od. Each FET 141 Oa-1 014d has a signal gate electrode 1412a-1412d, a control gate electrode 1414a-1 414d, drain electrodes 1416a-1416d, and source electrodes 1418a-1418d, as shown. FET's 141 Oa 1410d are connected in a cthmo (grounded) source configuration. The signal gate electrodes 1412a, 1412b of FET's 141 Oa, 141 Ob are here coupled to the transmission lines 32a and 32g of the transceiver 12i (FIG. 2) respectively, through a pair 85 of impedance matching circuits 513, as described in conjunction with FIG. 5. Each drain electrode 1416a, 1416b is coupled to the phase shifter40'via transmis sion line 1420. The output of the phase shifter40'is coupled tothe input gate electrodes 1412c, 1412d of 90 FET's 1410c, 1410d, respectively, via transmission line 1422 and impedance matching circuit 513. The drain electrodes 1416c, 1416d are coupled to transmission lines 32h a d 32d, respectively, of the transceiver 12i (FIG. 2). In operation, one of a pair of input signals fed 95 to the signal gate electrodes 1412a, 1412b of input channels 1430,1432 is selectively coupled to the corresponding drain electrodes 1416a, 1416b in re sponse to signals fed to control gate electrodes 1414a, 1414b on lines 29i,,fg-il. Such selectively coupled 100 signal is fed to the phase shifter 40'and the phase of such signal is shifted in response to control signals 29i2,,-29i2h as previously described. One of the pair of output channels 1434,1436 is selected, by signals on lines 29i,,19-il fed to control gates 1414c, 1414d. The 105 phase shifted signal, is coupled to the input gate electrodes 1412c, 1412d of FETs 141 Oc, 141 Od. The phase shifted signal fed to each of the input gate electrodes 1412c, 1412d is coupled to one of the drain electrodes 1416c, 1416d sele ctively in response to 110 control signals on lines 29il, f9-il fed to control gates 1414c, 1414d, respectively, as previously explained.

The signal onthe selected one of the drain electrodes 1416c, 1416d is coupled to transmission lines 32h during the receive mode or32d of the transceiver 12i 115 (FIG. 2) during the transmit mode.

Assuming one milliwatt of power consumption per FET, the power consumption of the phase shifter 50 is four milliwatts since four FET's are conducting atthe same time. Two FET's of thefour reciprocating 120 switches conduct and one FET in each of stages 40a' and 40b'(FIG. 13) conducts, during operation of the phase shifter. The net overall gain forthe phase shifter section 50 is approximately 4 db. This assumes a 6 db loss due to inputsignal division into the four channels, 125 FET's 1330a-1330d of phase shifterstage 40a'(FIG. 13) and 6 db of loss dueto input signal division for stage 40b'(FIG. 13). In addition, there is a loss of 3 db in each stage (40a', 40b') attributable to theterminating resistors 1322 for transmission lines 1320 and 1320' 130 GB 2 158 996 A 8 (Fig. 13), andthere is a loss of 1 db perstage dueto parasiticsandthe matching circuits.These losses are partially compensated for by a minimum of 8 db gain foreach FETresulting in a netloss of at most2 db per stage. Moreover,the FETswitches 1410a-1410d contribute 16 db of gain (8 db perswitch,two switches active atonetime). This gain is reduced, however, by3 db duetosignal division intothetwo channels of FET's 1410a, 1410d and 1 db dueto parasitics andthe matching circuits. Thus,the netgainforthe phase shifter5O is approximately 4 db.

Referring nowto FIG. 15, an alternative embodimentof an phase shifter40" suitableforuse in transceiver 12i (Fig. 2) and 12i'(Fig. 3), includes a first phase shifter stage 40a", a second phase shifter stage 40b", and a third phase shifter stage 40c" cascade interconnected, as shown. Each phase shifter stage 40a", 40b" and 40c" is similarto the digitally controlled phase shifter stage 40a described in conjunction with FIGS. 6-8. Phase shifter stage 40a" is here used, however, to provide a variable continuous phase shift between 00 and 900. Phase shifting stage 40b'is used to produce a phase shift of 0 = Vor a phase shift of 0 = 90', and phase shifter stage 40c" is used to produce a phase shift of 0 = O'or 0 = 180'. The cascade interconnection of phase shifter stages 40a", 40b" and 40c" provides the phase shifter40" which is capable of varying the phase of an input signal continuously overthe range of O'to 360'.

Referring also to Fig. 16 - Fig. 17, an exemplary one of the stages 40a"40c" here 40a" is formed on the substrate 41 having a ground plane 43. The phase shifter stage 40a" is coupled to transmission line 32b of the transceiver 12i (FIG. 2). The phase shifter stage 40a" includes a transmission line 512 coupled between the input matching network 513 as explained in conjunction with FIG. 5 and the transmission line 32b of transceiver 12i (FIG. 2). The matching network 513 is coupled to input gate electrodes 532a, 532b of a pair of FET's 530a-530b, as shown. FET's 530a-530b further include control gate electrodes 534a-534b, source electrodes 538a-538b, and drain electrodes 536a536b. FET's 530a-530b are fabricated, such that gains and phases provided to an input signal fed to the input gate electrodes 532a, 532b are substantially equal at the drain electrodes 536a, 536b, as explained in conjunction with FIG. 6. FET's 530a-530b are here connected in a common (grounded) source configuration, as shown. The control gate electrodes 53a-534b arefed voltage level control signals on control lines 29i3a, 29i3b. The radar system (Fig. 2) providesthe control signals on lines 29i3a, 29i3b (notshown in Fig. 2). The levels of such signals on the control lines 29i3a, 29i3b are used to control the operating point of each FET and hence the amplitude of signals coupled to the drain electrodes 536a, 536b. The drain electrodes 536a, 536b are electrically connected to capacitor 544 and impedance matching networks 545a, 545b, as described in conjunction with FIGS. 6-8. In the preferred embodiment of the invention, the impedance matching networks 545a, 545b are electrically connected to a conventional four port or quadrature itupler 1560. Such a coupler is described in an article entitled "GaAs Monolithic Lange and Wilkinson Couplers" by Raymond C. Waterman, Jr. et al, IEEE 9 Transactions on Electron Devices, Vol. ED-28, No. 2, February 1981. A quadrature coupler is here used to couple input signals on each input of the coupler, in quatrature, to the output. In otherwords, the phase of the input signal from drain electrode 536b as coupled 70 to the output 1570 of the couplerwill lag the phase of the input signal from drain electrode 536a as coupled to the output 1570 of the coupler by 90'.

Thus, unlike prior embodiments of the invention where signals fed to the control gate electrodes 534a-534b are complementary pairs of control signals, such signals provided to place an FET in an off-state or an on-state, the signals fed on lines 29i3,, 29i3b to the control gate electrodes 534a, 534b, here are selectable voltage levels between pinchoff and zero volts "on" 80 levels of such FET.

An outputvoltage signal V., when measured atthe drain electrode, of an input signal Vi fed to the input gate electrode is given as: Vi = Aoej")', is V, = BA.0"P), for embodiments disclosed in conjunction 85 with FIGS. 5-14where B isthe gain and tp isthe phase provided tothe input signal bythe FET. However, if the control signals on lines 29i3a, 29i3afedto the control gates 534a-534b provide voltage level signalswhich changethe operating point ofthe FET between the off 90 state and the on state, the FET's 530a, 530b no longer function as switches, and, instead the FETs 530a, 530b function as variable gain amplifiers. When the output voltage V.w)wqfu2A) of the FET 530a is a function of the control gate voltage V(g) fed to control gate 534a, 95 the portion of the output voltage V,t at the output of the coupler 1560 from the voltage VO(A) is given as: V.

= BAA,e j(wt+LP+AOn), where BA isthe gain of FET 530a as a function of the control gate voltage, AOn isthe phase shift corresponding to the pathlength between the 100 drain electrode of the n th FET and the output of the coupler 1560. The output voltage of FET530a and FET 530b may be represented as:

VO (A); V,)(B) where VOW = BAAoej("0; VO(B) = B13A,,ej('+P) 105 Since the quadrature coupler 1560 combines the two input signals VO(A) and VO(B) in quadrature, the output voltage atthe coupler 1560 may be represented as:

VoT VOW _ jVO(B) or VoT = BAA,,ei("'q"AOA) + B,3A,,ei("t+"AOB) or VoT = A.J+q"A) [B, + 1313e -i"121 which may be simplified to:

V.T = A.'BW9 where B'= (BA 2 + B 132) 1/2 and tan E) = BB/BA. Thus, the phase of an inputsignal Vi (Fig. 15) is shifted in accordancewith the ratio of the amplitudes V 0 iA), VO (B) of such inputsignal as coupled to each drain electrode 536a, 536b coupled in quadratureto provide the signal Vt (Fig. 15) at the output of the quadrature coupler 1560.

Thus by selecting the relative values of B, and B2 any phase between 0 and 7T12 may be realized. Since onlythe ratio of B, and B2 determines the phase, it is possible to keep B'and hence the overall gain of the stage 40a" substantially constant. This is accomplished by separately adjusting the values of B, and B2. This provides an additional flexibility of amplitude control along with phase adjustment.

As an examplejor a minimum phase shift incre- GB 2 158 996 A 9 ment of 7T/16, the values of B, and B2 which will yield all eight phase shift increments between 0 and;T/2 with substantially constant amplitude B'are given in the Table below.

TAB1X 1 Phase 11 h, -T Shift where- 0 1.000 w/16 0.921 W 18 0.924 3 w/16 0.832 1 w14 1 0.707 1 5 W 116 1 o.ssr.

1 3718 1 0.383 7 Y 116 1 0.195 w/2 1 0 1 0 1 0-383 0.556 0.707 0.832 0.924 0.981 1.000 b1B, - B1 b2B - B2 The minimal phaseshift increment provided bythe variable phase shiftstage40a" is limited only bythe degree ofcontrol of the voltage applied to thecontrol gate electrodes 534a-534b of FET 530a-530b of phase shifter stage 40a".

Phase shift stage 40a" is cascade interconnected to phase shift stage 40b" as shown. The phase shift stage 40b" is identical to phase shift stage 40a". The only difference between the stages 40a" and 40b", is the technique for producing the phase shift. A phase shift of O'or 90' provided by phase shifter stage 40b" is determined by controlling which FET 530a-530b is biased in the on state, as previously described in conjunction with Figs. 6-8.

Phase shift40c- stage is similarto phase shift stage 40a" exceptforthe inclusion of an additional 90'of pathlength difference such as transmission line section 554b (Fig. 9b) coupled between the impedance matching network 545a and the coupler 1560.

Referring nowto FIGS. 18-19, bidirectional switch 18a having a firstbranch port 19a coupledto transmission line 32a (Fig. 2), a second branch port 21 a, coupled to transmissit line 32h (Fig. 2), and a common port 20a coupled to transmission line 33i, (Fig. 2), is shown. The didirectional switch 18a is formed on the substrate 41, having the ground plane 43 formed on the bottom surface of substrate 41, as shown. FETs 50a- 50b areformed on a portion of the substrate 41. In the preferred embodiment, FET's 50a, 50b include a plurality of FETcells, each cell having a reactive component (C-) coupled between the drain and source electrode of each cell as shown in Fig. 20. A network, here the FET 50a is formed interconnecting each one of such drain electrodes of each FET cell. Such network is formed having a characteristic impedance equal to the characteristic impedance of the transmission line sections 58a, 58b, here 50 ohms. The network is formed as follows: a length (d) of a microstrip conductor 59 having a distributed inductance per unit length (LL) and a distributed capacitance per unit length (CL) is chosen such that when coupled between the cells of each FET itwill provide such networkwith the predetermined characteristic;m.pe dance given as: ZO = (LL(CL + 2 (C-/d)))112. The bidirectional switch further includes a pairof trans mission lines 58a-58b, each having a electrical length substantially equal to one quarter of a wavelength (A,/4) whereX, is the wavelength of the nominal operating frequencyforthe circuit. The first drain electrode 54a of FET 50a is coupled between thefirst branch port 19a and to one end of transmission line 58a. The transmission line 58a is coupled between the branch port 19a and the common port 20a. A drain electrode 54b of a second FET 50b is coupled to the second branch port 21 a, and one end of the transmis- sion line 58b. The other end of transmission line 58b is coupled to the common port 20a. The sources 56a-56b of FET50a-50b are electrically connected to grou d. The gate electrodes 52a-52b of FET's 50a-50b are electrically connected to control lines 29il, 29il, and arefed complementary signals on such lines.

The T/R switch 18a is used to couple a signal on transmission line 33i of the transceiver 12i (Fig. 2) fed to the common port 20a to one of the branch ports 19a or 21 a in accordance with a pair of complementary control signals on lines 29il, f9- il, fed to gate electrodes 52a, 52b. The T/R switch 18a cou ples an input signal from common port 20a to branch port 19a, as follows: the control Sig nal on I ine 29ii, is fed to the gate electrode 52a of FET 50a, placing FET 50a in a nonconducting state; correspondingly, the control signal fed on linef5ii is applied to the gate electrode 52b of FET50b placing FET50b in a conducting state; by placing FET50b in a conducting state, a short circuit @ (lowimpedance path to Ground) is produced atthe end 58b'of transmission line 58b coupledto the drain electrode 54b; one quarterof a wavelength from this point (atthe second end of transmission line 58b) the short circuit atthe first end appears as an open circuit @ (high impedance) to a microwave frequency signal having a wavelength substantially similarto the wavelength of the corresponding centerband frequency of operation forthe bidirectional switch 18a. The transmission line 58a andthe open circuit resulting from FET50a being in a nonconducting state, appears as a 50 ohm transmission line atthe common portside 58a'of thetransmission line 58a. Thus, a signal on common port20a is coupled to the branch port 19a. In a similarmanner, by changing the state of the complementary pairof control signals on lines 29il, 19-il, a microwave frequency signal on common port 20a maybe coupled tothe branch port 21a.

Having described preferred embodiments of the invention, itwill now become readily apparentto those of skill in the artthat other embodiment incorporating the invention may be realized. It isfelt, therefore, thatthis invention should not be limited to the disclosed embodiments but rathershould be limited onlytothe scope of the appended claims.

Matterdescribed hereinbefore is described and

Claims (4)

claimed in co-pending patent application No. 8305509 from which the present application is divided. CLAIMS

1. A phased array antenna for producing collimated and directed beams of transmitted and re- ceived electromagnetic energy comprising:

an array of antenna elements; a plurality of transceiver elements each one of such elements being coupled to a corresponding one of such antenna elements each one of the transceiver elements comprising:

a phase shifter; and a switching means for steering electromagnetic energy provided by a common feed through the phase shifterto the corresponding antenna element during a transmit mode and for steering electromagnetic GB 2 158 996 A 10 energy from the corresponding antenna elementto the commonfeed during a receive mode.

2. A phased array according to claim 1, wherein the phase shifter of each of such transceiver elements is independently controllable to provide a selected phase shiftto both transmitted and received electromagnetic energy.

3. A phased array according to claim 1, wherein the switching means provides a pair of signal paths between a terminal of each one of such transceiver elements and the corresponding antenna elements.

4. A phased array according to claim 3, wherein each transmitter element further comprises: a transmitting amplifier; a receiving amplifier; and wherein the transmitting amplifier is disposed in a first one of such signal paths and the receiving amplifier is disposed in a second one of such signal paths.

Printed in the United Kingdom for Her Majesty's Stationery Office, 8818935, 11185, 18996. Published at the Patent Office. 25 Southampton Buildings, London WC2A lAY, from which copies may be obtained.