GB2162345A - Digital multiplier - Google Patents

Abstract

A digital multiplier for multiplying together two binary numbers includes a linear array of bit processing cells. Each cell has two input connections (Ia, Ib) to which are applied successive bits of the two numbers, and two output connections (Oa, Ob) by means of which the successive bits are applied to the next cell. Each cell also includes multiplying means (G) for multiplying together one bit of each number, and an adder (AD) operable to add together and store the results of successive multiplication operations. <IMAGE>

Description

SPECIFICATION Digital multiplier This invention relates to digital multipliers, and in particular to such multipliers which are particularly suitable for large scale integration in integrated circuit form.

Many of the operations required in signal or image processing, such as correlation, convolution and filtering are not best performed on a computer of conventional achitecture. The basic requirement for these operations is the ability to multiply together streams of pairs of numbers and to accumulate a total. In binary representation, numbers with a 32 bit wordlength possess sufficient precision for current and future signal processing operations while the use of 64 bit products will minimise rounding errors in the accumulating process.

The reason for the inefficiency in executing algorithms for the signal processing operations mentioned above rises from the repeated passing of a single data item back and forth between a memory and a processor. One very attractive approach for the processiing of continuous streams of data is to use a systolic array of processing elements. Such a systolic array is used as a special purpose processor attached to a general purpose host computer, thus leaving the host computer available to perform its more general purpose functions.

Clearly, such a special purpose processor must be able to deliver the results of its processing operation to its host computer at a rate compatible with the incoming stream of data. The systolic array approach achieves this by making the maximum use of pipelining and parallelism, and by making full use of each data item as it passes through a given configuration of relatively simple, locally connected processing elements.

In the case of the signal processing operations mentioned above, the basic function of each identical processing element is to multiply together pairs of numbers (whose wordlength is -sufficiently large to provide an acceptable level of precision) and to accumulate the sum of the products.

Known systolic arrays require an array of identical multiplying cells each of which multiplies one bit of each of the numbers to be multiplied together. British patent application 2,1 06,278A, for example, describes an arrangement involving a rectangular array of cells each of which is connected to each adjacent cell in the array. However, in such an array the number of cells in the array increases as the square of the number of bits in each number to be multiplied. Hence for useful word lengths the number of cells may become very large. This is of importance particularly because the fastest operation would be obtained from a multiplier contained on a single silicon chip, since inter-chip connections introduce time delays.

It is an object of the invention, therefore, to provide a digital multiplier of the "pipelined" type in which the number of multiplying cells increases only linearly with the size of the numbers to be multiplied.

According to the present invention there is provided a digital multiplier for multiplying together two binary numbers, which includes a linear array of bit level processing cells each comprising two input connections to respective ones of which are applied successive bits of each of the two binary numbers, two output connections connected to the next adjacent cell and to which are applied said successive bits, multiplying means operable to multiply together one bit of each of said numbers, and adder means operable to add together and store the results of successive multiplication carried out in the cell.

Preferably the number of cells in the linear array is equal to the sum of the number of bits in the two numbers to be multiplied together.

The invention will now be described with reference to the accompanying drawings, in which: Figure 1 is a logic diagram of bit processing cell according to a first embodiment of the invention; Figure 2 is a schematic diagram showing the interconnection of a simple array of the bit processing cells of Fig. 1 to form a digital multiplier; Figure 3 illustrates the operation of the digital multiplier of Fig. 2; Figure 4 is a logic diagram of a bit processing cell according to a second embodiment of the invention; Figure 5 illustrates the operation of a multiplier comprising an array of the bit processing cells of Fig. 4; Figure 6 shows an example of the operation of the multiplier of Fig. 4; and Figure 7 shows a block diagram of signal processing apparatus incorporating a plurality of digital multipliers.

Referring now to Fig. 1, this shows one form of bit processing cell according to the invention.

The cell shown is to be used for multiplying together two numbers 'a' and 'b', and the data flow for the two numbers is in opposite directions. The cell shown has three data inputs marked la, Ib and Ic, the latter being for any "carry" bit generated by the preceding cell in the array. Each of these inputs is connected to a separate edge-triggered bistable latch, shown as L1, L2 and L3. To each latch is also connected a clock pulse signal CK. The output of latch L1 forms the 'a' data output to the next following cell to the right by way of output connection Oa, and is also connected to one input of a two-input AND gate G. The output of latch L2 is connected to the other input of gate G and also forms the 'b' data output to the next following cell to the left by way of output connection Ob.

The output of the AND gate G is connected to an adder AD, along with the output of latch L3. A "carry" output from the adder AD forms the "carry" output c' to the next following cell to the right by way of output connection Oc. A "read" signal RD may be applied to the adder AD to cause the adder to apply its contents to a data output DO.

In operation, one bit of each of the numbers 'a' and 'b' is applied to the AND gate G when a clock pulse or "beat" is applied to each of the latches L1 and L2. Multiplication of two singlebit binary numbers is in fact simply AND-ing, since when either or both of the numbers is zero then the product is also zero. The output of the AND gate G is retained in the adder AD. Any 'carry' bit from the preceding cell is also applied to the adder, and any resulting 'carry' is applied immediaely to the next following cell.

When the entire multiplication operation to be performed by the array has been completed, the 'read' signal RD is applied to each adder in the array in sequence, causing successive bits of the result of the multiplication operation to be read out onto a data highway. Further circuitry may be added to deal with sign extraction and the clearing of the stores prior to the start of a further multiplication operation.

Fig. 2 shows how a number of the bit processing cells described may be connected together to form a multiplier. The number of bit processing cells must bve at least equal to the sum of the numbers of bits in each of the two numbers. For example the multiplication of two three-bit numbers requires six cells, shown in Fig. 2 as C1 to C6. The "read" and output connections are also shown and labelled RD1 to RD6 and DC1 to DC6 respectively.

Fig. 3 illustrates the operation of the multiplier in multiplying together two three-bit numbers.

The drawing shows the multiplier operation for each of nine successive beats, the multiplier being shown for each beat with the positions of the bits of the two numbers shown as a1, a2, a3 and bt, b2 and b3 respectively, bits a3 and b3 being the most significant bits of the respective numbers.

The multiplication of two three bit numbers is shown below:~ b3 b2 b x a3 a2 a, =i h g f e d where d = a1b, e = a1b2 + a2b1 + any carry from d f = a,b3 + a2b2 + a3b1 + any carry from e g = a2b3 + a3b2 + any carry from f h = a3b3 + any carry from g i = any carry from h.

Hence each bit of one number is mutiplied in turn by each bit of the other number. The two numbers will usually be available on separate data highways at the same time, and it is necessary for the bits of one number, in this case 'b', to be applied in reverse order. It will be seen that the first cell shown, C1, is a "dummy" cell in that no multiplication takes place.

Referring now to Fig. 3, the least significant bit a1 of number 'a' is applied to the 'a' input of cell C1. On the second beat a1 moves to cell C2 but there is still no 'b' input. On the third beat a1 moves to cell C3, bit a2 is applied to cell C1 and the most significant bit b3 of number 'b' is applied to cell C6. On the forth beat a1 moves to cell C4 as does b3, and hence the product a1b3 is stored in the adder of cell C4. Also on the fourth beat b2 is applied to cell C6 and a2 moves to cell C2.

The bits of the 'a' and b'b numbers continue to move along the array of cells, and each time one bit of each number appears in the same cell a product is formed as stored in the adder of that cell. In each of the storage operations any "carry" generated is passed to the next adjacent cell to the right. The process continues until each bit of one number has been multiplied by each bit of the other number. It will be seen that after beat 8 the adder of each one of the cells contains one of the numbers d to i given above, except for cell C1.

The result of the multiplication operation is obtained by reading out the contents of the adder of each cell in sequence, starting with cell C6.

In the embodiment just described the bits of the two numbers moved in opposite directions through the array of bit processing cells with bits being applied on alternate beats. This, of course, requires that both numbers are present at the same time and probably that one is stored in a register until the other is available.

A second embodiment describes an arrangement suitable for the case where the numbers appear one at a time on a highway. Fig. 4 shows the arrangement of one bit processing cell for such an embodiment. This is similar to the cell of Fig. 1 except for the addition of an extra latch L4 between the output of latch L2 and the 'b' output connection Ob. In addition, both numbers are shown entering the cell in the same direction. The effect of the latch L4 is to delay the application of each bit of the 'b' number by one clock pulse or beat with respect to the bits of the 'a' numbers, as will be described below.

Fig. 5 illustrates the operation of an array of the cells of Fig. 4, for multiplying together two three-bit numbers. The extra delay provided for each bit of the 'b' number is represented by a square box in one corner of the symbol representing the cell.

Referring now to Fig. 5, the most significant bit b3 of the number 'b' is applied to that input of the cell CD to which the additional one-beat delay is applied. On the second beat bit b3 is held by this delay unit whilst bit b2 is applied to the cell CD. On the third beat bit b3 is passed to cell C1, bit b2 is held in the delay unit of cell CD, and least significant bit b1 is applied to cell CD. The bits of number 'b' continue to move along the array of cells at the rate of one cell every two beats. On the fourth beat the least significant bit a1 of number 'a' is applied to cell CD, moving on to cell C1 on the next beat as bit a2 is applied to cell CD. Bit a1 is present in cell C1 at the same time as bit b1 and hence the product a1b1 is determined and stored in the adder in cell C1.

On the sixth beat bit a1 passes to cell C2 at the same time as bit b2, and hence the product a1b2 is determined and stored in cell C2. On the seventh beat bits a1 and b3 are multiplied in cell C3, whilst bits a2 and b1 are multiplied in cell C2, the product being added to that of bits a1 and b2 already contained in the adder. Any resulting "carry" is passed to cell C2.

The process continues as shown in Fig. 5 until each bit of one number has been multiplied by each bit of the other number. It will be seen that after beat 11 the adder of each of the cells C1 to C6 contains the sums of the products set out above, except that cell C6 will only contain any product from cell C5.

The result of the multiplication operation is obtained by reading out the contents of the adder of each cell in sequence, starting with the most significant bit in cell C6.

Fig. 6 shows an example of the operation just described, involving the multiplication of the numbers 111 and 101. The actual digits of each number have been written into the blocks and the results of the multiplications are shown underneath the appropriate blocks. The final output is shown at the bottom of the diagram as 100011, with the arrows denoting a "carry" from the adder of one cell to that of the next cell.

As already stated, the technique described above requires only a number of bit processing cells at least equal to the sum of the number of bits in the two numbers, and multipliers of the two forms described are intended for the multiplication of large numbers.

Digital multipliers of the types described above may be put to a number of uses. For example, the multiplication of two matrices is a common requirement in digital signal processing.

Consider, for example, the following matrix multiplication:~

where each number is itself a multiple-bit number.

then:- c11 = a,,b1, + a,2b2, + a,3b3, c,2 = a"b,2 + a12b22 + a,3b32and so on.

Such a calculation may readily be performed by using an array of multipliers of the type already described. For the matrix multiplication set out above an array of nine digital multipliers is required, as shown in Fig. 7. The nine digital multpliers DM1 to DM9 each comprise a linear array of bit processing cells as already described. The nine multipliers are arranged in a three by three array so that as each number passes through one multplier it is passed on bit by bit to the next multiplier in the same row or column. The drawing also shows the order in which the numbers are applied to the matrix of multipliers. Shown in each box representing a multiplier is the result of the calculation determined by that multiplier, for example DM3 calculates the result C13 of the final matrix.

It will be seen from Fig. 7 that the numbers a11 and b11 are first applied to multiplier DM1, which determines the product of these two numbers. When this has been done the number a passes to multiplier DM2, where it is multiplied by b12, whilst b11 passes to multiplier DM4 where it is multiplied by a22. At the same time a,2 and b21 are applied to multiplier Do 1. The product a12b2, is determined in multiplier DM1 and added to the product a1,b1, already stored there. The multiplication proceeds step by step until each of the 'a' numbers has been multiplied by each of the 'b' numbers. The final results are read out of the nine multipliers in the desired sequence.

Since each digital multiplier is not only multiplying together two n-bit numbers but is also adding together the results of three such multiplications, each multiplier will have to comprise more than 2n cells, since there may be 'carry' bits. In fact, if there are 'm' products to add together, then the number of cells N in each cell in each multiplier is given by N = 2n + (m - 1) In the case of the matrix multiplication given above, where each result is the addition of three multiplications (i.e. m = 3) and where each number is a 32-bit number (i.e. n = 32) then, for each of the nine digital multipliers, N = 66. This means that each multiplier comprises a linear array of 66 cells, and not the 64 which are sufficient for the multiplication of two 32-bit numbers.

Matrix multiplication is only one example of the many uses to which a digital multiplier according to the invention may be put.

Claims (10)

1. A digital multiplier for multiplying together two binary numbers, which includes a linear array of bit level processing cells each comprising two input connection to respective ones of which are applied successive bits of each of the two binary numbers, two output connections connected to the next adjacent cell and to which are applied said successive bits, multiplying means operable to multiply together one bit of each of said numbers, and adder means operable to add together and store the results of successive multiplication operations carried out in the cell.

2. A multiplier as claimed in Claim 1 in which first and second bistable latch devices are connected one between each of the input connections and the corresponding one of the output connections.

3. A multiplier as claimed in Claim 2 in which the multiplier means comprises an AND gate having two inputs connected one to the output of each of the first and second latch devices.

4. A multiplier as claimed in any one of Claims 1 to 3 in which the adder means of each bit processing cell except the first cell in the array has a carry input connected to the preceding cell by way of a bistable latch device.

5. A multiplier as claimed in any one of Claims 1 to 4 in which the adder means of each bit processing cell except last cell in the array has a carry output connected to the next following cell.

6. A multiplier as claimed in any one of the preceding claims which includes delay means operable to delay the application of each successive bit of one of said numbers to the appropriate output connection by a predetermined time interval relative to each successive bit of the other of said numbers.

7. A multiplier as claimed in Claim 6 in which the delay means includes a third bistable latch device connected between the output of said second latch device and the corresponding output connection.

8. A multiplier as claimed in any one of the preceding claims in which the number of cells in the array is at least equal to the sum of the number of bits in each of the two binary numbers to be multiplied together.

9. A multiplier as claimed in any one of Claims 1 to 8 which includes readout means operable to extract from the adder in each bit processing cell the number stored therein when the multiplication of said two binary numbers has been completed.

10. A digital multiplier substantially as herein described with reference to the accompanying drawing.