FR2568034A1 - DIGITAL MULTIPLIER - Google Patents

Abstract

A DIGITAL MULTIPLIER FOR MULTIPLYING TWO BINARY NUMBERS BETWEEN THEM, INCLUDES A LINEAR BIT PROCESSING MATRIX. EACH CELL CONTAINS TWO IA, IB INPUT CONNECTIONS TO WHICH SUCCESSIVE BITS OF TWO NUMBERS ARE APPLIED, AND TWO OA, OB OUTPUT CONNECTIONS BY MEANS OF WHICH SUCCESSIVE BITS ARE APPLIED TO THE FOLLOWING CELL. EACH CELL ALSO INCLUDES G MEANS FOR MULTIPLYING A BIT WITH EACH OF THE NUMBERS, AND AN ADDITIONER CAPABLE OF ADDING AND STORING THE RESULTS OF SUCCESSIVE MULTIPLICATIONS.

Description

The invention relates to digital multipliers, and in particular to

  multipliers that are particularly suitable for integration into

  large scale in integrated circuits.

  Many of the operations required for signal or image processing, such as correlation, convolution and filtering, are not performed at

  -best on a conventional architecture computer.

  The basic requirement for these operations is the ability to multiply streams of pairs of numbers and accumulate a total. In binary representation, numbers having a word length of 32 bits have a

  sufficient precision for the processing operations

  present and future signals, while the use of 64-bit products will minimize rounding

in the cumulative process.

  The reason for the inefficiency in the execution of the algorithms of the signal processing operations mentioned above stems from the repeated trips of the same data element between a memory and a processor. A very interesting approach for

  the treatment of continuous data flows is the use of

  of a contracted matrix of

  is lying. Such a contracted array is used as a particular processor attached to a general-purpose host computer, thus leaving the computer in a hurry.

  available to perform its more general functions.

  It is obvious that such a particular processor

  link must be able to deliver the results of its processing operations to its host computer at

  a speed compatible with the incoming data flow.

  This is accomplished by the contracted matrix approach by making maximum use of serial combinations.

  parallel, and making full use of each

  data transfer as it passes through a certain

  configuration of relatively simple processor elements

ples and connected locally.

  In the case of the signal processing operations mentioned above, the basic function of each identical processor element is to multiply pairs of numbers (the word length of which is sufficiently large to give an acceptable level of precision), and to accumulate the sums

some products.

  Known contracted matrices require an array of identical multiplier cells, each of which multiplies one bit of each of the numbers to be multiplied together. The patent application

  British Patent No. 2,106,278, for example, discloses a disclosure

  position involving a rectangular matrix of cells, each of which is connected to each adjacent cell in the network. However, in such a matrix, the number of cells in the network increases as the square of the number of bits in each number to be multiplied. Therefore, for the usual word lengths, the number of cells can become very large. This is of particular importance because the fastest operation would be achieved with a multiplier contained on a single silicon chip, since the connections between chips

introduce delays.

  It is therefore one of the objects of the invention to propose a numerical multiplier of the type

  "series" in which the number of multiplying cells

  trices increases only in linear size

numbers N multiply.

  According to the invention, a multiplier is proposed

  numerically to multiply together two binary numbers

  res, comprising a linear array of bit-level processing cells, each including two

  input connections to which

  the successive bits of each of the two binary numbers, two output connections connected to the next adjacent cell and to which the successive bits are applied, multiplication means which act to multiply together a bit of each of the numbers, and means of multiplication. addition that act to add together and store the results of the successive multiplications performed in the

cell.

  The number of cells in the linear network is preferably equal to the sum of the numbers of bits

  in the two numbers to multiply.

  The invention will now be described in

  referring to the accompanying drawings, in which: FIG. 1 is a logic diagram of a bit processing cell according to a first embodiment of the invention; Fig. 2 is a schematic diagram showing the interconnection of a simple matrix of bit processing cells of Fig. 1 to form a digital multiplier; Figure 3 illustrates the operation of the digital multiplier of Figure 2; FIG. 4 is a logic diagram of a bit processing cell according to a second embodiment of the invention; Fig. 5 illustrates the operation of a multiplier comprising a bit processing cell array of Fig. 4;

  Figure 6 shows an example of the function-

  multiplier of Figure 4; and Figure 7 shows a flowchart of a signal processing apparatus comprising a certain

  number of digital multipliers.

  Referring to Figure 1, we see a

  bit processing cell form according to the invention.

  tion. The cell shown should be used to multiply two numbers "a" and "b" together, and the data streams of the two numbers arrive in opposite directions. The represented cell has three

  data entries marked Ia, Ib and Ic, this last

  being done for the "hold" bits generated by the previous cell of the network. Each of these

  Inputs are connected to a bistable flip-flop

  triggered, separated, marked L1, L2 or L3. Each flip-flop also has a clock pulse signal CK. The output of the flip-flop L1 constitutes the output of the data "a" towards the next nearest cell on the right via the output connection Oa, and is also connected to an input of a double-input AND gate. G. The output of flip-flop L2 is connected to the other input of gate G, and is also the output of data "b" to the next nearest cell on the left.

  via the output connection Ob.

  The output of the AND gate G is connected to an adder circuit AD, as well as the output of the

  flip-flop L3. A "hold" output of the add-on circuit

  neur AD constitutes the "held" output c 'towards the

  next nearest cell on the right through

  mediate the Oc output connection. A signal of

  "read" RD can be applied to the circuit addition-

  neur AD to cause the spill of its contents

to an output of data DO.

  In operation, a bit of each of the numbers "a" and "b" is applied to the AND gate G when a clock pulse or "top" is applied to each of the latches L1 and L2. The multiplication of two single-bit binary numbers consists of simply doing the AND operation, since when one or both numbers are zero the product is also zero. The output of the AND gate G is stored in the adder circuit AD. Any "hold" bit of the previous cell is also applied to the circuit

  adder, and any resulting restraint is applied

  immediately to the next nearest cell. When the entire multiplication operation to be performed by the network has been completed, the read signal RD is sequentially applied to each adder circuit of the network, causing the flow of

  successive bits of the result of the operation of multi-

  plication to a data bus. Other circuits can be added to extract the signs and reset the memories before starting a

  new multiplication operation.

  Figure 2 shows how a number of bit processing cells of the described model can be connected together to form a multiplier. The number of bit processing cells must be at least equal to the sum of the number of bits in each of the two numbers. For example, the multiplication of two three-bit numbers requires six cells, marked in Figure 2 from C1 to C6. "Read" and output connections are also represented

  and labeled RD1 to RD6 and RO1 to RO6 respectively.

  Figure 3 illustrates the operation of the multiplier when it multiplies between them two three-bit numbers. The drawing shows the operation of the multiplier for each of nine successive tops, the multiplier being represented for each top with the positions of the bits of the two numbers respectively labeled a1, a2, a3 and b1, b2 and b3, the bits a3 and b3 being the bits of larger weights of the respective numbers. The multiplication of two numbers of three bits is represented below: b3 b2 b1 x a3 a2 a1 = ihgfedod = a1b1 e = a1b2 + a2b1 + possible retention of df = a1b3 + a2b2 + a3b1 + possible retention of eg = a2b3 + a3b2 + possible retention of fh = a3b3 + possible retention of gi = possible retention of h. It follows that each bit of one of the numbers is multiplied in turn by each bit of the other number. The two numbers will generally be obtained on two separate data buses, at the same time, and the bits of one of the numbers, in this case "b",

  are applied in reverse order. We will see that the first

  miter cell represented, Cl, is a "fictional" cell

  which does not perform any multiplication.

  Referring now to FIG. 3, the least significant bit a1 of the number "a" is applied to the input "a" of the cell Ci. At the second top, a1 passes into the cell C2 but there is no no entry "b" yet. At the third top, a1 passes into cell C3, bit a2 is applied to cell C1 and the second top bit of larger weights b3 of the number "b" is applied to cell C6. At the fourth top, a1 passes into cell C4, as well as b3, and therefore product a1b3 is stored in the adder circuit of cell C4. Also at the fourth top b2 is applied to cell C6, and a2 goes into the

cell C1.

  The bits of the numbers "a" and "b" continue to pass in the cell network, and each time a bit of each of the numbers appears in the same cell,

  a product is made and stored in the cir-

  baked adder of this cell. During each storage operation, the holdings made are passed to the next nearest cell on the right. The process continues until each bit of one of the numbers has been multiplied by each bit of the other number. It will be seen that after the top 8, the adder circuit of each of the cells contains one of the numbers d to i mentioned above, except for

the cell Cl.

  The result of the multiplication operation

  is obtained by reading in sequence the contents of the cir-

  cooked adders from each cell, starting

by cell C6.

  In the embodiment that has just been

  describe, the bits of the two numbers went

  opposing views across the cell network of

  bit processing, the bits being applied alternately

  tops. This naturally requires that both numbers be present at the same time, and probably,

  that one of them be stored in a register

  until the other is available.

  A second embodiment has a

  provision where the numbers appear

  feel at different times on a bus. Figure 4 shows the arrangement of a bit processing cell for such an embodiment. This is similar to the cell of FIG. 1, except for the addition of an additional flip-flop L4 between the output of the flip-flop L2 and the connection Ob of the output "b". Moreover, we see that the numbers enter the cell in the same direction. The effect of the flip-flop L4 is to delay the application of each bit of the number "b" of a clock pulse, or of a peak with respect to the

  bits of the number "a", as will be described below.

  Figure 5 illustrates the operation of a

  cell network of FIG. 4, during the multi-

  one by the other of two three-bit numbers. The extra delay given to each bit of the number "b" is represented by a square in a corner

  the symbol representing the cell.

  Referring now to FIG. 5, the largest weight bit b3 of the number "b" is applied to the input of the CD cell to which the additional delay of a top is applied. At the second top, bit b3 is retained by this delay circuit, while bit b2 is applied to cell CD. At the third top, the bit b3 goes to the cell C1, the bit b2 is retained in the delay circuit of the cell CD, and the bit of least weight b! is applied to the CD cell. The bits of the number "b" continue to pass through the cell array at the rate of one cell every two tops. At the fourth top, the least significant bit a1 of the number "a" is applied to the CD cell, and passes to the

  cell C1 at the next top, when bit a2 is applied

  to the CD cell. The bit a1 is in the cell C1 along with the bit b1 and therefore the product a1b1 is performed and stored in the memory.

  adding circuit of the cell C1.

  At the sixth top, the bit a1 passes in the cell C2 at the same time as the bit b2, and consequently the product

  a1b2 is performed and stored in the cell C2.

  At the seventh top, the bits a1 and b3 are multiplied in the cell C3, while the bits a2 and b1 are multiplied in the cell C2, the product being added to that of the bits a1 and b2 already contained in the adder circuit. The eventual withholding is passed to cell C2. The process continues as shown in Figure 5 until each bit of one of the numbers has been multiplied by each bit of the other number. It will be seen that after the top 11 the add-on circuits of each of the cells C1 to C6 contain the sums of the products mentioned above, with the exception of the cell C6 which will contain only a possible product

coming from cell C5.

  The result of the multiplication operation

  is obtained by reading in sequence the contents of the cir-

  cooked adders from each cell, starting

  by the most significant bit in cell C6.

  Figure 6 shows an example of the operation just described, namely the numbering of the numbers 111 and 101. The actual numbers of each number were written in the rectangles, and the results

  multiplications are shown below the rec-

  tangles concerned. The final output 100011, is indi-

  at the bottom of the diagram, with the arrows indicating a "restraint" carried forward from the adder circuit of a

  cell to that of the next cell.

  As already indicated, the technique described above requires only a number of bit processing cells at least equal to the sum of the number of bits in the two numbers, and the multipliers having one of the two described forms are suitable for multiplication

large numbers.

  Digital multipliers of the type described above can be used for many purposes. For example, the multiplication of two matrices is a

  common requirement in the processing of digital

  c. Consider, for example, the following multiplication of matrices: a a b11b12bbl r 013il 12 1ilb3 2 13. ilC11 201 3 a21 a22 a23 X b21 b22 b23 [21 22 23 la31 a32 a 33 b31 b32 b33 e31 c32 e33l

  o each number is itself composed of several bits.

  Then: Cll = allb1 + al2b21 + al3b31 e12 = allb12 + a12b22 + a13b32

And so on.

  Such a calculation can be easily performed in

  using a multiplier network of the type already described.

  For the multiplication of matrices indicated above, a network of nine digital multipliers is required, as shown in Figure 7. The nine numerical multipliers

  DM1 to DM9 each comprise a linear network of

  bit processing, as already described. The nine multipliers are arranged in a network of three by three, so that when a number passes into a multiplier, it is passed bit by bit to the next multiplier of the same row or column. The drawing also shows the order in which the numbers are applied to the

  matrix of multipliers. In each rectangle

  In the case of a multiplier, the result of the calculation made by this multiplier is indicated, for example the multiplier DM3 calculates the result C13 of the final matrix. We will see in Figure 7 that the numbers garl and b1l are first applied to the multiplier DM1, which produces the product of these two numbers. When this has been done, the number a11 goes to the multiplier DM2, where it is multiplied by b12, while b11 goes to the multiplier DM4, where it is multiplied by a22. At the same time, a12 and b21 are applied to the multiplier

  DM1. The product a12b21 is carried out in the multiplication

  DM1 and added to the product a11b11 which is already in memory. The multiplication continues step by step until each of the numbers "a" has been multiplied by each of the numbers "b". The final results are read

  in the nine multipliers according to the desired sequence.

  Because the digital multipliers not only multiply two n-bit numbers one by one, but also add together the results of three such multiplications, each multiplier must have more than 2n cells, since there may be bits of "restraint". In fact, if there are "m" products to add to each other, the number N of cells

  in each multiplier is given by N = 2n + (m-1).

  In the case of the multiplication of matrices mentioned above, where each result is the addition of three multiplications (m = 3), and o each number

  is a 32-bit number (n = 32), then we have

  one of the nine digital multipliers, N = 66. This means that each multiplier includes a network

  66 cells, not the 64 that are sufficient

  for the multiplication of two numbers of

32 bits.

  The multiplication of matrices is only an example

  many uses that can be made of a

  digital multiplier according to the invention.

Claims (9)

  A digital multiplier for multiplying one by one two binary numbers, characterized by a linear matrix of bit-level processing cells, each comprising two input connections each of which are respectively applied the successive bits of each. two binary numbers, two output connections connected to the cell   next adjacent, and to which the   successive bits already mentioned, means of multiplying   cation acting to multiply together a bit of each of the numbers, and addition means acting   to add together and store the results   successive multiplications carried out in the cell.   2. A multiplier according to claim 1,   characterized by the fact that the first and second cir-   bistable flip-flops are connected between each of the input connections and the corresponding connection Release.   3. A multiplier according to claim 2, characterized in that the multiplying means comprise an AND gate having two connected inputs.   at the outputs of the first and second toggle circuits.   4. A multiplier according to any one   Claims 1 to 3, characterized in that   the adding means of each bit processing cell, with the exception of the first cell of the network, has a hold input connected to the preceding cell by means of a flip-flop circuit bistable.   5. A multiplier according to any one   Claims 1 to 4, characterized in that   the means for adding each bit-processing cell, with the exception of the last cell of the network, have a hold output connected to the cell next closest.   6. A multiplier according to any one   previous claims, characterized by   delay means acting to delay the application of the successive bits of one of the numbers to the connection   appropriate output, a predetermined time interval   completed, with respect to each of the successive bits of the other number.   7. A multiplier according to claim 6, characterized in that the delay means comprise a third flip-flop circuit connected between the output of the second flip-flop circuit.   and the corresponding output connection.   8. A multiplier according to any one   previous claims, characterized by the fact   that the number of cells in the network is at least equal to the sum of the numbers of bits in each of the   binary numbers to multiply one by the other.   9. A multiplier according to any one   Claims 1 to 8, characterized by means   reading to act to extract additional circuits   of each bit processing cell the number stored therein when the multiplication   two binary numbers is complete.