GB2161301A - Cross-correlator - Google Patents

Abstract

To remove noise common to a pair of correlated real process derived signals, the positive time cross correlation function and the negative time cross correlation function are both determined, and the difference between the latter functions is taken. Apparatus is described. The functions may be evaluated by means of a physical single bit correlator even when input signals are resolved to be more than one bit resolution. A signal processing system is employed to update smoothed estimates of the difference at a rate equal to the sampling rate and to evaluate the median of the most likely time delay. <IMAGE>

Description

SPECIFICATION Improved cross-correlator Field of the invention statement: This invention relates to a method and apparatus for correcting the cross-correlation function of two signals to remove noise common to both signals.

Apparatus for measuring the cross-correlation function between two signals is known. Such apparatus estimates the cross-correlation function for positive time lags.

Such methods suffer from the disadvantage that any common mode noise between the channels may bias the time lag of the correlation peak value.

When calculating the lag time for the peak value of the cross-correlation function it has been usual to sum a number, hereafter referred to as N, of previous estimates of the cross-correlation function.

That method suffers from the disadvantage that only one estimate of the lag time for the peak value is obtained for each N of estimations of the cross-correlation function.

When evaluating the cross correlation function of data sampled to more than single bit resolution it has been usual to employ a plurality of single bit correlators.

The method suffers from the disadvantage that it is costly to implement.

Object of the invention An object of the present invention is to provide a method of and apparatus for removing noise common to two correlated signals and which avoids or at least ameliorates some of the disadvantages of the prior art.

Disclosure of the invention According to one aspect the invention consists in an apparatus for removing noise common to a first signal and a second signal correlated with the first, comprising: correlator means for providing a third signal indicative of the cross correlation of the first and second signals as a function of positive time lag of the first signal with respect to the second, and for providing a fourth signal indicative of the cross correlation of the first and second signals as a function of negative time lag of the first signal with respect to the second signal, and means for providing an output signal indicative of the difference between the third and fourth signals.

The means for providing an output signal indicative of the difference between the third and fourth signals may involve analogue or digital subtraction or as is mathematically equivalent, may involve inversion of one signal and analogue or digital addition.

Preferred embodiments of the invention provide means whereby both positive and negative time lags of the cross-correlation function are differenced to remove the autocorrelation function of noise common to both signals and individual estimates of the cross- correlation function at each discrete lag time are exponentially smoothed. Desirably embodiments include a means whereby the median value of the lag time for the peak value of the correlation function is evaluated.

Desirably embodiments include a means whereby the cross correlation of two signals which have been digitised to more than 1 bit resolution is evaluated by one single bit correlator.

Brief description of the drawings The invention will now be described by way of example only with reference to the accompanying drawings, wherein: Figure 1 is a diagram illustrating the presence of common mode noise in correlated real process signals.

Figure 2 is a diagram showing a typical uncorrected cross- correlation function, and a function corrected for common mode noise.

Figure 3 exemplifies a positive time lag cross-correlation function signal for process signals.

Figure 4 shows the cross-correlation function signal of figure 3 corrected for common mode noise by the method of the invention.

Figure 5 shows a preferred embodiment of a cross-correlator preprocessor circuit.

Figure 6a and 6b show a schematic diagram of a circuit according to the invention.

Figure 7 shows a complete circuit diagram of apparatus according to the invention.

The cross correlation function Ryx(T) of two signals y(t) and x(t) is given by

(t)x(t-T) dt, wherein T is lag time, M is the total sampling time. If y(t) is the output of a linear system with input x(t) and impulse response h(T), then The convolution relation:

also holds.

In a real process common mode noise n(t) may be present, as shown in Figure 1.

When the process is a pure transport lag (L), h(T) becomes a unit impulse at time delay L, and Ryx (T) = TAKE IN HERE Rxx (T - L) +Rnn (T).

Since all autocorrelation functions, for example: Rnn (T), are symetrical about zero T, that is: Rnn (T) = IT), then Ryx (T) - Ryx (-T) = Rxx (T - L) - Rxx (-T - L).

In order to determine L accurately, the signals x(t) and y(t) must have a bandwidth sufficient to ensure that h(T) is a narrow peak at lag time L, and thus that Rxx (T) is very small for IT l > L, and thus: Ryx (T) - Ryx (-T) = Rxx (T - L) which is the cross-correlation function free from noise n(t).

Figure 2 shows a sketch of a typical cross-correlation function between two process signals which are similar in spectral content, but with one signal (y(t)), referred to as the downstream signal, delayed in time with respect to the other (x(t)). The signals are shown as a function of Lag T. Curve 1 shows the uncorrected cross- correlation function Ryx (T). Curve 2 shows the common mode noise (auto correlation function) Rnn (T). Curve 3 shows the function corrected for common mode noise. As is evident from Figure 2, the peak value of a cross-correlation function may be biased in both time (Lag) and amplitude by common mode noise.

Any noise which is common to both channels can be removed from the cross correlation function by subtracting the correlation value at negative time lags from that at respective positive time lags.

Figure 3 shows positive time lag cross-correlation functions for measured process signals with varying amounts of 120 Hz sine wave noise added to both channels. The top diagram 3(a) shows results for a noise free signal. The second 3(b) for a signal to noise ratio of 4:1 and the third 3(c) for the noise only.

Figure 3 (c) shows uncorrected cross-correlation function for a measured process with 120 Hz noise added, 7.8 mS per division horizontal and demonstrates perfect correlation at top of screen and perfect negative correlation at bottom of screen. The bias in peak position between Figures 3(a) and 3(b) is evident Figure 4 shows the output from the improved cross-correlator circuit according to the invention. The cross-correlation function is corrected for common mode noise and under the same conditions as in Figure 3. It can be seen that the lag time of the peak correlation value is now not biased by the noise, and that the noise is no longer apparent.

In preferred embodiments of the invention, Ryx(T) - Ryx(-T) is evaluated by time multiplexing the serial inputs to the correlator, such that every second sample of both inputs represents -Ryx(-T) and every other sample of both inputs represents Ryx(T).

In preferred embodiments of the invention the difference, Ryx(T) - Ryx(-T), at each time lag (T) is exponentially smoothed by means of circuits which perform the steps of: (1) storing an exponentially smooth value of each difference; (2) calculating a function of lag time herein defined as A by dividing each stored value by a power of two; (3) calculating a function of lag time herein defined as B by dividing each new difference value by the same power of two; (4) calculating a function of lag time herein defined as C by evaluating the "two's complement" of each value in A; (5) calculating the sum of B and C; (6) calculating a correction function herein defined as the sum of B and C divided by a further adjustable power of two, resulting in an adjustable time constant for the exponentially smoothed values;; (7) adding said correction function to the stored values resulting in said stored values being updated.

Desirably embodiments the exponentially smoothed stored values, being a function of positive lag number, provide an output proportional to the median of the lag time of the larget value of the stored function by: (1) circuits which determine the lag time, herein designated by L, of the largest value of the stored function; (2) incrementing said output if the value of L is greater than said output; (3) decrementing said output if the value of L is smaller than said output.

According to preferred embodiments of the invention, the two input signals are zero crossing polarity detected (given a value of 0 or 1 depending on whether they are less than or greater than zero respectively). Signals with more than 1 bit resolution are accommodated by an optional add on circuit, the preferred embodiment of which is detailed in Figure 5. The preferred embodiment achieves 2 bit resolution by time multiplexing three input signal configurations on one single bit correlator. The three input configurations are: (a) Correlation of the most significant bit of the upstream signal with the most significant bit of the downstream signal.

(b) Correlation of the most significant bit of the upstream signal with the least significant bit of the downstream signal.

(c) Correlation of the least significant bit of the upstream signal with the most significant bit of the downstream signal.

The simultaneous correlation of these multiplexed input configurations is equivalent to adding results from three separate single bit correlators. This is known to provide correct statistical weighting to the significance of the bits as described. As used herein, downstream refers to the signal in which the required information is delayed in time with respect to the same information in the other signal herein referred to as the "Upstream" signal.

For preference a single digital cross-correlation integrated circuit is employed which samples the inputs twice in rapid succession (compared to the sample rate), firstly connected normally and secondly connected with reversed inputs and with one input inverted, that is to say, the input normally connected to the upstream signal is connected to the downstream signal and the input normally connected to the downstream signal is connected to the inverted upstream signal. In a less preferred embodiment two digital cross-correlator integrated circuits are employed. The second of the digital cross-correlator integrated circuits is connected with reversed inputs, that is to say, the input designed to be connected to the Upstream signal is connected to the Downstream signal and the input designed to be connected to the Downstream signal is inverted and connected to the Upstream signal.In this embodiment the output from the digital cross correlators is added to the output of the second. It will be understood that this is mathematically equivalent to feeding the first and non-inverted second signals to respective second and first terminals of the second digital correlator and differencing the outputs.

The invention will now be described, by way of example only, with reference to Figures 5, 6 and 7.

Components referred to in the figures are identified by numbers, and data by a function of time, (e.g., A(t)) or a letter). Data flow is indicated by arrows. The number of physical wires in a data bus is indicated by a slash and a number.

Figure 5 shows a preprocessor for the cross-correlator which comprises two 2 bit analog to digital converters and a time operated multiplexer which enables correct weighting to be applied to each bit of the digitised data on a time shared basis. This circuitry constitutes an optional "plug-in" in addition to the common mode corrected correlator circuit of Figure 6a.

The analog to digital converters are designed to automatically adjust the full scale range according to the input signal amplitude.

Figure 6a shows a common mode corrected correlator that provides a number between 0 and 64 which represents the correlation level between the two inputs at each sample interval.

This implementation samples the two inputs U(t) and D(t) by zero crossing polarity detection. The noise corrected cross-correlation is implemented in part by a TRW 1023J correlator integrated circuit. At the completion of each record (period of 256 samples), the last 64 binary samples, obtained from the last 32 upstream samples alternated with the last 32 inverted downstream samples are loaded into a holding latch, as described in Figure 6a (1 and 2). At each of the next 256 samples the TRW 1023J evaluates a 7bit correlation between the holding latch and the latest contents of the B shift register.

For preference, the correlator output, which ranges from 0 to 64 is limited to 0 to 63 to prevent overflow in the following circuitry (4).

The result is a correlation which has been corrected for common mode noise. This common mode noise correction technique is implemented with the circuitry in Figure 7. It is constructed in such a way that it is pin for pin compatible with a single TRW 1023J correlator integrated circuit via a plug (5), thus allowing existing cross-correlator designs to be upgraded by a plug in replacement.

The clock in Figure 6b (6) provides: 1. A sample interval clock which is adjustable.

2. A lag number which is incremented by one after each sample interval.

3. A pulse after the 256th sample interval (when the lag number is reset to zero). This pulse is also used to control the multibit time multiplexer (Figure 5).

In Figure 6b the exponential smoothing circuit provides: 1. A means for calculating the exponentially smoothed value of the corrected cross correlation function at each lag number.

2. Random Access Memory (7) to store the 256 smoothed corrected correlation values. The 7-bit corrected correlation is multiplied by 32 to give a 12-bit number (C(T) in Figure 6b (8)). C(T) is limited to 2047 for perfect correlation, and 0 for perfect negative correlation. A(T) is the value of the address bus and is known as the lag number. When the input signals are derived from random processes, the precision at a given lag number can be improved by smoothing. Each of the 256 values are exponentially smooth, with 256 smoothed values being stored in Random Access Memory (7).

If G(T) in Figure 6 is the smoothed, noise corrected correlation function and C(T,N) is the value of C(T) obtained N records previously, then: Infinity GIT) = Sum C(T,N) (1-11k)N (1) N=1 k is the smoothing time in records, and k is a power of 2.

The smoothed corrected correlation value for lag T is updated in the following manner. J (T) is calculated from: J(T) = -G(T)132 (9). (2) using 2's complement arithmetic. D(T) is then calculated by: D(T) = C(T)/32 + J(T) = C(T)132 - GIT)132 (3) D(T) represents a negative number if its most significant bit is set, that is to say, it is in 2's complement form.

If, for example, k = 64, then D(T) is divided by two (11), and E(T) becomes: E(T) = CIT)/64 - G(T)164 (4) E(T) representes the adjustment which must be added to G(T) to update G(T). E(T) is in two's complement form. G(T) is always a positive number, and is in absolute binary form.

The adjustment E(T) is added to G(T) in (12 and 13) to give the updated value: GIT) updated = (Ci(T)/64) + (1 - 1164) G(T) (5) This recursive formula can be read as an exponentially smoothed version of C(T).

In Figure 6b the peak detector circuit provides: 1. The lag number (address) of the largest smoothed corrected correlation value found during the current record of 256 samples. This is held in latch 14. The output is latched (15) at the end of a record.

At the beginning of a record latch (16), and thus L is cleared. The value of K(T) is compared with L (17).

If K(T) L, and if T is greater than a present minimum determined by (18) and (19) then after the next sample check, clock L becomes K(T) and the value of T is latched into (14). At the end of the record L contains the largest corrected correlation value and (14) contains the lag number of the largest corrected correlation value.

(2) A means of ensuring that if the peak corrected correlation value is too low then the output is not updated (20 through 22).

Both the lag number A(T) and the corrected correlation values K(T) are available as analogue outputs which can be used to display the "correlogram" on an oscilloscope (23 and 24).

In Figure 6b, latch (15) contains the lag number of the peak corrected correlation value. The median value of the contents of (15) over several records is obtained in preference to simple averaging since the median is more immune to noise.

The principle of the median lag follower is as follows: If Q is the output of tha follower and P is the input, then at the end of each record 0 (output of counter (25) is incremented by one if P > O or decremented by one if P < (as determined by (26)).

A more detailed description of the preferred embodiment of the invention is given below, in which: Two rapid clock pulses shift two values into each of the upstream and downstream registers of TDC1023J circuit (Figure 6a). These clock pulses are generated in (3) and at the first clock pulse the switch (2) is set to the left and at the second clock pulse the switch (2) is set to the right.

The 7-bit correlation result is shifted by five bits to provide a 12-bit number (C(T) in Figure 6). This is added to a 16-bit number (J(T) in Figure 6) derived from the data bus. The data bus is divided by 32 by shifting by five bits. The most significant five bits are implied zeros. The two's complement is taken by inverting all sixteen bits and adding one. Thus the most significant five bits of (J(T) are thus all ones. The least significant five bits of C(T) are all zeros. C(T) and J(T) are now added.

Since all bits representing 2 to the power (12 to 15) in J(T) are ones and all similar valued bits of C(T) are zeros, the adder for the most significant four bits consists of a single inverter derived from the carry output of IC 3.

This two's complement number may then be divided by 1,2,4,8 or 16, depending upon the required exponential smoothing time. (Representing 32,64,128,256 or 512 times the maximum correlation time.) The adder outputs are stored in a 16-bit latch.

The latch outputs are stored in memory at the address given by the lag number. The memory consists of two 2K x 8 CMOS static RAM chips (5) arranged as a 16-bit wide memory. Only 256 memory ad dresses are used.

Two D/A converters, Figure 6b (23 and 24) provide analoque outputs of the data bus and lag number bus respectively. These enable the latest "correlogram" to be displayed on an Oscilloscope in real time.

At the beginning of a record, the peak comparator latch (16) is cleared. At each sample clock the eight most significant bits of the data bus are latched if they represent a number larger than that currently contained in the latch. This latch therefore holds the largest corrected correlation value for the current record.

The lag number is latched (14) at a transition of the sample clock provided the peak comparator (17) indicates that this is the largest smoothed corrected correlation value to date for this record and provided the lag number is greater than the minimum set on switch (19).

The downward transition of the most significant bit of the lag number A(t) signals the end of a record (256 samples).

The latch (14) contains the lag number of the peak corrected correlation so far for this record. At the end of a record, this number is latched into the end of record latch (15). Said latch holds the lag number of the corrected correlation peak and is updated after each record is complete, provided the amplitude of the corrected correlation peak is greater than a minimum set by switch (22).

At the end of a record the upidown counter (25) with optional parallel load is incremented by one, decremented by one or left as is, if the output of the end of record is greater than, less than or equal to the up/down counter output (as determined by (26) respectively. This constitutes the median lag calculation.

The digital output (0) is the lag number of the peak corrected cross correlation, that is to say, and estimate of the time lag between the two input signals. This implementation of the invention also provides for a multiplying digital to analogue converter (27), connected such that: i. The digital value representing the lag time of the peak of the corrected cross correlation function is connected to the digital input of the multiplying digital to analogue converter (27): ii. The output of the multiplying digital to analoque converter is subtracted from a one-volt reference and the result of this subtraction then amplified (28). Said amplified signal is applied to the voltage reference input of the multiplying digital to analogue converter: iii. The output is taken from the reference voltage applied to the multiplying digital to analogue converter.When the invention is applied in an application where the input signals represent properties of a flowing material as measured by two sensors separated by a known distance, then said output is then proportional to the velocity of the material.

A complete circuit diagram is enclosed as Figure 7.

It will be understood that Ryx(T)-Ryx(-T) is mathematically equivalent to the inverse fourier transform of the imaginary part of the complex cross-power spectrum of Y(T) and X(T).

This method for deriving the required function could be implemented by a microprocessor, however current state of the art makes this impractical (high cost and slow operation).

As will be apparent to those skilled in the art from the teaching thereof the invention herein described may be implemented by other circuits and all such equivalent embodiments are deemed to be within the scope thereof.

Claims (23)

1. Apparatus for removing noise common to a first signal and a second signal correlated with the first, comprising: correlator means for providing a third signal indicative of the cross correlation of the first and second signals as a function of positive time lag of the first signal with respect to the second, and for providing a fourth signal indicative of the cross correlation of the first and second signals as a function of negative time lag of the first signal with respect to the second signal, and means for providing an output signal indicative of the difference between the third and fourth signals.

2. Apparatus according to Claim 1 wherein the correlator means comprises a signal correlator having a first circuit input, a second circuit input, and providing a signal which is indicative of the cross correlation of signals applied to the inputs as a function of time lag of one input signal with respect to the other, and means for switching inputs between a "positive time lag" mode and a "negative time lag" mode, said switching means in the "positive time lag" mode directing the first signal to the first input and the second signal to the second input whereby to provide the third signal and said switching means in the "negative time lag" mode directing the first signal to the second input and a second signal to the first input whereby to provide the fourth signal.

3. Apparatus according to Claim 2 wherein the means for providing an output signal indicative of the difference between the third and fourth signal includes means for inverting one of the signals applied in one of the modes and adding the third and fourth signals.

4. Apparatus according to Claim 2 further comprising means for storing the difference between the output signal obtained when the switch means is in a "positive time lag" mode and the output signal obtained when the switch is in a "negative time lag" mode.

5. Apparatus according to Claim 2 wherein the correlator is a single bit correlator circuit and further comprising means for time multiplexing the input signals.

6. App#aratus according to Claim 5 wherein every second sample of output represents the cross correlation of the first signal with respect to the second for a negative time lag and every other output represents said cross correlation for a positive time lag.

7. Apparatus according to Claim 1 comprising a memory means for storing signals representing exponentially smoothed estimates of the difference between the third and fourth signals at various values of time lag, and means for updating the memory means at a rate equal to a sampling rate of the first and second input signals.

8. Apparatus according to Claim 1 comprising: a first digital cross correlator; a second digital cross correlator; means to supply the first and second signals to respective first and second inputs of the first cross correlator and to supply the first and second signals to respective second and first inputs of the second cross correlator; and means for indicating the difference between the outputs of the first and second digital cross correlators.

9. Apparatus according to Claim 8 wherein one of the signals to one of the correlators is inverted and the output signals of said cross correlators is summed whereby to indicate said difference.

10. Apparatus according to Claim 8 wherein each correlator is a single bit correlator circuit.

11. Apparatus according to Claim 8 comprising memory means for storing signals representing smoothed estimates of the difference between the third and fourth signals at various values of time lag, and means for updating the memory means at a rate equal to a sampling rate of the first and second input signals.

12. Apparatus according to Claim 1 in combination with data processing means for evaluating the median value of the time lag corresponding to the maximum positive value of a corrected cross correlation function.

13. Apparatus according to Claim 1 in combination with means to digitise the first and the second signal each to two bit resolution and means to time multiplex selected combinations of the resulting four bits whereby to evaluate the corrected cross correlation functions of inputs with two bit resolution.

14. A method for removing noise common to a first signal and a second signal correlated with the first comprising the steps of processing the first and second signals so as to provide a third signal indicative of the cross correlation of the first and second signals as a function of positive time lag of the first signal with respect to the second; processing the first and second signals so as to provide a fourth signal indicative of the cross correlation of the first and second signals as a function of negative time lag of the first signal with respect to the second signal, and differencing the third and fourth signals.

15. A method according to Claim 14 comprising the steps of switching the first and second signals between a "positive time lag" mode in which the first and second signals are fed to respective first and second circuit inputs of a signal correlator, and a "negative time lag" mode in which the first and inverted second signal are fed to respective second and first circuit inputs of the cross correlator.

16. A method according to Claim 15 further comprising the step of storing the difference between the output signal obtained when the signals are switched in the "positive time lag" and the output signal obtained when the signals are switched in the "negative time lag" mode.

17. A method according to Claim 15 wherein the correlator is a single bit correlator circuit and further comprising the step of time muitiplexing the input signals.

18. A method according to Claim 15 comprising the step of storing signals representing exponentially smoothed estimates of the difference between the third and fourth signals at various values of time lag, and updating the estimates at a rate equal to a sampling rate of the first and second input signals.

19. A method according to Claim 14 comprising the steps of feeding the first and second signals to respective first and second terminals of a first digital cross correlator; feeding the first and inverted second signals to respective second and first terminals of a second digital cross correlator; and adding the output signals obtained from said cross correlators.

20. A method according to Claim 14 comprising the steps of feeding the first and second signals to respective first and second terminals of a first digital cross correlator, feeding the first and second signals to respective second and first terminals of a second digital cross correlator and differencing the output signals obtained from said cross correlators.

21. A method according to Claim 19 wherein each correlator is a single bit correlator.

22. A method according to Claim 21 comprising the step of storing signals representing exponentially smoothed estimates of the difference between the third and fourth signals at various values of time lag.

23. A method according to Claim 22 wherein the estimates are updated at a rate substantially equal to the sampling rate of the first and second signals.