GB2159662A - Forming diffused junctions - Google Patents
Forming diffused junctions Download PDFInfo
- Publication number
- GB2159662A GB2159662A GB08510079A GB8510079A GB2159662A GB 2159662 A GB2159662 A GB 2159662A GB 08510079 A GB08510079 A GB 08510079A GB 8510079 A GB8510079 A GB 8510079A GB 2159662 A GB2159662 A GB 2159662A
- Authority
- GB
- United Kingdom
- Prior art keywords
- junctions
- channel
- forming
- layer
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000010410 layer Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000007943 implant Substances 0.000 claims abstract description 9
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910021339 platinum silicide Inorganic materials 0.000 claims abstract description 3
- 239000002344 surface layer Substances 0.000 claims abstract description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 11
- 229910052796 boron Inorganic materials 0.000 claims description 11
- 229910052785 arsenic Inorganic materials 0.000 claims description 8
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 230000009977 dual effect Effects 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- OLBVUFHMDRJKTK-UHFFFAOYSA-N [N].[O] Chemical compound [N].[O] OLBVUFHMDRJKTK-UHFFFAOYSA-N 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 238000000137 annealing Methods 0.000 claims 5
- 150000002500 ions Chemical class 0.000 claims 2
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 230000005465 channeling Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A method of producing diffused junctions in a silicon substrate 2,4, comprises forming an amorphous surface layer 10 by e.g. implanting silicon, forming diffused junctions, e.g. doped p and n channel junctions 12 and 16 using a single implant mask, and forming a metallised layer, e.g. of platinum which is then annealled to form a thin layer of platinum silicide. Such a semiconductor device exhibits junction depths of, typically, 0.25 mu m and junction sheet resistance values </=8 OMEGA per square. <IMAGE>
Description
SPECIFICATION
A method of producing diffused junctions in a semiconductor substrate
The present invention relates to an improved method of producing diffused junctions in a semiconductor substrate.
With the shrinking of lateral dimensions towards the submicron range for very large scale integration (VLSI) complementary metal oxide silicon (CMOS) circuits, it is desirable to achieve very shallow source and drain structures to minimise short channel effects. This can be achieved more easily for high doped arsenic regions for n-channel metal oxide silicon transistors, but it is more difficult using boron to obtain the same shallow structures for p-channel devices. This is largely a consequence of ion channeling which for boron, typically gives rise to junction depths greater than 0.4#m even when low energy molecular implants (BF+) are used.In current advanced
CMOS processes, junction depths of 0.4 and 0.7#m are attainable with sheet resistance values of 30 and 5552/so. respectively for n + and p+ sources and drains. If junction depths are reduced substantially, an inevitable consequence is a detrimental increase in sheet resistance.
The present invention is intended to provide a remedy to this problem and enables n- and p- channel devices to the fabricated having shallow junction depths of 0.25ELm or less and low sheed resistance values of#8#/sq.
Accordingly, there is provided a method for producing diffused junctions in a silicon substrate, the method comprising forming an amorphous surface layer on the substrate, forming diffused junctions in the amorphous layer, and forming a metallised layer on the amorphous layer.
Advantageously the amorphous layer may be formed by a dual silicon inplant.
The metallised layer may comprise platinum.
The present invention will now be described, by way of example, with reference to the accompanying drawings in which;
Figure 1 illustrates a method of forming diffused p + and n + junctions in a semiconductor substrate;
Figure 2 illustrates the secondary ion mass spectometry profiles of the source/drain region as-implanted in accordance with a prefered method of the present invention and
Figure 3 illustrates the secondary ion mass spectrometry profiles of the counter doped nchannel of a metal oxide silicon transistor formed in accordance with a method of the present invention.
Referring to Fig. 1, there is shown an nchannel semiconductor substrate 2 having a p-channel substrate well 4 such as is used in complementary metal oxide silicon (CMOS) technology. The substrate 2 has an oxide layer 6 in which windows 8 have been formed where it is required to implant junctions in the substrate 2,4. An amorphising silicon implant, which may be a dual silicon implant, is carried out on this structure to form an amorphous silicon layer 10 in the region of the n and p substrate material exposed by the windows 8 in the oxide layer 6. This process produces the structure illustrated in Fig. 1 a.
The amorphous silicon layer 10 greatly reduces ion channeling during subsequent stages of the process when dopant implantation takes place, as shown in Figs. 1b and 1 c.
Boron is now implanted to form p + junctions 12 in the regions of the windows 8. No inplant mask is used for this stage of the process and hence, the boron doped p + junctions 12 are formed in both the n-channel substate and the p-channel substrate well, as shown in Fig. 1 b. Typically, the boron is implanted at an energy level of 25 Kev and a dose of 6 x 10'4 ion cm-2.
An implant mask 14, such as resist is now formed over the desired boron doped p + junctions in the substate 2. Arsenic is now implanted to counterdope n + junctions 16 in the p-channel substrate well 4, as shown in
Fig. 1 c. Typically the arsenic is implanted at an energy level of 110 Kev and a dose in the range of 5 x 1016 ion cm-2. The amorphous silicon layer 10 enables p + junctions 12 and n + junctions 16 to be fabricated having junction depths of, typically, 0.25;lem.
The implant mask 14 is now stripped from the structure to leave the exposed p + and n + junctions 12 and 16, as shown in Fig.
1 d .
The process of implanting the boron doped p + junctions 12, masking, and then implanting the arsenic doped n + junctions 16 by counterdoping enables the formation of these junctions using only a single implant mask.
However, it should be realised that a dual mask process may be adopted to form the junctions 12 and 16.
The structure shown in Fig. ld is now annealed at a temperature of about 600 C in a nitrogen, hydrogen ambient atmosphere to restore crystalline perfection followed by an activation anneal at about 900 C in an oxygen nitrogen ambient atmosphere. This results in minimal redistribution of the boron and arsenic dopants, as illustrated in Figs. 2 and 3.
A platinum film is now deposited on the structure to contact the p + and n + junctions 12 and 16, preferably by magnetron sputtering. At this stage of the process the boron doped p + junctions 12 have typical sheet resistance values of 20052 per square and the arsenic doped n + junctions 16 have typical sheet resistance values of 20-50S1 per square. The structure is now once again annealed and the platinum reacts with the sili con to form a layer of platinum silicide 18 of approximately sooA thickness in contact with the diffused junctions 12 and 16. After this siliciding step the n + junctions (source) and the p + junctions (drain) have, typically, sheet resistance values < 8# per square. Although the present invention has been described with respect to a particular embodiment it is to be understood that modifications may be effected within the scope of the invention.
Claims (11)
1. A method of producing diffused junctions in a silicon substrate, the method comprising forming an amorphous surface layer on the substrate, forming diffused junction in the amorphous layer, and forming a metallised layer on the amorphous layer.
2. A method according to claim 1 wherein the amorphous layer is formed by a dual silicon amorphising inplant.
3. A method according to claim 1 or claim 2 comprising p-channel and n-channel diffused junctions and wherein the p-channel junctions are formed by implanting boron and the n-channel junctions are formed by implanting arsenic.
4. A method according to claim 3 wherein the p-channel and n-channel junctions are implanted using a single implant mask.
5. A method according to claim 3 or claim 4 wherein the p-channel junctions are formed by in planting boron at an energy level of approximately 25 Kev and a dose of approximately 6 x 1014 ions cm-2 and the n-channel junctions are formed by counterdoping with arsenic at an energy level of approximately 110 Kev and a dose in the range of 5 X 10'5 to 1 X 1016 ions cm-2.
6. A method according to any one of claims 1 to 5 comprising annealing the substrate after forming the diffused junctions in the amorphous layer.
7. A method according to claim 6 wherein annealing the substrate after forming the diffused junctions in the amorphous layer comprises annealing in a nitrogen hydrogen ambient atmosphere at a temperature of approximately 600 C and annealing in an oxygen nitrogen ambient atmosphere at a temperature of approximately 900 C.
8. A method according to any one of claims 1 to 7 wherein the metallised layer is formed by magnetron sputtering.
9. A method of according to any of claims 1 to 8 wherein the metallised layer comprises platinum.
10. A method according to claim 9 comprising annealing the substrate after forming the platinum metallised layer to form a layer of platinum silicide.
11. A method substantially as hereinbefore described with reference to the accompanying drawings.
1 2. A semiconductor substrate produced in accordance with the method as claimed in claim 10 or claim 11 having junction depths S2 0.25#m and junction sheet resistance values of #8# per square.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB848410252A GB8410252D0 (en) | 1984-04-19 | 1984-04-19 | Shallow source/drain structures |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8510079D0 GB8510079D0 (en) | 1985-05-30 |
| GB2159662A true GB2159662A (en) | 1985-12-04 |
Family
ID=10559892
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB848410252A Pending GB8410252D0 (en) | 1984-04-19 | 1984-04-19 | Shallow source/drain structures |
| GB08510079A Withdrawn GB2159662A (en) | 1984-04-19 | 1985-04-19 | Forming diffused junctions |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB848410252A Pending GB8410252D0 (en) | 1984-04-19 | 1984-04-19 | Shallow source/drain structures |
Country Status (1)
| Country | Link |
|---|---|
| GB (2) | GB8410252D0 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0295121A1 (en) * | 1987-06-11 | 1988-12-14 | General Electric Company | Method for fabricating a self-aligned lightly doped drain semiconductor device with silicide |
| US4933994A (en) * | 1987-06-11 | 1990-06-19 | General Electric Company | Method for fabricating a self-aligned lightly doped drain semiconductor device with silicide |
| EP0443297A1 (en) * | 1990-02-20 | 1991-08-28 | STMicroelectronics S.r.l. | Metal-semiconductor ohmic contact forming process |
| US6720627B1 (en) * | 1995-10-04 | 2004-04-13 | Sharp Kabushiki Kaisha | Semiconductor device having junction depths for reducing short channel effect |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1542651A (en) * | 1975-04-30 | 1979-03-21 | Sony Corp | Semiconductor devices |
| GB2021316A (en) * | 1978-05-23 | 1979-11-28 | Western Electric Co | Isolation region for a semiconductor device |
| WO1983003032A1 (en) * | 1982-02-19 | 1983-09-01 | Tanaka, Tomoyuki | Semiconductor device and method of fabricating the same |
-
1984
- 1984-04-19 GB GB848410252A patent/GB8410252D0/en active Pending
-
1985
- 1985-04-19 GB GB08510079A patent/GB2159662A/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1542651A (en) * | 1975-04-30 | 1979-03-21 | Sony Corp | Semiconductor devices |
| GB2021316A (en) * | 1978-05-23 | 1979-11-28 | Western Electric Co | Isolation region for a semiconductor device |
| WO1983003032A1 (en) * | 1982-02-19 | 1983-09-01 | Tanaka, Tomoyuki | Semiconductor device and method of fabricating the same |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0295121A1 (en) * | 1987-06-11 | 1988-12-14 | General Electric Company | Method for fabricating a self-aligned lightly doped drain semiconductor device with silicide |
| US4933994A (en) * | 1987-06-11 | 1990-06-19 | General Electric Company | Method for fabricating a self-aligned lightly doped drain semiconductor device with silicide |
| EP0443297A1 (en) * | 1990-02-20 | 1991-08-28 | STMicroelectronics S.r.l. | Metal-semiconductor ohmic contact forming process |
| US5302549A (en) * | 1990-02-20 | 1994-04-12 | Sgs-Thompson Microelectronics S.R.L. | Metal-semiconductor ohmic contact forming process |
| US6720627B1 (en) * | 1995-10-04 | 2004-04-13 | Sharp Kabushiki Kaisha | Semiconductor device having junction depths for reducing short channel effect |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8510079D0 (en) | 1985-05-30 |
| GB8410252D0 (en) | 1984-05-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |