GB2157922A - Relay multiplexing for circuit testers - Google Patents

Abstract

Disclosed is a relay multiplexer circuitry for use in selectively connecting channels of a tester to selected test pins connected to nodes of a circuit under test. The pin nodes, channel nodes and relays are organised in a group such that it is possible to make a connection between any pin node or any channel node of the group with any other pin node or channel node of the group, through multiple or single closed relays, and each said pin node of said group is directly connectable to a unique combination of said channel nodes within said group, the number of pin nodes P in said group being greater than the number of channel nodes C in said group. It is preferred that there are two channel connections per pin, at least some of the channels are included in more than one group and that the P pins and C channels within at least part of a group are connected through relays in a combinatorial manner.

Description

SPECIFICATION Relay multiplexing for circuit testers The invention relates to relay multiplexer circuitry for making channels of a tester connectable to a large number of nodes of a circuit board being tested.

A printed circuit board (PCB) can be tested by using a testerto provide test signals to nodes of the board undertest and analyzing the resulting conditions at the nodes. One method oftesting, in-circuittesting, involves using test pins to contact the nodes of the board under test, providing signals to those nodes that affectthe conditions art a given device on the board (typically the nodes connected to leads to the particular device), analyzing the resulting signals, thereaftertesting another device on the board by providing signals to another set of nodes of the board undertest, and soon.There typically are a limited number of test channels, owing to their expense, connected to a large number oftest pins through a relay multiplexer wired to make each test pin connectableto one of two test channels through two relays.

The relays are operated to connect a test channel to only one test pin at onetime, and the total number of test channels and the total number of test pins are usually divided into groups.

In one such prior art relay multiplexer, each group has two test channels made connectable to all sixteen test pins in the groupthroughthirty-two relays; thus onlytwo test pins ofthe group can be connected at one time without a conflict. In this multiplexer, each group has a unique set of two test channels.

The possibility of conflict can also be reduced by increasing the number of relays to increase the "depth", i.e.,the number of test channels connectable to each test pin. In the extreme case, making each channel connectable to each pin, one could use all channels and any pins without conflict. The number of relays, however, would be the number of channels mesthe number oftest pins, requiring, for example, 100,000 relaysto make one hundredtestchannels connectable to one thousand test pins.

Summary of the Invention We have discovered that a limited number of test channels can be made connectable through relay multiplexer circuitry to a large number of test pins with decreased possibility of conflict and without increasing the number of relays per pin by making each pin connectable to a unique combination of test channels within a group.

In preferred embodiments there are two channels per pin; at least some of the channels are included in more than one group; the P pins and C channels within at least part of a group are connected through relays in a fully combinatorial manner, i.e., every possible combination of C channels is used, and P = C!/D! (C-D) !, where D equals the depth; and the test pins are assigned to a particular device on a board undertest such that each channel is used no more than the depth, one pin being assigned to a device not being used.

We have discovered that, when a group of test channel nodes, test pin nodes and relays of a relay multiplexer is to include less than every possible unique combination of channel nodes, by making the number of pin nodes connectable to each channel node substantially uniform in the group, the channels are used efficiently so as to reduce the possibility of conflict.

in preferred embodiments the number of pin nodes connectable to each channel node does notvary by morethan one (Most preferably the number of pin nodes per channel is the same); and the number of relays per channel is two.

Description of the Preferred Emodiment The structure and operation of the presently preferred embodiment of the invention will now be described afterfirst briefly describing the drawings.

Fig. isafunctional block diagram showing relay multiplexer circuitry according to the invention connected to a PCB being tested and driverldetectors for tester channels.

Fig. 2 is a functional block diagram of a channel driver/detector.

Fig. 3 is a schematic showing the wiring of the relays between channel nodes and pin nodes in said relay multiplexer circuitry.

Fig. 4 is a schematic of a relay of said relay multiplexer circuitry.

Fig. 5 is a diagrammatic elevation of a board under test contacted by test pins connected to specified pin nodes of said relay multiplexer circuitry.

Fig. 6 is a diagram showing a method of assigning channel combinations to test pins and devices under test.

Structure Referring to Fig. there is shown relay multiplexer 10 having 126 test pin nodes 12, connected to PCB undertest 13 by 126 pin lines 15, and twelve test channel nodes 14, connected to twelve channel driver/detectors 1 6for channels Ato Lvia channel lines 18. Channel nodes 14 are connected to pin nodes 12 via relays in multiplexer 10 controlled by relay controller 20. Channel driver/detectors 16 and relay contrnller 20 are connected to test controller 22 by bus 24.

Referring to Fig. 2, there is shown a channel driver/detector 16. It includes driver 26 and detector 28 connected in parallel to switch 29 connected to channel line 18. It also includes switch 30 for connecting line 18 to analog signal line 31.Analog signal line 31, driver 26, and detector 28 are all connected to bus 24.

Referring to Fig. 3, showing the wiring of relay multiplexer 10, it is seen thatthere are two groups 32, 34 of pin nodes 12 and channel nodes 14. Group 32 includes test pin nodes numbered 1 to 66, and group 34 includes test pin nodes numbered 67 to 126. Within each group, each pin node 12 is connectable to a unique combination oftwo channel nodes 14through two relays 36 (single form A layers). As is seen in Fig. 4, each relay 36 makes a channel node 14connectableto a pin node 12 by a normally open switch 38 controlled byTTL signals from controller 20 (via means not shown).In group 32 or group 34 it is possibleto make a connection between any pin node or any channel node ofthe group with any other pin node or channel node of the group, through multiple orsingle closed relays; in typical operation, however, at any given time, each channel node would be connected to no morethan one pin node, and each pin node would be connected to no more than one channel node.

In group 32, the combinations of channel nodes 14 are assigned to pin nodes 12 in a fully combinatorial manner; i.e., every possible uniquecombination of two ofthetwelve channels Ato L is shown in Fig. 3.

Thus,thetotal number of pin nodes (sixty-six) equals C!/D! (C-D) !, where C equals the number of channels (twelve), and D equals the depth (two). In group 32 each channel is connectabie to eleven test pin nodes.

The assignment of unique combinations of two channel nodesforthe test pin nodes in group 34 is identical to that in group 32 except that group 34 does not have combinations corresponding to those for pin nodes numbered 21,25,33,38,48,56. (Thus the combinations of channels are not fully combinatorial in group 34.) These six combinations have not been duplicated because only 126 (and not 132) pin nodes are being used in relay multiplexer 1 0.An X on the Fig.

3schematicindicatestheabsencefrom group34ofa combination that is used in group 32. These combina tionswere picked because each channel Ato L is represented once, so that in group 34there are ten pin nodes assigned to each of twelve channels A to L, instead of, e.g., nine pins assigned to one channel and eleven to another. This even distributio of pins per channel acts to reduce conflict, as does the require mentthateach pin node in a group be connectable to a unique combination of channel nodes, as is discussed below.

Referring to Fig. it is seen that PCB under test 14 includes a plurality of electronic devices 40. As is illustrated somewhat diagrammatically in Fig. 5 for a single device 40, nodes 42 atthe leads to device 40 are contacted by spring-loaded test pins 44, connected to the indicated eleven pin nodes 12 (those numbered 1, 3,6,10,15,21,28,36,45, 55,66). As can be seen from Fig. 3, the indicated eleven pin nodes and another pin node 12, the one numbered 56, have been selected so that each channel has been used no more than twice; thus all channels can be used to test device 40 without conflict.

Operation In operation, if PCB under test 13 has more devices 40 and nodes 42 than can be driven bythetwelve channels Ato Land 126 test pins connected to relay multiplexer 10, additional groups oftwelve channel driver/detectors 16, relay multiplexers 10 and relay controllers 20, are provided and connected to test controller 22 over bus 24.

Test pins 44are mounted on a support in position to contact all nodes 42 of PCB undertest 13. In wiring test pins 44to pin nodes 12, the pin nodes are assigned so that each channel is used no more than twice in the combinations of channels associated with the pin nodes connected to a single device 40. One pin node that is assigned to a device 40 is not initially wired but is reserved.

The diagram of combinations in Fig. 6 can be used to assign pin nodes. For example, in assigning pin nodes to the test pins 44 shown wired in Fig. 5, one picks channel combination group 46to obtain combinations such that each channel is used onlytwice, and refers to Fig. 3two identify the numbers of the corresponding pin nodes having these combinations. One combination of group 46 that is not used is the combination of channelsAa,.d L,the combinationforthe pin node numbered 56. By using only eleven pins in a channel combination group, any channel can be freed for use by any remaining pin to accommodate, without conflict, subsequent engineering change orders that might affect nodes 42 and require providing another test pin to a device 40.

In wiring further pin nodes 12 to test pins 44 for further devices 40, the test pin nodes associated with channel combination groups 48 to 54 (Fig. 6) can be used to identify pin nodes so that for each device 40, each channel is used no more than twice.

In makingthesetest pin to pin node wiring connections, the possibility of conflict (i.e, of a channel having to be connected to more than one test pin at the same time) is smaller than with prior relay multiplexers having comparable numbers of channels and relays, because pin nodes 12 within group 32 or34 are connectable to unique combinations of channel nodes 14. There is less chance that both channels for a pin node 12 will have to be used by other pin nodes than there would be,forexample, if sixteen pin nodes 12 were all connectable to the same two channel nodes 14.

The various devices 40 on PCB undertest 13 are tested by providing inputs to test pins 44 contacting those nodes 42 on board 13that are electically common to leads of a given device 40 on the board, while other devices 40 on the board are disabled by providing the appropriate signals, and sensing the resulting conditions atthe nodes common to leads to the device 40 being tested. In testing individual devices 40, selected channels A-L are connected to selected test pins 44 by activatingthe appropriate relays 36 by relay controller 20, operating under relay control signals provided by controller 22 over bus 24.

Test controller 22 also provides test control signals over bus 24to operate channel drivers 26to provide test signals inputs and detectors 28 to detect the test outputs while switch 29 is closed and switch 30 is open. When switch 30 is closed, analog signals are provided to test pins 44. The test outputs are provided to test controller 22, and compared with expected test outputs. After one device 40 has been tested, another device 40 on the board is tested by activating another setoftest pins44and soon.

Other Embodiments Other embodiments of the invention are within the scope ofthefollowing claims. For example, if less than sixty pins areto be used in group 34, additional channel combinations are picked so that the number of pins per channel for each channel is uniform. For example, if between seven and twelve ofthe sixty-six total possible combinations would not be used (i.e., if it was desired to have between fifty-fou r and fifty-nine pins), each channel would be represented no more than twice in the combinations removed from thefully combinatorial set shown in group 32. (In this case the pins per channel for each channel would be either ten or eleven). If between thirteen and eighteen ofthe sixty-six total would not be used, each channel would be represented no more than three times in the combinations removed from the fully combinatorial set (in this case the pins per channel would be either nine orten), and so on. This substantial uniformity of pins assigned to each channel results in efficient use ofthe channels and relays to avoid conflict; e.g., if one merely used pin nodes numbered 1 to 60, channel L would only be connectable to five pins, while the other channels would be connectable to eleven or ten pins, an inefficient use of channel L.While in some instances the pins per channel for each channel could vary be more than one and still be acceptable, preferablythe pins per channel for each channel of a group should vary by no more than one, and most preferably the number should be the same for all channels.

The Fig. 6 diagram can be used to identify channel combinations to be deleted from the fully combinatorial set. In Fig. 6, the sixty-six unique channel combinations fortwelve channels A-L and a depth of two are divided into five groups 46to 54 of twelve channel combinations and one group 56 of six channel combinations. In group 56 each channel is repre sented once, and in each of groups 46 to 54 each channel is represented twice. Thus, if one were to use between sixty and sixty-five pins, the channel combinations of group 56 could be selected for deletion.

(The six combinations not used in group 34 are different from but equivalent to those in group 56). If one were to use between fifty-four and fifty-nine pins, the combinations of any one of groups46to 54 could be selected for deletion. If one were to use between forty-eight and fifty-three pins, the combinations of group 56 and any one of groups 46to 54 could be selected for deletion, and soon.

Also, when using a second groupto add pins for connection to channels aiready in a first group having a fully combinatorial set of channel combinations, one could assign channels to the new pins sothatthe number of pins per channel in the second group is substantially uniform. In this way the overall pins per channel values would be substantially uniform, providing efficient use of channels and promoting reduced chance of conflict.

Also, the principles described herein can be applied to depths largerthan two and other numbers of channels in a group.

Claims (17)

1. Relay multiplexer circuitryfor selectively connecting channels of a testerto selected test pins electricallyconnectedto nodes of a circuit undertest, said pins being larger in numberthan said channels, said test circuitry comprising channel nodes for connection to said channels, pin nodes for connection to said pins, and relays wired for selectively making at least some of said pin nodes connectable to at least two said channels, at least some of said pin nodes, channel nodes and relays being organized in a group such that it is possible to make a connection between any pin node or any channel node of the group with any other pin node or channel node of the group, th rough multiple or single closed relays, and each said pin node of said group is connectable to a unique combination of said channel nodes within said group, the number of pin nodes Pin said group being greaterthan the number of channel nodes C in said group.

2. The circuitry of claim 1 wherein said unique combinations of channel nodes in said group are fully combinatorial.

3. The circuitry of claim 1 wherein said unique combinations of channel nodes in said group include less than the fully combinatorial set of combinations.

4. Thecircuitryofclaim 1 wherein there are two channels per pin.

5. The circuitry of claim 1 wherein at least some of said channels are connectable to more than one group.

6. Testing apparatus comprising the circuitry of claim 1 and test pins mounted on a support and spatially arranged to contact nodes of a printed circuit board undertest, said test pins being electrically connected to said pin nodes, said pin nodes connected to test pins for nodes for a given electronic device on said printed circuit board having associated combinations of channels such that each said channel in said group is represented in said associated combinations no morethanthe number of relays per pin. and there are channels represented in said associated combinations less than said number of relays per pin, to accommodate design changes of said circuit under test without conflict.

7. A method oftesting printed circuit boards using said relay multiplexer circuitry of claim 1, said method comprising providing test pins mounted on a support and spatially arranged to contact nodes of a printed circuit board undertest, and wiring said test pins to said pin nodes, said pin nodes connected to test pins for nodes for a given electronic device on said printed circuit board having associated combinations of channels such that each said channel in said group is represented in said associated combinations no morethanthe numberof relays per pin, there being channels represented in said associated combinations less than said number of relays per pin, to accommodate design changes of said circuit undertest without conflict.

8. Thecircuitryofclaim 1, said unique combina- tions of channel nodes in said group including less than the fully combinatorial set of combinations, the number of pins connectable to each said channel in said group being substantially uniform to efficiently use the channels so as to reduce the possiblilty of conflict.

9. The circuitry of claim 8 wherein the number of pin nodes connectable to each channel node does not vary by more than one in said group.

10. The circuitry of claim 9 wherein the number of pin nodesconnectableto each channel node is the same.

11. The circuitry of claim 8 wherein there are two channels per pin.

12. Relay multiplexer circuitryforselectively con- necting channels of a testerto be selected test pins electrically connected to nodes of a circuit under test, said pins being larger in numberthan said channels, said test circuitry comprising channel nodesforconnectionto said channels, pin nodesforconnectiontosaid pins, and relays wired for selectively making at least some of said pin nodes connectableto at least two said channels, at leastsome of said pin nodes, channel nodes and relays being organized in afirst group such that it is possible to make a connection between any pin node or any channel node of said first group with any other pin node or channel node of said first group,through multiple or single closed relays, and each said pin node of said first group is connectable to a unique combination ofsaid channel nodes within said first group, the number of pin nodes Pin said first group being greaterthan the number of channel nodes C in said first group.

at least some of said pin nodes, channel nodes and relays being organized in a second group, the number of pins connectable to each said channel in said second group being substantially uniform to efficiently use the channels so asto reduce the possibility of confict.

13. The circuitry of claim 12wherein said unique combinations of channel nodes in said first group are fully combinatorial.

14. The circuitry of claim 1 3wherein the number of pin nodes of said second group connectable to each channel node ofsaid second group does not vary by more than one in said second group.

15. The circuitry of claim 14whereinthe numberof pin nodes of said second group connect lye to each channel node of said second group is the same.

16. The circuitry ofclaim " wherein there are two channels per pin.

17. Relay multiplexer circuitry substantially as herein described with reference to Figs. 1 -4 of the drawings.