CA1211225A - Relay multiplexing for circuit testers - Google Patents
Relay multiplexing for circuit testersInfo
- Publication number
- CA1211225A CA1211225A CA000476350A CA476350A CA1211225A CA 1211225 A CA1211225 A CA 1211225A CA 000476350 A CA000476350 A CA 000476350A CA 476350 A CA476350 A CA 476350A CA 1211225 A CA1211225 A CA 1211225A
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- test
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Abstract
ABSTRACT OF THE DISCLOSURE
Relay multiplexer circuitry for making a limited number of test channels connectable to a large number of test pins through relays connected to selected test channel nodes and test pin nodes, each test pin node being connectable to a unique combination of test channel nodes within a group of pin nodes, channel nodes and relays.
Relay multiplexer circuitry for making a limited number of test channels connectable to a large number of test pins through relays connected to selected test channel nodes and test pin nodes, each test pin node being connectable to a unique combination of test channel nodes within a group of pin nodes, channel nodes and relays.
Description
~12-1486 ~ S
The invention relates to relay multiplexer circuitry for making channels of a tester connectable to a larye number of nodes of a circuit board being tested.
A printed circuit board (PCB) can be tested by using a tester to provide test signals to nodes of the board under test and analyzing the resulting conditions at the nodes. One method : of testing, in-circuit testing, involves using test pins to contact the nodes of the board under test, providing signals to those nodes that affect the conditions at a given device on the board (typically the nodes connected to leads to the particular device) r analyzing the resulting signals, thereafter testing another device on the board by providing signals to another set of nodes of the board under test, and so on. There typically are a limited number of test channels, owing to their expense, ; connected to a large number of test pins through a relay multi-plexer wired to make each test pin connectable to one of two test channels through two relays. The relays are operated -to connect a test channel to only one test pin at one time, and the total number of test channels and the total number of test pins are usually divided into groups.
In one such prior art relay multiplexer, each group has two test channels made connectable to all sixteen test pins in the group through thirty-two relays; thus, only two test pins of the group can ~e connected at one time without a conflict. In this multiplexer, each group has a unique set of two test channels.
The possibility of conflict can also be reduced by ~' USSN 589,577
The invention relates to relay multiplexer circuitry for making channels of a tester connectable to a larye number of nodes of a circuit board being tested.
A printed circuit board (PCB) can be tested by using a tester to provide test signals to nodes of the board under test and analyzing the resulting conditions at the nodes. One method : of testing, in-circuit testing, involves using test pins to contact the nodes of the board under test, providing signals to those nodes that affect the conditions at a given device on the board (typically the nodes connected to leads to the particular device) r analyzing the resulting signals, thereafter testing another device on the board by providing signals to another set of nodes of the board under test, and so on. There typically are a limited number of test channels, owing to their expense, ; connected to a large number of test pins through a relay multi-plexer wired to make each test pin connectable to one of two test channels through two relays. The relays are operated -to connect a test channel to only one test pin at one time, and the total number of test channels and the total number of test pins are usually divided into groups.
In one such prior art relay multiplexer, each group has two test channels made connectable to all sixteen test pins in the group through thirty-two relays; thus, only two test pins of the group can ~e connected at one time without a conflict. In this multiplexer, each group has a unique set of two test channels.
The possibility of conflict can also be reduced by ~' USSN 589,577
2~S
increasing the number oE relays to increase the "depth", i.e., the number of test channels connectable to each test pin. In the extreme case, making each channel connectable to each pin, one could use all channels and any pins without conflict. The number of relays, however, would be the number of channels times the number of test pins, requiring, for example, 100,000 relays to make one hundred test channels connectable to one thousand test pins.
I have discovered that a limited number o~ test channels can be made connectable through relay multiplexer circuitry to a large number of test pins with decreased possibility of conflict and without increasing the num~er of relays per pin by making each pin connectable to a unique combination of test channels within a group.
Thus, in accordance with a broad aspect of the invention, there is provided relay multiplexer circuitry for selectively connecting channels of a tester to selected test pins electrically connected to nodes of a circuit under test, said pins being larger in number than said channels, said test circuitry compris-ing channel nodes for connection to said channels, pin nodes forconnection to said pins, and relays wired for selectively making at least some o~ said pin nodes connectable to at least two said channels, at least some of said pin nodes, channel nodes and relays being organized in a group such that it is possible to make a connection between any pin node or any channel node of the group with any other pin node or channel node of the group, through multiple or single closed relays, and each said pin node of said ` :,' ~ - \
group is connectable to a unique combination o~ said channel nodes within said yroup, the number of pin nodes P in said group belng greater than the number of channel nodes C in said group.
In preferred embodiments there are two channels per pin; at least some of the channels are included in more than one group; the P pins and C channels within at least part of a group are connected through relays in a fully combinatorial manner, i.e., every possible combination of C channels is used, and P = C'/D'(C-D)!, where D equals the depth; and the -test pins are assigned to a particular device on a board under test such that each channel i5 used no more than the depth, one pin being assigned to a device not being used.
The structure and operation o the presently preferred embodiment of the invention will now be described after first briefly describing the drawings.
Drawings Figure 1 is a functional block diagram showing relay multiplexer circuitry accGrding to the invention connected to a Pcs being tested and driver/de-tectors for tester channels.
Figure 2 is a functional block diagram of a channel driver/detector.
Figure 3 is a schematic showing the wiring of the relays between channel nodes and pin nodes in said relay multi-plexer circuitry.
Figure 4 is a schematic of a relay of said relay multiplexer circuitry.
Figure 5 is a diagrammatic elevation of a board under 2~25 test contacted by test pins connected to specified pin nodes of said relay multiplexer circuitry.
Figure 6 is a diagram showing a method of assigning channel combinations to test pins and devices under test.
Structure Referring to Figure 1, there is shown relay multiplexer 10 having 126 test pin nodes 12, connected to PCB under test 13 by 126 pin lines 15, and twelve test channel nodes 14, connec-ted to twelve channel driver/detectors 16 for channels A to L via channel lines 18. Channel nodes 14 are connected to pin nodes 12 via relays in multiplexer 10 con~rolled by relay controller 20. Channel driver/detectors 16 and relay controller 20 are connected to test controller 22 by hus 24.
Referring to Figure 2, there is shown a channel drive/
detector 16. It includes driver 26 and detector 28 connected in parallel to switch 29 connected to channel line 18. It also includes switch 30 for connecting line 18 to analog signal line 31. Analog signal line 31, driver 26, and detector 28 are all connected to bus 24.
Referring to Figure 3, showing the wiring of relay multiplexer 10, it is seen that there are two groups 32, 34 of pin nodes 12 and channel nodes 14. Group 32 includes test pin nodes numbered 1 to 66, and group 34 includes test pin nodes numbered 67 to 126. Within each group, each pin node 12 is connectable to a unique combination of two channel nodes 14 through two relays 36 (single form A relays). As is seen in Figure 4, each relay 36 makes a channel node 14 connectable to a ~2.1l~ 2S
pin node 12 by a normally open switch 38 controlled by TTL
signals ~rom controller 20 (via means not shown). In group 32 or group 34 it is possible to make a connection between any pin node or any channel node of the group with any other pin node or channel node of the group, through multiple or single closed relays; in typical operation, however, at any given time, each channel node would be connected to no more than one pin node, and each pin node would be connected to no more than one channel node~
In group 32, the combinations of channel nodes 14 are assigned to pin nodes 12 in a fully combinatorial manner; i.e., every possible unique combination of two of the twelve channels A to L is shown in Figure 3. Thus, the total number of pin nodes (sixty-six) equals C'/Di(C-D)', where C equals the number of channels (twelve), and D equals the depth (two). In group 32 each channel is connectable to eleven test pin nodes.
The assignment of unique combinations of two channel nodes for the test pin nodes in ~roup 34 is identical to that in group 32 except that group 34 does not have combinations corres-ponding to those for pin nodes numbered 21, 25, 33~ 38, 48, 56.
(Thus the combinations of channels are not fully combinatorial in group 34 ) These six combinations have not been duplicated because only 126 (and not 132) pin nodes are being used in relay multiplexer 10. An X on the Figure 3 schematic indicates the absence from group 34 of a combination that is used in group 32.
These combinations were picked because each channel ~ to L is represented once, so that in group 34 there are ten pin nodes s assigned to each of twelve channels ~ to L, instead of, e.g., nine pins assigned to one channel and eleven to another. This even distribution of pins per channel acts ko reduce conflict, as does the re~uirement that each pin node in a group be connect-able to a unique combination of channel nodes, as is discussed below.
Referring to Fiyure 5, i-t is seen that PCB under test 14 includes a plurality of electronic devices 40. As is illustrated somewhat diayrammati.cally in Figure 5 for a single device 40, nodes 42 at the leads to device 40 are contacted by spring-loaded test pins 44, connected to the indicated eleven pin nodes 12 (those numbered 1, 3, 6, 10, 15, 21, 28, 36, 45, 55, 66). As can be seen from Figure 3, the indicated eleven pin nodes and another pin node 12, the one numbered 56, have been selected so that each channel has been used no more than -twice;
thus all channels can be used to test device 40 without conflict.
Operation In operation, if PCB under test 13 has more devices 40 and nodes 42 than can be driven by the twelve channels A to L and 126 test pins connected to relay multiplexer 10, additional groups of twelve channel driver/detectors 16, relay multiplexers 10 and relay controllers 20, are provided and connected to test controller 22 over bus 24.
Test pins 44 are mounted on a support in position to contact all nodes 42 of PCB under test 13. In wiring test pins 44 to pin nodes 12, the pin nodes are assigned so that each channel is used no more than twice in the combinations of channels associated with the pin nodes connected to a single device 40. One pin node that is assigned to a device 40 is not initially wired but is reserved.
The diagram of combinations in Figure 6 can be used to assign pin nodes. For example, in assigning pin nodes to the test pins 44 shown wired in Figure 5, one picks channel combina-tion group 46 to obtain combina~ions such that each channel is used only twice, and refers to Figure 3 to identify the numbers of the corresponding pin nodes having these combinations. One combination of group 46 that is not used is the combination of channels A and L, the combination for the pin node numbered 56.
By using only eleven pins in a channel combination group, any channel can be freed for use by any remaining pin to accommodate, without conflict, subsequent engineering change orders that might affect nodes 42 and require providing another test pin to a device 40.
In wiring further pin nodes 12 to test pins 44 for further devices 40, the test pin nodes associates with channel combination groups 48 to 54 (Figure 6) can be used to identify pin nodes so that for each device 40, each channel is used no more than twice.
In making these test pin to pin node wiring connections~ the possibility of conflict (i.e., of a channel having to be connected to more than one test pin at the same time) is smaller than with prior relay multiplexers having comparable numbers of channels and relays, because pin nodes 12 within group 32 or 34 are connectable to unique combinations of s channel nodes 14. There is less chance that both channels for a pin node 12 will have to be used by other pin nodes than there would be, for example, if sixteen pin nodes 12 were all connect-able to the same two channel nodes 14.
The various devices 40 on PCB under test 13 are tested by providing inputs to test pins 44 contacting those nodes 42 on board 13 that are electrically common to leads of a given device 40 on the board, while other devices 40 on the board are disabled by providing the appropriate signals, and sensing the resulting conditions at the nodes common to leads to the device 40 being tested. In testing individual devices 40, selected channels A-L are connected to selected test pins 44 by activating the appropriate relays 36 by relay controller 20, operating under relay control signals provided by controller 22 over bus 24.
Test controller 22 also provides test control signals over bus 24 to operate channel drivers 26 to provide test signal inputs and detectors 28 to detect the test outputs while switch 29 is ; closed and switch 30 is open. When switch 30 is closed, analog signals are provided to test pins 44. The test outputs are provided to test controller 22, and compared with expected test outputs. After one device 40 has been tested, another device 40 on the board is tested by activating another set of test pins 44 and so on.
Other Embodimen-ts Other embodiments of the invention are within the scope of the following claims. For example, if less than sixty pins are to be used in group 34, additional channel combinations are 13L;22S
picked so that the number of pins per channel or each channel is uniform. For example, if between seven and twelve of the sixty-six total possible combinations would not be used (i.e., if it was desired to have bekween fifty-four and fifky-nine pins), each channel would be represented no more than twice in the combinations removed from the fully combinatorial set shown in group 32. (In this case the pins per channel for each channel would be either -ten or eleven.) If between thirteen and eighteen of the sixty six total would not be used, each channel would be represented no more than three times in the combinations removed from the fully combinatorial set (in this case the pins per channel would be either nine or ten), and so on. This substantial uniformity of pins assigned to each channel results in efficient use of the channels and relays to avoid conflict;
e.g., if one merely used pin nodes numbered 1 to 60, channel L
would only be connectable to five pins, whlle the other channels would be connectable to eleven or ten pins, an inefficient use of channel L. While in some instances the pins per channel for each channel could vary by more than one and still be acceptable, preferably the pins per channel for each channel of a group should vary by no more than one, and most preferably the number should be the same for all channels.
The Figure 6 diagram can be used to identify channel combinations to be deleted from the fully combinatorial set. In Figure 6, the sixty-six unique channel combinations for twelve channels A - L and a depth of two are divided into five groups 46 to 54 of twelve channel combinations and one group 56 of six 22S;
channel combinations. In group 56 each channel is represented once, and in each of groups 46 to 5~ each channel is represented twice. Thus, if one were to use between sixty and sixty-five pins, the channel combinations of group 56 could be selected for deletion. (The six combinations not used in group 34 are ; different from but equivalent to those in group 56.) I-f one were to use between fifty-four and fifty--nine pins, the combinations of any one of groups 46 to 54 could be selected for deletion. If one were to use between forty-elght and fifty-three pins, the combinations of group 56 and any one of groups 46 to 54 could be selected for dele-tion, and so on.
Also, when using a second group to add pins for connection to channels already in a first group having a fully combinatorial set of channel combinations, one could assign channels to the new pins so that the number of pins per channel in the second group is substantially uniform. In this way the overall pins per channel values would be substantially uniform, providing efficient use of channels and promoting reduced chance of conflict.
Also, the principles described herein can be applied to depths larger than two and other numbers of channels in a group.
increasing the number oE relays to increase the "depth", i.e., the number of test channels connectable to each test pin. In the extreme case, making each channel connectable to each pin, one could use all channels and any pins without conflict. The number of relays, however, would be the number of channels times the number of test pins, requiring, for example, 100,000 relays to make one hundred test channels connectable to one thousand test pins.
I have discovered that a limited number o~ test channels can be made connectable through relay multiplexer circuitry to a large number of test pins with decreased possibility of conflict and without increasing the num~er of relays per pin by making each pin connectable to a unique combination of test channels within a group.
Thus, in accordance with a broad aspect of the invention, there is provided relay multiplexer circuitry for selectively connecting channels of a tester to selected test pins electrically connected to nodes of a circuit under test, said pins being larger in number than said channels, said test circuitry compris-ing channel nodes for connection to said channels, pin nodes forconnection to said pins, and relays wired for selectively making at least some o~ said pin nodes connectable to at least two said channels, at least some of said pin nodes, channel nodes and relays being organized in a group such that it is possible to make a connection between any pin node or any channel node of the group with any other pin node or channel node of the group, through multiple or single closed relays, and each said pin node of said ` :,' ~ - \
group is connectable to a unique combination o~ said channel nodes within said yroup, the number of pin nodes P in said group belng greater than the number of channel nodes C in said group.
In preferred embodiments there are two channels per pin; at least some of the channels are included in more than one group; the P pins and C channels within at least part of a group are connected through relays in a fully combinatorial manner, i.e., every possible combination of C channels is used, and P = C'/D'(C-D)!, where D equals the depth; and the -test pins are assigned to a particular device on a board under test such that each channel i5 used no more than the depth, one pin being assigned to a device not being used.
The structure and operation o the presently preferred embodiment of the invention will now be described after first briefly describing the drawings.
Drawings Figure 1 is a functional block diagram showing relay multiplexer circuitry accGrding to the invention connected to a Pcs being tested and driver/de-tectors for tester channels.
Figure 2 is a functional block diagram of a channel driver/detector.
Figure 3 is a schematic showing the wiring of the relays between channel nodes and pin nodes in said relay multi-plexer circuitry.
Figure 4 is a schematic of a relay of said relay multiplexer circuitry.
Figure 5 is a diagrammatic elevation of a board under 2~25 test contacted by test pins connected to specified pin nodes of said relay multiplexer circuitry.
Figure 6 is a diagram showing a method of assigning channel combinations to test pins and devices under test.
Structure Referring to Figure 1, there is shown relay multiplexer 10 having 126 test pin nodes 12, connected to PCB under test 13 by 126 pin lines 15, and twelve test channel nodes 14, connec-ted to twelve channel driver/detectors 16 for channels A to L via channel lines 18. Channel nodes 14 are connected to pin nodes 12 via relays in multiplexer 10 con~rolled by relay controller 20. Channel driver/detectors 16 and relay controller 20 are connected to test controller 22 by hus 24.
Referring to Figure 2, there is shown a channel drive/
detector 16. It includes driver 26 and detector 28 connected in parallel to switch 29 connected to channel line 18. It also includes switch 30 for connecting line 18 to analog signal line 31. Analog signal line 31, driver 26, and detector 28 are all connected to bus 24.
Referring to Figure 3, showing the wiring of relay multiplexer 10, it is seen that there are two groups 32, 34 of pin nodes 12 and channel nodes 14. Group 32 includes test pin nodes numbered 1 to 66, and group 34 includes test pin nodes numbered 67 to 126. Within each group, each pin node 12 is connectable to a unique combination of two channel nodes 14 through two relays 36 (single form A relays). As is seen in Figure 4, each relay 36 makes a channel node 14 connectable to a ~2.1l~ 2S
pin node 12 by a normally open switch 38 controlled by TTL
signals ~rom controller 20 (via means not shown). In group 32 or group 34 it is possible to make a connection between any pin node or any channel node of the group with any other pin node or channel node of the group, through multiple or single closed relays; in typical operation, however, at any given time, each channel node would be connected to no more than one pin node, and each pin node would be connected to no more than one channel node~
In group 32, the combinations of channel nodes 14 are assigned to pin nodes 12 in a fully combinatorial manner; i.e., every possible unique combination of two of the twelve channels A to L is shown in Figure 3. Thus, the total number of pin nodes (sixty-six) equals C'/Di(C-D)', where C equals the number of channels (twelve), and D equals the depth (two). In group 32 each channel is connectable to eleven test pin nodes.
The assignment of unique combinations of two channel nodes for the test pin nodes in ~roup 34 is identical to that in group 32 except that group 34 does not have combinations corres-ponding to those for pin nodes numbered 21, 25, 33~ 38, 48, 56.
(Thus the combinations of channels are not fully combinatorial in group 34 ) These six combinations have not been duplicated because only 126 (and not 132) pin nodes are being used in relay multiplexer 10. An X on the Figure 3 schematic indicates the absence from group 34 of a combination that is used in group 32.
These combinations were picked because each channel ~ to L is represented once, so that in group 34 there are ten pin nodes s assigned to each of twelve channels ~ to L, instead of, e.g., nine pins assigned to one channel and eleven to another. This even distribution of pins per channel acts ko reduce conflict, as does the re~uirement that each pin node in a group be connect-able to a unique combination of channel nodes, as is discussed below.
Referring to Fiyure 5, i-t is seen that PCB under test 14 includes a plurality of electronic devices 40. As is illustrated somewhat diayrammati.cally in Figure 5 for a single device 40, nodes 42 at the leads to device 40 are contacted by spring-loaded test pins 44, connected to the indicated eleven pin nodes 12 (those numbered 1, 3, 6, 10, 15, 21, 28, 36, 45, 55, 66). As can be seen from Figure 3, the indicated eleven pin nodes and another pin node 12, the one numbered 56, have been selected so that each channel has been used no more than -twice;
thus all channels can be used to test device 40 without conflict.
Operation In operation, if PCB under test 13 has more devices 40 and nodes 42 than can be driven by the twelve channels A to L and 126 test pins connected to relay multiplexer 10, additional groups of twelve channel driver/detectors 16, relay multiplexers 10 and relay controllers 20, are provided and connected to test controller 22 over bus 24.
Test pins 44 are mounted on a support in position to contact all nodes 42 of PCB under test 13. In wiring test pins 44 to pin nodes 12, the pin nodes are assigned so that each channel is used no more than twice in the combinations of channels associated with the pin nodes connected to a single device 40. One pin node that is assigned to a device 40 is not initially wired but is reserved.
The diagram of combinations in Figure 6 can be used to assign pin nodes. For example, in assigning pin nodes to the test pins 44 shown wired in Figure 5, one picks channel combina-tion group 46 to obtain combina~ions such that each channel is used only twice, and refers to Figure 3 to identify the numbers of the corresponding pin nodes having these combinations. One combination of group 46 that is not used is the combination of channels A and L, the combination for the pin node numbered 56.
By using only eleven pins in a channel combination group, any channel can be freed for use by any remaining pin to accommodate, without conflict, subsequent engineering change orders that might affect nodes 42 and require providing another test pin to a device 40.
In wiring further pin nodes 12 to test pins 44 for further devices 40, the test pin nodes associates with channel combination groups 48 to 54 (Figure 6) can be used to identify pin nodes so that for each device 40, each channel is used no more than twice.
In making these test pin to pin node wiring connections~ the possibility of conflict (i.e., of a channel having to be connected to more than one test pin at the same time) is smaller than with prior relay multiplexers having comparable numbers of channels and relays, because pin nodes 12 within group 32 or 34 are connectable to unique combinations of s channel nodes 14. There is less chance that both channels for a pin node 12 will have to be used by other pin nodes than there would be, for example, if sixteen pin nodes 12 were all connect-able to the same two channel nodes 14.
The various devices 40 on PCB under test 13 are tested by providing inputs to test pins 44 contacting those nodes 42 on board 13 that are electrically common to leads of a given device 40 on the board, while other devices 40 on the board are disabled by providing the appropriate signals, and sensing the resulting conditions at the nodes common to leads to the device 40 being tested. In testing individual devices 40, selected channels A-L are connected to selected test pins 44 by activating the appropriate relays 36 by relay controller 20, operating under relay control signals provided by controller 22 over bus 24.
Test controller 22 also provides test control signals over bus 24 to operate channel drivers 26 to provide test signal inputs and detectors 28 to detect the test outputs while switch 29 is ; closed and switch 30 is open. When switch 30 is closed, analog signals are provided to test pins 44. The test outputs are provided to test controller 22, and compared with expected test outputs. After one device 40 has been tested, another device 40 on the board is tested by activating another set of test pins 44 and so on.
Other Embodimen-ts Other embodiments of the invention are within the scope of the following claims. For example, if less than sixty pins are to be used in group 34, additional channel combinations are 13L;22S
picked so that the number of pins per channel or each channel is uniform. For example, if between seven and twelve of the sixty-six total possible combinations would not be used (i.e., if it was desired to have bekween fifty-four and fifky-nine pins), each channel would be represented no more than twice in the combinations removed from the fully combinatorial set shown in group 32. (In this case the pins per channel for each channel would be either -ten or eleven.) If between thirteen and eighteen of the sixty six total would not be used, each channel would be represented no more than three times in the combinations removed from the fully combinatorial set (in this case the pins per channel would be either nine or ten), and so on. This substantial uniformity of pins assigned to each channel results in efficient use of the channels and relays to avoid conflict;
e.g., if one merely used pin nodes numbered 1 to 60, channel L
would only be connectable to five pins, whlle the other channels would be connectable to eleven or ten pins, an inefficient use of channel L. While in some instances the pins per channel for each channel could vary by more than one and still be acceptable, preferably the pins per channel for each channel of a group should vary by no more than one, and most preferably the number should be the same for all channels.
The Figure 6 diagram can be used to identify channel combinations to be deleted from the fully combinatorial set. In Figure 6, the sixty-six unique channel combinations for twelve channels A - L and a depth of two are divided into five groups 46 to 54 of twelve channel combinations and one group 56 of six 22S;
channel combinations. In group 56 each channel is represented once, and in each of groups 46 to 5~ each channel is represented twice. Thus, if one were to use between sixty and sixty-five pins, the channel combinations of group 56 could be selected for deletion. (The six combinations not used in group 34 are ; different from but equivalent to those in group 56.) I-f one were to use between fifty-four and fifty--nine pins, the combinations of any one of groups 46 to 54 could be selected for deletion. If one were to use between forty-elght and fifty-three pins, the combinations of group 56 and any one of groups 46 to 54 could be selected for dele-tion, and so on.
Also, when using a second group to add pins for connection to channels already in a first group having a fully combinatorial set of channel combinations, one could assign channels to the new pins so that the number of pins per channel in the second group is substantially uniform. In this way the overall pins per channel values would be substantially uniform, providing efficient use of channels and promoting reduced chance of conflict.
Also, the principles described herein can be applied to depths larger than two and other numbers of channels in a group.
Claims (7)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. Relay multiplexer circuitry for selectively connecting channels of a tester to selected test pins electrically connected to nodes of a circuit under test, said pins being larger in number than said channels, said test circuitry comprising channel nodes for connection to said channels, pin nodes for connection to said pins, and relays wired for selectively making at least some of said pin nodes connectable to at least two said channels, at least some of said pin nodes, channel nodes and relays being organized in a group such that it is possible to make a connection between any pin node or any channel node of the group with any other pin node or channel node of the group, through multiple or single closed relays, and each said pin node of said group is connectable to a unique combination of said channel nodes within said group, the number of pin nodes P in said group being greater than the number of channel nodes C in said group.
2. The circuitry of claim 1 wherein said unique combina-tions of channel nodes in said group are fully combinatorial.
3. The circuitry of claim 1 wherein said unique combina-tions of channel nodes in said group include less than the fully combinatorial set of combinations.
4. The circuitry of claim 1 wherein there are two channels per pin.
5. The circuitry of claim 1 wherein at least some of said channels are connectable to more than one group.
6. Testing apparatus comprising the circuitry of claim 1 and test pins mounted on a support and spatially arranged to contact nodes of a printed circuit board under test, said test pins being electrically connected to said pin nodes, said pin nodes connected to test pins for nodes for a given electronic device on said printed circuit board having associated combina-tions of channels such that each said channel in said group is represented in said associated combinations no more than the number of relays per pin, and there are channels represented in said associated combinations less than said number of relays per pin, to accommodate design changes of said circuit under test without conflict.
7. A method of testing printed circuit boards using said relay multiplexer circuitry of claim 1, said method comprising providing test pins mounted on a support and spatially arranged to contact nodes of a printed circuit board under test, and wiring said test pins to said pin nodes, said pin nodes connected to test pins for nodes for a given electronic device on said printed circuit board having associated combinations of channels such that each said channel in said group is represented in said associated combinations no more than the number of relays per pin, there being channels represented in said associated combinations less than said number of relays per pin, to accommodate design changes of said circuit under test without conflict.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US58957784A | 1984-03-14 | 1984-03-14 | |
| US589,577 | 1984-03-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1211225A true CA1211225A (en) | 1986-09-09 |
Family
ID=24358595
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000476350A Expired CA1211225A (en) | 1984-03-14 | 1985-03-13 | Relay multiplexing for circuit testers |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1211225A (en) |
-
1985
- 1985-03-13 CA CA000476350A patent/CA1211225A/en not_active Expired
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